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authorJonathan Gray <jsg@jsg.id.au>2013-02-27 02:25:48 +1100
committerJonathan Gray <jsg@jsg.id.au>2013-02-27 02:25:48 +1100
commit083a73105b2b3a5e16e7d82d53ce14aaa45a3839 (patch)
treeae7b13082793a5bb890656cc9aa2f6cf56acf0f6 /sys/dev
parent98c05c52b1b11cf59051ccaf42d906e34aeda7a0 (diff)
pte bits have changed on gen6+, for now always set to uncached
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/pci/agp_i810.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/sys/dev/pci/agp_i810.c b/sys/dev/pci/agp_i810.c
index 4d6f878b0ef..5b14a1162e5 100644
--- a/sys/dev/pci/agp_i810.c
+++ b/sys/dev/pci/agp_i810.c
@@ -60,6 +60,10 @@
/* Memory is snooped, must not be accessed through gtt from the cpu. */
#define INTEL_COHERENT 0x6
+#define GEN6_PTE_UNCACHED (1 << 1)
+#define GEN6_PTE_CACHE_LLC (2 << 1)
+#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
+
enum {
CHIP_NONE = 0, /* not integrated graphics */
CHIP_I810 = 1, /* i810/i815 */
@@ -731,8 +735,16 @@ agp_i810_bind_page(void *sc, bus_addr_t offset, paddr_t physical, int flags)
* COHERENT mappings mean set the snoop bit. this should never be
* accessed by the gpu through the gtt.
*/
- if (flags & BUS_DMA_COHERENT)
- physical |= INTEL_COHERENT;
+ switch (isc->chiptype) {
+ case CHIP_SANDYBRIDGE:
+ case CHIP_IVYBRIDGE:
+ physical |= GEN6_PTE_UNCACHED;
+ break;
+ default:
+ if (flags & BUS_DMA_COHERENT)
+ physical |= INTEL_COHERENT;
+ break;
+ }
intagp_write_gtt(isc, offset - isc->isc_apaddr, physical);
}