Move GEM initialization code into its own function like Linux has.

4 files changed, 74 insertions, 58 deletions

diff --git a/sys/dev/pci/drm/i915/i915_drv.c b/sys/dev/pci/drm/i915/i915_drv.c
index 2ee0c7c97ab..592d7077280 100644
--- a/sys/dev/pci/drm/i915/i915_drv.c
+++ b/sys/dev/pci/drm/i915/i915_drv.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_drv.c,v 1.21 2013/04/18 20:19:32 kettenis Exp $ */
+/* $OpenBSD: i915_drv.c,v 1.22 2013/04/21 14:41:26 kettenis Exp $ */
 /*
  * Copyright (c) 2008-2009 Owain G. Ainsworth <oga@openbsd.org>
  *
@@ -894,46 +894,11 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
 	}
 
 	/* GEM init */
-	INIT_LIST_HEAD(&dev_priv->mm.active_list);
-	INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
-	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
-	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
-	for (i = 0; i < I915_NUM_RINGS; i++)
-		init_ring_lists(&dev_priv->ring[i]);
-	timeout_set(&dev_priv->mm.retire_timer, inteldrm_timeout, dev_priv);
 	timeout_set(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, dev_priv);
 	dev_priv->next_seqno = 1;
 	dev_priv->mm.suspended = 1;
 	dev_priv->error_completion = 0;
 
-	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
-	if (IS_GEN3(dev)) {
-		u_int32_t tmp = I915_READ(MI_ARB_STATE);
-		if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
-			/*
-			 * arb state is a masked write, so set bit + bit
-			 * in mask
-			 */
-			I915_WRITE(MI_ARB_STATE,
-			           _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
-		}
-	}
-
-	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
-
-	/* Old X drivers will take 0-2 for front, back, depth buffers */
-	if (!drm_core_check_feature(dev, DRIVER_MODESET))
-		dev_priv->fence_reg_start = 3;
-
-	if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) ||
-	    IS_I945GM(dev) || IS_G33(dev))
-		dev_priv->num_fence_regs = 16;
-	else
-		dev_priv->num_fence_regs = 8;
-
-	/* Initialise fences to zero, else on some macs we'll get corruption */
-	i915_gem_reset_fences(dev);
-
 	if (pci_find_device(&bpa, inteldrm_gmch_match) == 0) {
 		printf(": can't find GMCH\n");
 		return;
@@ -963,12 +928,10 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
 		}
 	}
 
-	i915_gem_detect_bit_6_swizzle(dev_priv, &bpa);
-
-	dev_priv->mm.interruptible = true;
+        /* Try to make sure MCHBAR is enabled before poking at it */
+        intel_setup_mchbar(dev_priv, &bpa);
 
-	printf("%s: %s\n", dev_priv->dev.dv_xname,
-	    pci_intr_string(pa->pa_pc, dev_priv->ih));
+	i915_gem_load(dev);
 
 	mtx_init(&dev_priv->irq_lock, IPL_TTY);
 	mtx_init(&dev_priv->rps.lock, IPL_NONE);
diff --git a/sys/dev/pci/drm/i915/i915_drv.h b/sys/dev/pci/drm/i915/i915_drv.h
index 6e526b8bccd..9bfd4fd869a 100644
--- a/sys/dev/pci/drm/i915/i915_drv.h
+++ b/sys/dev/pci/drm/i915/i915_drv.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: i915_drv.h,v 1.14 2013/04/17 20:04:04 kettenis Exp $ */
+/* $OpenBSD: i915_drv.h,v 1.15 2013/04/21 14:41:26 kettenis Exp $ */
 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  */
 /*
@@ -643,6 +643,12 @@ struct inteldrm_softc {
 		/** List of all objects in gtt_space. Used to restore gtt
 		 * mappings on resume */
 		struct list_head bound_list;
+		/**
+		 * List of objects which are not bound to the GTT (thus
+		 * are idle and not used by the GPU) but still have
+		 * (presumably uncached) pages still attached.
+		 */
+		struct list_head unbound_list;
 
 		/**
 		 * List of objects currently involved in rendering from the
@@ -1176,8 +1182,7 @@ int i915_gem_evict_something(struct inteldrm_softc *, size_t);
 int i915_gem_evict_inactive(struct inteldrm_softc *);
 
 /* i915_gem_tiling.c */
-void	i915_gem_detect_bit_6_swizzle(struct inteldrm_softc *, 
-	    struct pci_attach_args *);
+void	i915_gem_detect_bit_6_swizzle(struct drm_device *);
 void	i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *);
 void	i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *);
 int	i915_gem_swizzle_page(struct vm_page *page);
@@ -1226,6 +1231,7 @@ void i915_gem_reset(struct drm_device *);
 void i915_gem_clflush_object(struct drm_i915_gem_object *);
 void i915_gem_release(struct drm_device *, struct drm_file *);
 void i915_gem_release_mmap(struct drm_i915_gem_object *);
+void i915_gem_load(struct drm_device *dev);
 
 uint32_t
 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
diff --git a/sys/dev/pci/drm/i915/i915_gem.c b/sys/dev/pci/drm/i915/i915_gem.c
index 3ef9eda3668..81c47c401ae 100644
--- a/sys/dev/pci/drm/i915/i915_gem.c
+++ b/sys/dev/pci/drm/i915/i915_gem.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: i915_gem.c,v 1.11 2013/04/17 20:04:04 kettenis Exp $	*/
+/*	$OpenBSD: i915_gem.c,v 1.12 2013/04/21 14:41:26 kettenis Exp $	*/
 /*
  * Copyright (c) 2008-2009 Owain G. Ainsworth <oga@openbsd.org>
  *
@@ -3207,7 +3207,61 @@ init_ring_lists(struct intel_ring_buffer *ring)
 	INIT_LIST_HEAD(&ring->request_list);
 }
 
-// i915_gem_load
+void
+i915_gem_load(struct drm_device *dev)
+{
+	int i;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	INIT_LIST_HEAD(&dev_priv->mm.active_list);
+	INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
+	INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
+	INIT_LIST_HEAD(&dev_priv->mm.bound_list);
+	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
+	for (i = 0; i < I915_NUM_RINGS; i++)
+		init_ring_lists(&dev_priv->ring[i]);
+	for (i = 0; i < I915_MAX_NUM_FENCES; i++)
+		INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
+	timeout_set(&dev_priv->mm.retire_timer, inteldrm_timeout, dev_priv);
+#if 0
+	init_completion(&dev_priv->error_completion);
+#else
+	dev_priv->error_completion = 0;
+#endif
+
+	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
+	if (IS_GEN3(dev)) {
+		I915_WRITE(MI_ARB_STATE,
+			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
+	}
+
+	dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
+
+	/* Old X drivers will take 0-2 for front, back, depth buffers */
+	if (!drm_core_check_feature(dev, DRIVER_MODESET))
+		dev_priv->fence_reg_start = 3;
+
+	if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+		dev_priv->num_fence_regs = 16;
+	else
+		dev_priv->num_fence_regs = 8;
+
+	/* Initialize fence registers to zero */
+	i915_gem_reset_fences(dev);
+
+	i915_gem_detect_bit_6_swizzle(dev);
+#if 0
+	init_waitqueue_head(&dev_priv->pending_flip_queue);
+#endif
+
+	dev_priv->mm.interruptible = true;
+
+#if 0
+	dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
+	dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
+	register_shrinker(&dev_priv->mm.inactive_shrinker);
+#endif
+}
 
 /*
  * Create a physically contiguous memory object for this object
diff --git a/sys/dev/pci/drm/i915/i915_gem_tiling.c b/sys/dev/pci/drm/i915/i915_gem_tiling.c
index d165fbe5a24..dc108c62aaf 100644
--- a/sys/dev/pci/drm/i915/i915_gem_tiling.c
+++ b/sys/dev/pci/drm/i915/i915_gem_tiling.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: i915_gem_tiling.c,v 1.2 2013/03/29 05:15:42 jsg Exp $	*/
+/*	$OpenBSD: i915_gem_tiling.c,v 1.3 2013/04/21 14:41:26 kettenis Exp $	*/
 /*
  * Copyright (c) 2008-2009 Owain G. Ainsworth <oga@openbsd.org>
  *
@@ -105,13 +105,11 @@
  * access through main memory.
  */
 void
-i915_gem_detect_bit_6_swizzle(struct inteldrm_softc *dev_priv,
-    struct pci_attach_args *bpa)
+i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 {
-	struct drm_device	*dev = (struct drm_device *)dev_priv->drmdev;
-	uint32_t		 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-	uint32_t		 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
-	int			 need_disable;
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
 	if (IS_VALLEYVIEW(dev)) {
 		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
@@ -150,9 +148,6 @@ i915_gem_detect_bit_6_swizzle(struct inteldrm_softc *dev_priv,
 	} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
 		uint32_t dcc;
 
-		/* try to enable MCHBAR, a lot of biosen disable it */
-		need_disable = intel_setup_mchbar(dev_priv, bpa);
-
 		/* On 915-945 and GM965, channel interleave by the CPU is
 		 * determined by DCC.  The CPU will alternate based on bit 6
 		 * in interleaved mode, and the GPU will then also alternate
@@ -191,8 +186,6 @@ i915_gem_detect_bit_6_swizzle(struct inteldrm_softc *dev_priv,
 			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 		}
-
-		intel_teardown_mchbar(dev_priv, bpa, need_disable);
 	} else {
 		/* The 965, G33, and newer, have a very flexible memory
 		 * configuration. It will enable dual-channel mode