athn(4) is going to support a new family of Atheros 802.11n

chips (AR9003), which differs from the currently supported
families (AR5008, AR9001 and AR9002).

The main differences (from a driver point of view) are:

* DMA:
Tx and Rx descriptors have changed.
A single Tx descriptor can now reference up to 4 scatter/gather
DMA segments.
There is now a DMA ring for reporting Tx status with separate
Tx status descriptors (this ring is used to report Tx status for
all the Tx FIFOs).
Rx status descriptors are now put at the beginning of Rx buffers
and do not need to be allocated separately from buffers.
There are two Rx FIFOs (low priority and high priority) instead
of one.

* ROM:
The AR9003 family uses OTP-ROM instead of EEPROM.
Reading the ROM is totally insane since vendors can provide only
the chunks of ROM that differ from a default image (and thus the
default image has to be stored in the driver).
This is referenced as "compressed ROM" in the Linux driver, though
there is no real compression involved, at least for the moment.

* PHY registers:
All PHY registers have changed.
Some registers offsets do not fit on 16 bits anymore, but
since they are 32-bit aligned, we can still make them fit on
16 bits to save .rodata space in initialization tables.

* MAC registers:
Some MAC registers offsets have changed (GPIO, interrupt masks)
which is quite annoying (though ~98% remain the same.)

* Initialization values:
Initialization values are now split in mac/soc/bb/radio blocks
and pre/core/post phases in the Linux driver.  I have chosen to
not go that road and merge these blocks in modal and non-modal
initialization values (similar to the other families).
The initialization order remains exactly the same as the Linux
driver though.

To manage these differences, I have split athn.c in two backends:
ar5008.c contains the bits that are specific to the AR5008,
AR9001 and AR9002 families (used by ar5416.c, ar9280.c,
ar9285.c and ar9287.c) and that were previously in athn.c.

ar9003.c contains the bits that are specific to the new
AR9003 family (used by ar9380.c only for now.)

I have introduced a thin hardware abstraction layer (actually
a set of pointers to functions) that is used in athn.c.
My intent is to keep this abstraction layer as thin as possible
and not to create another ugly pile of abstraction layers a la
MadWifi.

I think I've managed to keep things sane, probably at the expense
of duplicating some code in both ar5008.c and ar9003.c, but at
least we do not have to dig through layers and layers of virtual
descriptors to figure out what is mapped to the hardware.

Tested for non-regression on various AR5416 (sparc64+i386), AR9281
and AR9285 (i386 only) adapters.
AR9380 part is not tested (hardware is not available to the general
public yet).

Committed over my AR9285 2.0.

16 files changed, 9156 insertions, 3650 deletions

diff --git a/sys/dev/ic/ar5008.c b/sys/dev/ic/ar5008.c
new file mode 100644
index 00000000000..d7651f9b1bb
--- /dev/null
+++ b/sys/dev/ic/ar5008.c
@@ -0,0 +1,2459 @@
+/*	$OpenBSD: ar5008.c,v 1.1 2010/05/10 17:44:21 damien Exp $	*/
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines common to AR5008, AR9001 and AR9002 families.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/timeout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+#include <sys/stdint.h>	/* uintptr_t */
+
+#include <machine/bus.h>
+#include <machine/endian.h>
+#include <machine/intr.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/if_ether.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/ar5008reg.h>
+
+int	ar5008_attach(struct athn_softc *);
+int	ar5008_read_rom_word(struct athn_softc *, uint32_t, uint16_t *);
+int	ar5008_read_rom(struct athn_softc *);
+void	ar5008_swap_rom(struct athn_softc *);
+int	ar5008_gpio_read(struct athn_softc *, int);
+void	ar5008_gpio_write(struct athn_softc *, int, int);
+void	ar5008_gpio_config_input(struct athn_softc *, int);
+void	ar5008_gpio_config_output(struct athn_softc *, int, int);
+void	ar5008_rfsilent_init(struct athn_softc *);
+int	ar5008_dma_alloc(struct athn_softc *);
+void	ar5008_dma_free(struct athn_softc *);
+int	ar5008_tx_alloc(struct athn_softc *);
+void	ar5008_tx_free(struct athn_softc *);
+int	ar5008_rx_alloc(struct athn_softc *);
+void	ar5008_rx_free(struct athn_softc *);
+void	ar5008_rx_enable(struct athn_softc *);
+void	ar5008_rx_radiotap(struct athn_softc *, struct mbuf *,
+	    struct ar_rx_desc *);
+void	ar5008_rx_intr(struct athn_softc *);
+int	ar5008_tx_process(struct athn_softc *, int);
+void	ar5008_tx_intr(struct athn_softc *);
+int	ar5008_intr(struct athn_softc *);
+int	ar5008_tx(struct athn_softc *, struct mbuf *, struct ieee80211_node *);
+void	ar5008_set_rf_mode(struct athn_softc *, struct ieee80211_channel *);
+int	ar5008_rf_bus_request(struct athn_softc *);
+void	ar5008_rf_bus_release(struct athn_softc *);
+void	ar5008_set_phy(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar5008_set_delta_slope(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar5008_enable_antenna_diversity(struct athn_softc *);
+void	ar5008_init_baseband(struct athn_softc *);
+void	ar5008_disable_phy(struct athn_softc *);
+void	ar5008_init_chains(struct athn_softc *);
+void	ar5008_set_rxchains(struct athn_softc *);
+void	ar5008_read_noisefloor(struct athn_softc *, int16_t *, int16_t *);
+void	ar5008_write_noisefloor(struct athn_softc *, int16_t *, int16_t *);
+void	ar5008_get_noisefloor(struct athn_softc *, struct ieee80211_channel *);
+void	ar5008_bb_load_noisefloor(struct athn_softc *);
+void	ar5008_noisefloor_calib(struct athn_softc *);
+void	ar5008_do_noisefloor_calib(struct athn_softc *);
+void	ar5008_do_calib(struct athn_softc *);
+void	ar5008_next_calib(struct athn_softc *);
+void	ar5008_calib_iq(struct athn_softc *);
+void	ar5008_calib_adc_gain(struct athn_softc *);
+void	ar5008_calib_adc_dc_off(struct athn_softc *);
+void	ar5008_write_txpower(struct athn_softc *, int16_t power[]);
+void	ar5008_set_viterbi_mask(struct athn_softc *, int);
+void	ar5008_hw_init(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+uint8_t	ar5008_get_vpd(uint8_t, const uint8_t *, const uint8_t *, int);
+void	ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *,
+	    struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *);
+void	ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]);
+void	ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]);
+void	ar5008_set_noise_immunity_level(struct athn_softc *, int);
+void	ar5008_enable_ofdm_weak_signal(struct athn_softc *);
+void	ar5008_disable_ofdm_weak_signal(struct athn_softc *);
+void	ar5008_set_cck_weak_signal(struct athn_softc *, int);
+void	ar5008_set_firstep_level(struct athn_softc *, int);
+void	ar5008_set_spur_immunity_level(struct athn_softc *, int);
+
+/* Extern functions. */
+void	athn_stop(struct ifnet *, int);
+int	athn_interpolate(int, int, int, int, int);
+int	athn_txtime(struct athn_softc *, int, int, u_int);
+void	athn_inc_tx_trigger_level(struct athn_softc *);
+void	athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);
+void	athn_config_pcie(struct athn_softc *);
+void	athn_config_nonpcie(struct athn_softc *);
+uint8_t	athn_chan2fbin(struct ieee80211_channel *);
+uint8_t	ar5416_get_rf_rev(struct athn_softc *);
+void	ar5416_reset_addac(struct athn_softc *, struct ieee80211_channel *);
+void	ar5416_rf_reset(struct athn_softc *, struct ieee80211_channel *);
+void	ar5416_reset_bb_gain(struct athn_softc *, struct ieee80211_channel *);
+void	ar9280_reset_rx_gain(struct athn_softc *, struct ieee80211_channel *);
+void	ar9280_reset_tx_gain(struct athn_softc *, struct ieee80211_channel *);
+
+
+int
+ar5008_attach(struct athn_softc *sc)
+{
+	struct athn_ops *ops = &sc->ops;
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ar_base_eep_header *base;
+	uint8_t eep_ver, kc_entries_log;
+	int error;
+
+	/* Set callbacks for AR5008, AR9001 and AR9002 families. */
+	ops->gpio_read = ar5008_gpio_read;
+	ops->gpio_write = ar5008_gpio_write;
+	ops->gpio_config_input = ar5008_gpio_config_input;
+	ops->gpio_config_output = ar5008_gpio_config_output;
+	ops->rfsilent_init = ar5008_rfsilent_init;
+
+	ops->dma_alloc = ar5008_dma_alloc;
+	ops->dma_free = ar5008_dma_free;
+	ops->rx_enable = ar5008_rx_enable;
+	ops->intr = ar5008_intr;
+	ops->tx = ar5008_tx;
+
+	ops->set_rf_mode = ar5008_set_rf_mode;
+	ops->rf_bus_request = ar5008_rf_bus_request;
+	ops->rf_bus_release = ar5008_rf_bus_release;
+	ops->set_phy = ar5008_set_phy;
+	ops->set_delta_slope = ar5008_set_delta_slope;
+	ops->enable_antenna_diversity = ar5008_enable_antenna_diversity;
+	ops->init_baseband = ar5008_init_baseband;
+	ops->disable_phy = ar5008_disable_phy;
+	ops->set_rxchains = ar5008_set_rxchains;
+	ops->noisefloor_calib = ar5008_do_noisefloor_calib;
+	ops->do_calib = ar5008_do_calib;
+	ops->next_calib = ar5008_next_calib;
+	ops->hw_init = ar5008_hw_init;
+
+	ops->set_noise_immunity_level = ar5008_set_noise_immunity_level;
+	ops->enable_ofdm_weak_signal = ar5008_enable_ofdm_weak_signal;
+	ops->disable_ofdm_weak_signal = ar5008_disable_ofdm_weak_signal;
+	ops->set_cck_weak_signal = ar5008_set_cck_weak_signal;
+	ops->set_firstep_level = ar5008_set_firstep_level;
+	ops->set_spur_immunity_level = ar5008_set_spur_immunity_level;
+
+	/* Set MAC registers offsets. */
+	sc->obs_off = AR_OBS;
+	sc->gpio_input_en_off = AR_GPIO_INPUT_EN_VAL;
+
+	if (!(sc->flags & ATHN_FLAG_PCIE))
+		athn_config_nonpcie(sc);
+	else
+		athn_config_pcie(sc);
+
+	/* Read entire ROM content in memory. */
+	if ((error = ar5008_read_rom(sc)) != 0) {
+		printf(": could not read ROM\n");
+		return (error);
+	}
+
+	/* Get RF revision. */
+	sc->rf_rev = ar5416_get_rf_rev(sc);
+
+	base = sc->eep;
+	eep_ver = (base->version >> 12) & 0xf;
+	sc->eep_rev = (base->version & 0xfff);
+	if (eep_ver != AR_EEP_VER || sc->eep_rev == 0) {
+		printf(": unsupported ROM version %d.%d\n",  eep_ver,
+		    sc->eep_rev);
+		return (EINVAL);
+	}
+
+	if (base->opCapFlags & AR_OPFLAGS_11A)
+		sc->flags |= ATHN_FLAG_11A;
+	if (base->opCapFlags & AR_OPFLAGS_11G)
+		sc->flags |= ATHN_FLAG_11G;
+	if (base->opCapFlags & AR_OPFLAGS_11N)
+		sc->flags |= ATHN_FLAG_11N;
+
+	IEEE80211_ADDR_COPY(ic->ic_myaddr, base->macAddr);
+
+	/* Check if we have a hardware radio switch. */
+	if (base->rfSilent & AR_EEP_RFSILENT_ENABLED) {
+		sc->flags |= ATHN_FLAG_RFSILENT;
+		/* Get GPIO pin used by hardware radio switch. */
+		sc->rfsilent_pin = MS(base->rfSilent,
+		    AR_EEP_RFSILENT_GPIO_SEL);
+		/* Get polarity of hardware radio switch. */
+		if (base->rfSilent & AR_EEP_RFSILENT_POLARITY)
+			sc->flags |= ATHN_FLAG_RFSILENT_REVERSED;
+	}
+
+	/* Get the number of HW key cache entries. */
+	kc_entries_log = MS(base->deviceCap, AR_EEP_DEVCAP_KC_ENTRIES);
+	sc->kc_entries = (kc_entries_log != 0) ?
+	    1 << kc_entries_log : AR_KEYTABLE_SIZE;
+
+	sc->txchainmask = base->txMask;
+	if (sc->mac_ver == AR_SREV_VERSION_5416_PCI &&
+	    !(base->opCapFlags & AR_OPFLAGS_11A)) {
+		/* For single-band AR5416 PCI, use GPIO pin 0. */
+		sc->rxchainmask = ar5008_gpio_read(sc, 0) ? 0x5 : 0x7;
+	} else
+		sc->rxchainmask = base->rxMask;
+
+	ops->setup(sc);
+	return (0);
+}
+
+/*
+ * Read 16-bit value from ROM.
+ */
+int
+ar5008_read_rom_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)
+{
+	uint32_t reg;
+	int ntries;
+
+	reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
+	for (ntries = 0; ntries < 1000; ntries++) {
+		reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
+		if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |
+		    AR_EEPROM_STATUS_DATA_PROT_ACCESS))) {
+			*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
+			return (0);
+		}
+		DELAY(10);
+	}
+	*val = 0xffff;
+	return (ETIMEDOUT);
+}
+
+int
+ar5008_read_rom(struct athn_softc *sc)
+{
+	uint32_t addr, end;
+	uint16_t magic, sum, *eep;
+	int need_swap = 0;
+	int error;
+
+	/* Determine ROM endianness. */
+	error = ar5008_read_rom_word(sc, AR_EEPROM_MAGIC_OFFSET, &magic);
+	if (error != 0)
+		return (error);
+	if (magic != AR_EEPROM_MAGIC) {
+		if (magic != swap16(AR_EEPROM_MAGIC)) {
+			DPRINTF(("invalid ROM magic 0x%x != 0x%x\n",
+			    magic, AR_EEPROM_MAGIC));
+			return (EIO);
+		}
+		DPRINTF(("non-native ROM endianness\n"));
+		need_swap = 1;
+	}
+
+	/* Allocate space to store ROM in host memory. */
+	sc->eep = malloc(sc->eep_size, M_DEVBUF, M_NOWAIT);
+	if (sc->eep == NULL)
+		return (ENOMEM);
+
+	/* Read entire ROM and compute checksum. */
+	sum = 0;
+	eep = sc->eep;
+	end = sc->eep_base + sc->eep_size / sizeof(uint16_t);
+	for (addr = sc->eep_base; addr < end; addr++, eep++) {
+		if ((error = ar5008_read_rom_word(sc, addr, eep)) != 0) {
+			DPRINTF(("could not read ROM at 0x%x\n", addr));
+			return (error);
+		}
+		if (need_swap)
+			*eep = swap16(*eep);
+		sum ^= *eep;
+	}
+	if (sum != 0xffff) {
+		printf("%s: bad ROM checksum 0x%04x\n",
+		    sc->sc_dev.dv_xname, sum);
+		return (EIO);
+	}
+	if (need_swap)
+		ar5008_swap_rom(sc);
+
+	return (0);
+}
+
+void
+ar5008_swap_rom(struct athn_softc *sc)
+{
+	struct ar_base_eep_header *base = sc->eep;
+
+	/* Swap common fields first. */
+	base->length = swap16(base->length);
+	base->version = swap16(base->version);
+	base->regDmn[0] = swap16(base->regDmn[0]);
+	base->regDmn[1] = swap16(base->regDmn[1]);
+	base->rfSilent = swap16(base->rfSilent);
+	base->blueToothOptions = swap16(base->blueToothOptions);
+	base->deviceCap = swap16(base->deviceCap);
+
+	/* Swap device-dependent fields. */
+	sc->ops.swap_rom(sc);
+}
+
+/*
+ * Access to General Purpose Input/Output ports.
+ */
+int
+ar5008_gpio_read(struct athn_softc *sc, int pin)
+{
+	KASSERT(pin < sc->ngpiopins);
+	return ((AR_READ(sc, AR_GPIO_IN_OUT) >> (sc->ngpiopins + pin)) & 1);
+}
+
+void
+ar5008_gpio_write(struct athn_softc *sc, int pin, int set)
+{
+	uint32_t reg;
+
+	KASSERT(pin < sc->ngpiopins);
+	reg = AR_READ(sc, AR_GPIO_IN_OUT);
+	if (set)
+		reg |= 1 << pin;
+	else
+		reg &= ~(1 << pin);
+	AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
+}
+
+void
+ar5008_gpio_config_input(struct athn_softc *sc, int pin)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_GPIO_OE_OUT);
+	reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+	reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
+	AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+}
+
+void
+ar5008_gpio_config_output(struct athn_softc *sc, int pin, int type)
+{
+	uint32_t reg;
+	int mux, off;
+
+	mux = pin / 6;
+	off = pin % 6;
+
+	reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
+	if (!AR_SREV_9280_20_OR_LATER(sc) && mux == 0)
+		reg = (reg & ~0x1f0) | (reg & 0x1f0) << 1;
+	reg &= ~(0x1f << (off * 5));
+	reg |= (type & 0x1f) << (off * 5);
+	AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
+
+	reg = AR_READ(sc, AR_GPIO_OE_OUT);
+	reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+	reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
+	AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+}
+
+void
+ar5008_rfsilent_init(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	/* Configure hardware radio switch. */
+	AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
+	reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
+	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
+	AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
+	ar5008_gpio_config_input(sc, sc->rfsilent_pin);
+	AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
+	if (!(sc->flags & ATHN_FLAG_RFSILENT_REVERSED)) {
+		AR_SETBITS(sc, AR_GPIO_INTR_POL,
+		    AR_GPIO_INTR_POL_PIN(sc->rfsilent_pin));
+	}
+}
+
+int
+ar5008_dma_alloc(struct athn_softc *sc)
+{
+	int error;
+
+	error = ar5008_tx_alloc(sc);
+	if (error != 0)
+		return (error);
+
+	error = ar5008_rx_alloc(sc);
+	if (error != 0)
+		return (error);
+
+	return (0);
+}
+
+void
+ar5008_dma_free(struct athn_softc *sc)
+{
+	ar5008_tx_free(sc);
+	ar5008_rx_free(sc);
+}
+
+int
+ar5008_tx_alloc(struct athn_softc *sc)
+{
+	struct athn_tx_buf *bf;
+	bus_size_t size;
+	int error, nsegs, i;
+
+	/*
+	 * Allocate a pool of Tx descriptors shared between all Tx queues.
+	 */
+	size = ATHN_NTXBUFS * AR5008_MAX_SCATTER * sizeof(struct ar_tx_desc);
+
+	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+	    BUS_DMA_NOWAIT, &sc->map);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->seg, 1,
+	    &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_map(sc->sc_dmat, &sc->seg, 1, size,
+	    (caddr_t *)&sc->descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamap_load_raw(sc->sc_dmat, sc->map, &sc->seg, 1, size,
+	    BUS_DMA_NOWAIT);
+	if (error != 0)
+		goto fail;
+
+	SIMPLEQ_INIT(&sc->txbufs);
+	for (i = 0; i < ATHN_NTXBUFS; i++) {
+		bf = &sc->txpool[i];
+
+		error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ,
+		    AR5008_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT,
+		    &bf->bf_map);
+		if (error != 0) {
+			printf("%s: could not create Tx buf DMA map\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+
+		bf->bf_descs =
+		    &((struct ar_tx_desc *)sc->descs)[i * AR5008_MAX_SCATTER];
+		bf->bf_daddr = sc->map->dm_segs[0].ds_addr +
+		    i * AR5008_MAX_SCATTER * sizeof(struct ar_tx_desc);
+
+		SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
+	}
+	return (0);
+ fail:
+	ar5008_tx_free(sc);
+	return (error);
+}
+
+void
+ar5008_tx_free(struct athn_softc *sc)
+{
+	struct athn_tx_buf *bf;
+	int i;
+
+	for (i = 0; i < ATHN_NTXBUFS; i++) {
+		bf = &sc->txpool[i];
+
+		if (bf->bf_map != NULL)
+			bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+	}
+	/* Free Tx descriptors. */
+	if (sc->map != NULL) {
+		if (sc->descs != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, sc->map);
+			bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->descs,
+			    ATHN_NTXBUFS * AR5008_MAX_SCATTER *
+			    sizeof(struct ar_tx_desc));
+			bus_dmamem_free(sc->sc_dmat, &sc->seg, 1);
+		}
+		bus_dmamap_destroy(sc->sc_dmat, sc->map);
+	}
+}
+
+int
+ar5008_rx_alloc(struct athn_softc *sc)
+{
+	struct athn_rxq *rxq = &sc->rxq[0];
+	struct athn_rx_buf *bf;
+	struct ar_rx_desc *ds;
+	bus_size_t size;
+	int error, nsegs, i;
+
+	rxq->bf = malloc(ATHN_NRXBUFS * sizeof(*bf), M_DEVBUF,
+	    M_NOWAIT | M_ZERO);
+	if (rxq->bf == NULL)
+		return (ENOMEM);
+
+	size = ATHN_NRXBUFS * sizeof(struct ar_rx_desc);
+
+	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+	    BUS_DMA_NOWAIT, &rxq->map);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rxq->seg, 1,
+	    &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_map(sc->sc_dmat, &rxq->seg, 1, size,
+	    (caddr_t *)&rxq->descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamap_load_raw(sc->sc_dmat, rxq->map, &rxq->seg, 1,
+	    size, BUS_DMA_NOWAIT);
+	if (error != 0)
+		goto fail;
+
+	for (i = 0; i < ATHN_NRXBUFS; i++) {
+		bf = &rxq->bf[i];
+		ds = &((struct ar_rx_desc *)rxq->descs)[i];
+
+		error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1,
+		    ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
+		    &bf->bf_map);
+		if (error != 0) {
+			printf("%s: could not create Rx buf DMA map\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+		/*
+		 * Assumes MCLGETI returns cache-line-size aligned buffers.
+		 */
+		bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+		if (bf->bf_m == NULL) {
+			printf("%s: could not allocate Rx mbuf\n",
+			    sc->sc_dev.dv_xname);
+			error = ENOBUFS;
+			goto fail;
+		}
+
+		error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+		    mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+		    BUS_DMA_NOWAIT | BUS_DMA_READ);
+		if (error != 0) {
+			printf("%s: could not DMA map Rx buffer\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+
+		bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
+		    bf->bf_map->dm_mapsize, BUS_DMASYNC_PREREAD);
+
+		bf->bf_desc = ds;
+		bf->bf_daddr = rxq->map->dm_segs[0].ds_addr +
+		    i * sizeof(struct ar_rx_desc);
+	}
+	return (0);
+ fail:
+	ar5008_rx_free(sc);
+	return (error);
+}
+
+void
+ar5008_rx_free(struct athn_softc *sc)
+{
+	struct athn_rxq *rxq = &sc->rxq[0];
+	struct athn_rx_buf *bf;
+	int i;
+
+	for (i = 0; i < ATHN_NRXBUFS; i++) {
+		bf = &rxq->bf[i];
+
+		if (bf->bf_map != NULL)
+			bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+		if (bf->bf_m != NULL)
+			m_freem(bf->bf_m);
+	}
+	if (rxq->bf != NULL)
+		free(rxq->bf, M_DEVBUF);
+	/* Free Rx descriptors. */
+	if (rxq->descs != NULL) {
+		if (rxq->descs != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, rxq->map);
+			bus_dmamem_unmap(sc->sc_dmat, (caddr_t)rxq->descs,
+			    ATHN_NRXBUFS * sizeof(struct ar_rx_desc));
+			bus_dmamem_free(sc->sc_dmat, &rxq->seg, 1);
+		}
+		bus_dmamap_destroy(sc->sc_dmat, rxq->map);
+	}
+}
+
+void
+ar5008_rx_enable(struct athn_softc *sc)
+{
+	struct athn_rxq *rxq = &sc->rxq[0];
+	struct athn_rx_buf *bf;
+	struct ar_rx_desc *ds;
+	int i;
+
+	/* Setup and link Rx descriptors. */
+	SIMPLEQ_INIT(&rxq->head);
+	rxq->lastds = NULL;
+	for (i = 0; i < ATHN_NRXBUFS; i++) {
+		bf = &rxq->bf[i];
+		ds = bf->bf_desc;
+
+		memset(ds, 0, sizeof(*ds));
+		ds->ds_data = bf->bf_map->dm_segs[0].ds_addr;
+		ds->ds_ctl1 = SM(AR_RXC1_BUF_LEN, ATHN_RXBUFSZ);
+
+		if (rxq->lastds != NULL) {
+			((struct ar_rx_desc *)rxq->lastds)->ds_link =
+			    bf->bf_daddr;
+		}
+		SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+		rxq->lastds = ds;
+	}
+	bus_dmamap_sync(sc->sc_dmat, rxq->map, 0, rxq->map->dm_mapsize,
+	    BUS_DMASYNC_PREREAD);
+
+	/* Enable Rx. */
+	AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
+	AR_WRITE(sc, AR_CR, AR_CR_RXE);
+}
+
+#if NBPFILTER > 0
+void
+ar5008_rx_radiotap(struct athn_softc *sc, struct mbuf *m,
+    struct ar_rx_desc *ds)
+{
+#define IEEE80211_RADIOTAP_F_SHORTGI	0x80	/* XXX from FBSD */
+
+	struct athn_rx_radiotap_header *tap = &sc->sc_rxtap;
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct mbuf mb;
+	uint64_t tsf;
+	uint32_t tstamp;
+	uint8_t rate;
+
+	/* Extend the 15-bit timestamp from Rx descriptor to 64-bit TSF. */
+	tstamp = ds->ds_status2;
+	tsf = AR_READ(sc, AR_TSF_U32);
+	tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32);
+	if ((tsf & 0x7fff) < tstamp)
+		tsf -= 0x8000;
+	tsf = (tsf & ~0x7fff) | tstamp;
+
+	tap->wr_flags = IEEE80211_RADIOTAP_F_FCS;
+	tap->wr_tsft = htole64(tsf);
+	tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
+	tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
+	tap->wr_dbm_antsignal = MS(ds->ds_status4, AR_RXS4_RSSI_COMBINED);
+	/* XXX noise. */
+	tap->wr_antenna = MS(ds->ds_status3, AR_RXS3_ANTENNA);
+	tap->wr_rate = 0;	/* In case it can't be found below. */
+	if (AR_SREV_5416_20_OR_LATER(sc))
+		rate = MS(ds->ds_status0, AR_RXS0_RATE);
+	else
+		rate = MS(ds->ds_status3, AR_RXS3_RATE);
+	if (rate & 0x80) {		/* HT. */
+		/* Bit 7 set means HT MCS instead of rate. */
+		tap->wr_rate = rate;
+		if (!(ds->ds_status3 & AR_RXS3_GI))
+			tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
+
+	} else if (rate & 0x10) {	/* CCK. */
+		if (rate & 0x04)
+			tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+		switch (rate & ~0x14) {
+		case 0xb: tap->wr_rate =   2; break;
+		case 0xa: tap->wr_rate =   4; break;
+		case 0x9: tap->wr_rate =  11; break;
+		case 0x8: tap->wr_rate =  22; break;
+		}
+	} else {			/* OFDM. */
+		switch (rate) {
+		case 0xb: tap->wr_rate =  12; break;
+		case 0xf: tap->wr_rate =  18; break;
+		case 0xa: tap->wr_rate =  24; break;
+		case 0xe: tap->wr_rate =  36; break;
+		case 0x9: tap->wr_rate =  48; break;
+		case 0xd: tap->wr_rate =  72; break;
+		case 0x8: tap->wr_rate =  96; break;
+		case 0xc: tap->wr_rate = 108; break;
+		}
+	}
+	mb.m_data = (caddr_t)tap;
+	mb.m_len = sc->sc_rxtap_len;
+	mb.m_next = m;
+	mb.m_nextpkt = NULL;
+	mb.m_type = 0;
+	mb.m_flags = 0;
+	bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN);
+}
+#endif
+
+static __inline int
+ar5008_rx_process(struct athn_softc *sc)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ifnet *ifp = &ic->ic_if;
+	struct athn_rxq *rxq = &sc->rxq[0];
+	struct athn_rx_buf *bf, *nbf;
+	struct ar_rx_desc *ds;
+	struct ieee80211_frame *wh;
+	struct ieee80211_rxinfo rxi;
+	struct ieee80211_node *ni;
+	struct mbuf *m, *m1;
+	int error, len;
+
+	bf = SIMPLEQ_FIRST(&rxq->head);
+	if (__predict_false(bf == NULL)) {	/* Should not happen. */
+		printf("%s: Rx queue is empty!\n", sc->sc_dev.dv_xname);
+		return (ENOENT);
+	}
+	ds = bf->bf_desc;
+
+	if (!(ds->ds_status8 & AR_RXS8_DONE)) {
+		/*
+		 * On some parts, the status words can get corrupted
+		 * (including the "done" bit), so we check the next
+		 * descriptor "done" bit.  If it is set, it is a good
+		 * indication that the status words are corrupted, so
+		 * we skip this descriptor and drop the frame.
+		 */
+		nbf = SIMPLEQ_NEXT(bf, bf_list);
+		if (nbf != NULL &&
+		    (((struct ar_rx_desc *)nbf->bf_desc)->ds_status8 &
+		     AR_RXS8_DONE)) {
+			DPRINTF(("corrupted descriptor status=0x%x\n",
+			    ds->ds_status8));
+			/* HW will not "move" RXDP in this case, so do it. */
+			AR_WRITE(sc, AR_RXDP, nbf->bf_daddr);
+			ifp->if_ierrors++;
+			goto skip;
+		}
+		return (EBUSY);
+	}
+
+	if (__predict_false(ds->ds_status1 & AR_RXS1_MORE)) {
+		/* Drop frames that span multiple Rx descriptors. */
+		DPRINTF(("dropping split frame\n"));
+		ifp->if_ierrors++;
+		goto skip;
+	}
+	if (!(ds->ds_status8 & AR_RXS8_FRAME_OK)) {
+		if (ds->ds_status8 & AR_RXS8_CRC_ERR)
+			DPRINTFN(6, ("CRC error\n"));
+		else if (ds->ds_status8 & AR_RXS8_PHY_ERR)
+			DPRINTFN(6, ("PHY error=0x%x\n",
+			    MS(ds->ds_status8, AR_RXS8_PHY_ERR_CODE)));
+		else if (ds->ds_status8 & AR_RXS8_DECRYPT_CRC_ERR)
+			DPRINTFN(6, ("Decryption CRC error\n"));
+		else if (ds->ds_status8 & AR_RXS8_MICHAEL_ERR) {
+			DPRINTFN(2, ("Michael MIC failure\n"));
+			/* Report Michael MIC failures to net80211. */
+			ic->ic_stats.is_rx_locmicfail++;
+			ieee80211_michael_mic_failure(ic, 0);
+			/*
+			 * XXX Check that it is not a control frame
+			 * (invalid MIC failures on valid ctl frames.)
+			 */
+		}
+		ifp->if_ierrors++;
+		goto skip;
+	}
+
+	len = MS(ds->ds_status1, AR_RXS1_DATA_LEN);
+	if (__predict_false(len == 0 || len > ATHN_RXBUFSZ)) {
+		DPRINTF(("corrupted descriptor length=%d\n", len));
+		ifp->if_ierrors++;
+		goto skip;
+	}
+
+	/* Allocate a new Rx buffer. */
+	m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+	if (__predict_false(m1 == NULL)) {
+		ic->ic_stats.is_rx_nombuf++;
+		ifp->if_ierrors++;
+		goto skip;
+	}
+
+	/* Sync and unmap the old Rx buffer. */
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+	    BUS_DMASYNC_POSTREAD);
+	bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+	/* Map the new Rx buffer. */
+	error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *),
+	    ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ);
+	if (__predict_false(error != 0)) {
+		m_freem(m1);
+
+		/* Remap the old Rx buffer or panic. */
+		error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+		    mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+		    BUS_DMA_NOWAIT | BUS_DMA_READ);
+		KASSERT(error != 0);
+		ifp->if_ierrors++;
+		goto skip;
+	}
+
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+	    BUS_DMASYNC_PREREAD);
+
+	/* Write physical address of new Rx buffer. */
+	ds->ds_data = bf->bf_map->dm_segs[0].ds_addr;
+
+	m = bf->bf_m;
+	bf->bf_m = m1;
+
+	/* Finalize mbuf. */
+	m->m_pkthdr.rcvif = ifp;
+	m->m_pkthdr.len = m->m_len = len;
+
+	/* Grab a reference to the source node. */
+	wh = mtod(m, struct ieee80211_frame *);
+	ni = ieee80211_find_rxnode(ic, wh);
+
+	/* Remove any HW padding after the 802.11 header. */
+	if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) {
+		u_int hdrlen = ieee80211_get_hdrlen(wh);
+		if (hdrlen & 3) {
+			ovbcopy(wh, (caddr_t)wh + 2, hdrlen);
+			m_adj(m, 2);	/* XXX sure? */
+		}
+	}
+#if NBPFILTER > 0
+	if (__predict_false(sc->sc_drvbpf != NULL))
+		ar5008_rx_radiotap(sc, m, ds);
+#endif
+	/* Trim 802.11 FCS after radiotap. */
+	m_adj(m, -IEEE80211_CRC_LEN);
+
+	/* Send the frame to the 802.11 layer. */
+	rxi.rxi_flags = 0;	/* XXX */
+	rxi.rxi_rssi = MS(ds->ds_status4, AR_RXS4_RSSI_COMBINED);
+	rxi.rxi_tstamp = ds->ds_status2;
+	ieee80211_input(ifp, m, ni, &rxi);
+
+	/* Node is no longer needed. */
+	ieee80211_release_node(ic, ni);
+
+ skip:
+	/* Unlink this descriptor from head. */
+	SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list);
+	memset(&ds->ds_status0, 0, 36);	/* XXX Really needed? */
+	ds->ds_status8 &= ~AR_RXS8_DONE;
+	ds->ds_link = 0;
+
+	/* Re-use this descriptor and link it to tail. */
+	if (__predict_true(!SIMPLEQ_EMPTY(&rxq->head)))
+		((struct ar_rx_desc *)rxq->lastds)->ds_link = bf->bf_daddr;
+	else
+		AR_WRITE(sc, AR_RXDP, bf->bf_daddr);
+	SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+	rxq->lastds = ds;
+
+	/* Re-enable Rx. */
+	AR_WRITE(sc, AR_CR, AR_CR_RXE);
+	return (0);
+}
+
+void
+ar5008_rx_intr(struct athn_softc *sc)
+{
+	while (ar5008_rx_process(sc) == 0);
+}
+
+int
+ar5008_tx_process(struct athn_softc *sc, int qid)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ifnet *ifp = &ic->ic_if;
+	struct athn_txq *txq = &sc->txq[qid];
+	struct athn_node *an;
+	struct athn_tx_buf *bf;
+	struct ar_tx_desc *ds;
+	uint8_t failcnt;
+
+	bf = SIMPLEQ_FIRST(&txq->head);
+	if (__predict_false(bf == NULL))
+		return (ENOENT);
+	/* Get descriptor of last DMA segment. */
+	ds = &((struct ar_tx_desc *)bf->bf_descs)[bf->bf_map->dm_nsegs - 1];
+
+	if (!(ds->ds_status9 & AR_TXS9_DONE))
+		return (EBUSY);
+
+	SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
+	ifp->if_opackets++;
+
+	sc->sc_tx_timer = 0;
+
+	if (ds->ds_status1 & AR_TXS1_EXCESSIVE_RETRIES)
+		ifp->if_oerrors++;
+
+	if (ds->ds_status1 & AR_TXS1_UNDERRUN)
+		athn_inc_tx_trigger_level(sc);
+
+	an = (struct athn_node *)bf->bf_ni;
+	/*
+	 * NB: the data fail count contains the number of un-acked tries
+	 * for the final series used.  We must add the number of tries for
+	 * each series that was fully processed.
+	 */
+	failcnt  = MS(ds->ds_status1, AR_TXS1_DATA_FAIL_CNT);
+	/* NB: Assume two tries per series. */
+	failcnt += MS(ds->ds_status9, AR_TXS9_FINAL_IDX) * 2;
+
+	/* Update rate control statistics. */
+	an->amn.amn_txcnt++;
+	if (failcnt > 0)
+		an->amn.amn_retrycnt++;
+
+	DPRINTFN(5, ("Tx done qid=%d status1=%d fail count=%d\n",
+	    qid, ds->ds_status1, failcnt));
+
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+	    BUS_DMASYNC_POSTWRITE);
+	bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+	m_freem(bf->bf_m);
+	bf->bf_m = NULL;
+	ieee80211_release_node(ic, bf->bf_ni);
+	bf->bf_ni = NULL;
+
+	/* Link Tx buffer back to global free list. */
+	SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
+	return (0);
+}
+
+void
+ar5008_tx_intr(struct athn_softc *sc)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ifnet *ifp = &ic->ic_if;
+	uint16_t mask = 0;
+	uint32_t reg;
+	int qid;
+
+	reg = AR_READ(sc, AR_ISR_S0_S);
+	mask |= MS(reg, AR_ISR_S0_QCU_TXOK);
+	mask |= MS(reg, AR_ISR_S0_QCU_TXDESC);
+
+	reg = AR_READ(sc, AR_ISR_S1_S);
+	mask |= MS(reg, AR_ISR_S1_QCU_TXERR);
+	mask |= MS(reg, AR_ISR_S1_QCU_TXEOL);
+
+	DPRINTFN(4, ("Tx interrupt mask=0x%x\n", mask));
+	for (qid = 0; mask != 0; mask >>= 1, qid++) {
+		if (mask & 1)
+			while (ar5008_tx_process(sc, qid) == 0);
+	}
+	if (!SIMPLEQ_EMPTY(&sc->txbufs)) {
+		ifp->if_flags &= ~IFF_OACTIVE;
+		ifp->if_start(ifp);
+	}
+}
+
+int
+ar5008_intr(struct athn_softc *sc)
+{
+	uint32_t intr, intr2, intr5, sync;
+
+	/* Get pending interrupts. */
+	intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+	if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
+		intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+		if (intr == AR_INTR_SPURIOUS || (intr & sc->isync) == 0)
+			return (0);	/* Not for us. */
+	}
+
+	if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+	    (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+		intr = AR_READ(sc, AR_ISR);
+	else
+		intr = 0;
+	sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->isync;
+	if (intr == 0 && sync == 0)
+		return (0);	/* Not for us. */
+
+	if (intr != 0) {
+		if (intr & AR_ISR_BCNMISC) {
+			intr2 = AR_READ(sc, AR_ISR_S2);
+			if (intr2 & AR_ISR_S2_TIM)
+				/* TBD */;
+			if (intr2 & AR_ISR_S2_TSFOOR)
+				/* TBD */;
+		}
+		intr = AR_READ(sc, AR_ISR_RAC);
+		if (intr == AR_INTR_SPURIOUS)
+			return (1);
+
+		if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
+			ar5008_rx_intr(sc);
+		if (intr & (AR_ISR_RXOK | AR_ISR_RXERR | AR_ISR_RXORN))
+			ar5008_rx_intr(sc);
+
+		if (intr & (AR_ISR_TXOK | AR_ISR_TXDESC |
+		    AR_ISR_TXERR | AR_ISR_TXEOL))
+			ar5008_tx_intr(sc);
+
+		if (intr & AR_ISR_GENTMR) {
+			intr5 = AR_READ(sc, AR_ISR_S5_S);
+			if (intr5 & AR_ISR_GENTMR) {
+				DPRINTF(("GENTMR trigger=%d thresh=%d\n",
+				    MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
+				    MS(intr5, AR_ISR_S5_GENTIMER_THRESH)));
+			}
+		}
+
+		intr5 = AR_READ(sc, AR_ISR_S5_S);
+		if (intr5 & AR_ISR_S5_TIM_TIMER)
+			/* TBD */;
+	}
+	if (sync != 0) {
+		if (sync & (AR_INTR_SYNC_HOST1_FATAL |
+		    AR_INTR_SYNC_HOST1_PERR))
+			/* TBD */;
+
+		if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
+			AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
+			AR_WRITE(sc, AR_RC, 0);
+		}
+
+		if ((sc->flags & ATHN_FLAG_RFSILENT) &&
+		    (sync & AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin))) {
+			struct ifnet *ifp = &sc->sc_ic.ic_if;
+
+			printf("%s: radio switch turned off\n",
+			    sc->sc_dev.dv_xname);
+			/* Turn the interface down. */
+			ifp->if_flags &= ~IFF_UP;
+			athn_stop(ifp, 1);
+			return (1);
+		}
+
+		AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
+		(void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+	}
+	return (1);
+}
+
+int
+ar5008_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ieee80211_key *k = NULL;
+	struct ieee80211_frame *wh;
+	struct athn_series series[4];
+	struct ar_tx_desc *ds, *lastds;
+	struct athn_txq *txq;
+	struct athn_tx_buf *bf;
+	struct athn_node *an = (void *)ni;
+	struct mbuf *m1;
+	uintptr_t entry;
+	uint16_t qos;
+	uint8_t txpower, type, encrtype, tid, ridx[4];
+	int i, error, totlen, hasqos, qid;
+
+	/* Grab a Tx buffer from our global free list. */
+	bf = SIMPLEQ_FIRST(&sc->txbufs);
+	KASSERT(bf != NULL);
+	SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list);
+
+	/* Map 802.11 frame type to hardware frame type. */
+	wh = mtod(m, struct ieee80211_frame *);
+	if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
+	    IEEE80211_FC0_TYPE_MGT) {
+		if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+		    IEEE80211_FC0_SUBTYPE_BEACON)
+			type = AR_FRAME_TYPE_BEACON;
+		else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+		    IEEE80211_FC0_SUBTYPE_PROBE_RESP)
+			type = AR_FRAME_TYPE_PROBE_RESP;
+		else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+		    IEEE80211_FC0_SUBTYPE_ATIM)
+			type = AR_FRAME_TYPE_ATIM;
+		else
+			type = AR_FRAME_TYPE_NORMAL;
+	} else if ((wh->i_fc[0] &
+	    (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
+	    (IEEE80211_FC0_TYPE_CTL  | IEEE80211_FC0_SUBTYPE_PS_POLL)) {
+		type = AR_FRAME_TYPE_PSPOLL;
+	} else
+		type = AR_FRAME_TYPE_NORMAL;
+
+	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
+		k = ieee80211_get_txkey(ic, wh, ni);
+		if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
+			return (ENOBUFS);
+		wh = mtod(m, struct ieee80211_frame *);
+	}
+
+	/* XXX 2-byte padding for QoS and 4-addr headers. */
+
+	/* Select the HW Tx queue to use for this frame. */
+	if ((hasqos = ieee80211_has_qos(wh))) {
+		qos = ieee80211_get_qos(wh);
+		tid = qos & IEEE80211_QOS_TID;
+		qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)];
+	} else if (type == AR_FRAME_TYPE_BEACON) {
+		qid = ATHN_QID_BEACON;
+	} else if (type == AR_FRAME_TYPE_PSPOLL) {
+		qid = ATHN_QID_PSPOLL;
+	} else
+		qid = ATHN_QID_AC_BE;
+	txq = &sc->txq[qid];
+
+	/* Select the transmit rates to use for this frame. */
+	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+	    (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
+	    IEEE80211_FC0_TYPE_DATA) {
+		/* Use lowest rate for all tries. */
+		ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+		    (ic->ic_curmode == IEEE80211_MODE_11A) ?
+			ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1;
+	} else if (ic->ic_fixed_rate != -1) {
+		/* Use same fixed rate for all tries. */
+		ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+		    sc->fixed_ridx;
+	} else {
+		int txrate = ni->ni_txrate;
+		/* Use fallback table of the node. */
+		for (i = 0; i < 4; i++) {
+			ridx[i] = an->ridx[txrate];
+			txrate = an->fallback[txrate];
+		}
+	}
+
+#if NBPFILTER > 0
+	if (__predict_false(sc->sc_drvbpf != NULL)) {
+		struct athn_tx_radiotap_header *tap = &sc->sc_txtap;
+		struct mbuf mb;
+
+		tap->wt_flags = 0;
+		/* Use initial transmit rate. */
+		tap->wt_rate = athn_rates[ridx[0]].rate;
+		tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
+		tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
+		tap->wt_hwqueue = qid;
+		if (ridx[0] != ATHN_RIDX_CCK1 &&
+		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+			tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+		mb.m_data = (caddr_t)tap;
+		mb.m_len = sc->sc_txtap_len;
+		mb.m_next = m;
+		mb.m_nextpkt = NULL;
+		mb.m_type = 0;
+		mb.m_flags = 0;
+		bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT);
+	}
+#endif
+
+	/* DMA map mbuf. */
+	error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+	    BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+	if (__predict_false(error != 0)) {
+		if (error != EFBIG) {
+			printf("%s: can't map mbuf (error %d)\n",
+			    sc->sc_dev.dv_xname, error);
+			m_freem(m);
+			return (error);
+		}
+		/*
+		 * DMA mapping requires too many DMA segments; linearize
+		 * mbuf in kernel virtual address space and retry.
+		 */
+		MGETHDR(m1, M_DONTWAIT, MT_DATA);
+		if (m1 == NULL) {
+			m_freem(m);
+			return (ENOBUFS);
+		}
+		if (m->m_pkthdr.len > MHLEN) {
+			MCLGET(m1, M_DONTWAIT);
+			if (!(m1->m_flags & M_EXT)) {
+				m_freem(m);
+				m_freem(m1);
+				return (ENOBUFS);
+			}
+		}
+		m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t));
+		m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len;
+		m_freem(m);
+		m = m1;
+
+		error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+		    BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+		if (error != 0) {
+			printf("%s: can't map mbuf (error %d)\n",
+			    sc->sc_dev.dv_xname, error);
+			m_freem(m);
+			return (error);
+		}
+	}
+	bf->bf_m = m;
+	bf->bf_ni = ni;
+
+	wh = mtod(m, struct ieee80211_frame *);
+
+	totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
+
+	/* Clear all Tx descriptors that we will use. */
+	memset(bf->bf_descs, 0, bf->bf_map->dm_nsegs * sizeof(*ds));
+
+	/* Setup first Tx descriptor. */
+	ds = bf->bf_descs;
+
+	ds->ds_ctl0 = AR_TXC0_INTR_REQ | AR_TXC0_CLR_DEST_MASK;
+	txpower = AR_MAX_RATE_POWER;	/* Get from per-rate registers. */
+	ds->ds_ctl0 |= SM(AR_TXC0_XMIT_POWER, txpower);
+
+	ds->ds_ctl1 = SM(AR_TXC1_FRAME_TYPE, type);
+
+	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+	    (hasqos && (qos & IEEE80211_QOS_ACK_POLICY_MASK) ==
+	     IEEE80211_QOS_ACK_POLICY_NOACK))
+		ds->ds_ctl1 |= AR_TXC1_NO_ACK;
+
+	if (0 && wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
+		/* Retrieve key for encryption. */
+		k = ieee80211_get_txkey(ic, wh, ni);
+		/*
+		 * Map 802.11 cipher to hardware encryption type and
+		 * compute crypto overhead.
+		 */
+		switch (k->k_cipher) {
+		case IEEE80211_CIPHER_WEP40:
+		case IEEE80211_CIPHER_WEP104:
+			encrtype = AR_ENCR_TYPE_WEP;
+			totlen += 8;
+			break;
+		case IEEE80211_CIPHER_TKIP:
+			encrtype = AR_ENCR_TYPE_TKIP;
+			totlen += 20;
+			break;
+		case IEEE80211_CIPHER_CCMP:
+			encrtype = AR_ENCR_TYPE_AES;
+			totlen += 16;
+			break;
+		default:
+			panic("unsupported cipher");	/* XXX BIP? */
+		}
+		/*
+		 * NB: The key cache entry index is stored in the key
+		 * private field when the key is installed.
+		 */
+		entry = (uintptr_t)k->k_priv;
+		ds->ds_ctl1 |= SM(AR_TXC1_DEST_IDX, entry);
+		ds->ds_ctl0 |= AR_TXC0_DEST_IDX_VALID;
+	} else
+		encrtype = AR_ENCR_TYPE_CLEAR;
+	ds->ds_ctl6 = SM(AR_TXC6_ENCR_TYPE, encrtype);
+
+	/* Check if frame must be protected using RTS/CTS or CTS-to-self. */
+	if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
+		/* NB: Group frames are sent using CCK in 802.11b/g. */
+		if (totlen > ic->ic_rtsthreshold) {
+			ds->ds_ctl0 |= AR_TXC0_RTS_ENABLE;
+		} else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
+		    athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) {
+			if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
+				ds->ds_ctl0 |= AR_TXC0_RTS_ENABLE;
+			else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
+				ds->ds_ctl0 |= AR_TXC0_CTS_ENABLE;
+		}
+	}
+	if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
+		/* Disable multi-rate retries when protection is used. */
+		ridx[1] = ridx[2] = ridx[3] = ridx[0];
+	}
+	/* Setup multi-rate retries. */
+	for (i = 0; i < 4; i++) {
+		series[i].hwrate = athn_rates[ridx[i]].hwrate;
+		if (athn_rates[ridx[i]].phy == IEEE80211_T_DS &&
+		    ridx[i] != ATHN_RIDX_CCK1 &&
+		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+			series[i].hwrate |= 0x04;
+		series[i].dur = 0;
+	}
+	if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
+		/* Compute duration for each series. */
+		for (i = 0; i < 4; i++) {
+			series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN,
+			    athn_rates[ridx[i]].rspridx, ic->ic_flags);
+		}
+	}
+
+	/* Write number of tries for each series. */
+	ds->ds_ctl2 =
+	    SM(AR_TXC2_XMIT_DATA_TRIES0, 2) |
+	    SM(AR_TXC2_XMIT_DATA_TRIES1, 2) |
+	    SM(AR_TXC2_XMIT_DATA_TRIES2, 2) |
+	    SM(AR_TXC2_XMIT_DATA_TRIES3, 4);
+
+	/* Tell HW to update duration field in 802.11 header. */
+	if (type != AR_FRAME_TYPE_PSPOLL)
+		ds->ds_ctl2 |= AR_TXC2_DUR_UPDATE_ENA;
+
+	/* Write Tx rate for each series. */
+	ds->ds_ctl3 =
+	    SM(AR_TXC3_XMIT_RATE0, series[0].hwrate) |
+	    SM(AR_TXC3_XMIT_RATE1, series[1].hwrate) |
+	    SM(AR_TXC3_XMIT_RATE2, series[2].hwrate) |
+	    SM(AR_TXC3_XMIT_RATE3, series[3].hwrate);
+
+	/* Write duration for each series. */
+	ds->ds_ctl4 =
+	    SM(AR_TXC4_PACKET_DUR0, series[0].dur) |
+	    SM(AR_TXC4_PACKET_DUR1, series[1].dur);
+	ds->ds_ctl5 =
+	    SM(AR_TXC5_PACKET_DUR2, series[2].dur) |
+	    SM(AR_TXC5_PACKET_DUR3, series[3].dur);
+
+	/* Use the same Tx chains for all tries. */
+	ds->ds_ctl7 =
+	    SM(AR_TXC7_CHAIN_SEL0, sc->txchainmask) |
+	    SM(AR_TXC7_CHAIN_SEL1, sc->txchainmask) |
+	    SM(AR_TXC7_CHAIN_SEL2, sc->txchainmask) |
+	    SM(AR_TXC7_CHAIN_SEL3, sc->txchainmask);
+#ifdef notyet
+#ifndef IEEE80211_NO_HT
+	/* Use the same short GI setting for all tries. */
+	if (ic->ic_flags & IEEE80211_F_SHGI)
+		ds->ds_ctl7 |= AR_TXC7_GI0123;
+	/* Use the same channel width for all tries. */
+	if (ic->ic_flags & IEEE80211_F_CBW40)
+		ds->ds_ctl7 |= AR_TXC7_2040_0123;
+#endif
+#endif
+
+	if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
+		uint8_t protridx, hwrate;
+		uint16_t dur = 0;
+
+		/* Use the same protection mode for all tries. */
+		if (ds->ds_ctl0 & AR_TXC0_RTS_ENABLE) {
+			ds->ds_ctl4 |= AR_TXC4_RTSCTS_QUAL01;
+			ds->ds_ctl5 |= AR_TXC5_RTSCTS_QUAL23;
+		}
+		/* Select protection rate (suboptimal but ok.) */
+		protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
+		    ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2;
+		if (ds->ds_ctl0 & AR_TXC0_RTS_ENABLE) {
+			/* Account for CTS duration. */
+			dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+			    athn_rates[protridx].rspridx, ic->ic_flags);
+		}
+		dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags);
+		if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
+			/* Account for ACK duration. */
+			dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+			    athn_rates[ridx[0]].rspridx, ic->ic_flags);
+		}
+		/* Write protection frame duration and rate. */
+		ds->ds_ctl2 |= SM(AR_TXC2_BURST_DUR, dur);
+		hwrate = athn_rates[protridx].hwrate;
+		if (protridx == ATHN_RIDX_CCK2 &&
+		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+			hwrate |= 0x04;
+		ds->ds_ctl7 |= SM(AR_TXC7_RTSCTS_RATE, hwrate);
+	}
+
+	/* Finalize first Tx descriptor and fill others (if any.) */
+	ds->ds_ctl0 |= SM(AR_TXC0_FRAME_LEN, totlen);
+
+	for (i = 0; i < bf->bf_map->dm_nsegs; i++, ds++) {
+		ds->ds_data = bf->bf_map->dm_segs[i].ds_addr;
+		ds->ds_ctl1 |= SM(AR_TXC1_BUF_LEN,
+		    bf->bf_map->dm_segs[i].ds_len);
+
+		if (i != bf->bf_map->dm_nsegs - 1)
+			ds->ds_ctl1 |= AR_TXC1_MORE;
+		ds->ds_link = 0;
+
+		/* Chain Tx descriptor. */
+		if (i != 0)
+			lastds->ds_link = bf->bf_daddr + i * sizeof(*ds);
+		lastds = ds;
+	}
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+	    BUS_DMASYNC_PREWRITE);
+
+	if (!SIMPLEQ_EMPTY(&txq->head))
+		((struct ar_tx_desc *)txq->lastds)->ds_link = bf->bf_daddr;
+	else
+		AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
+	txq->lastds = lastds;
+	SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list);
+
+	ds = bf->bf_descs;
+	DPRINTFN(6, ("Tx qid=%d nsegs=%d ctl0=0x%x ctl1=0x%x ctl3=0x%x\n",
+	    qid, bf->bf_map->dm_nsegs, ds->ds_ctl0, ds->ds_ctl1, ds->ds_ctl3));
+
+	/* Kick Tx. */
+	AR_WRITE(sc, AR_Q_TXE, 1 << qid);
+	return (0);
+}
+
+void
+ar5008_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+	uint32_t reg;
+
+	reg = IEEE80211_IS_CHAN_2GHZ(c) ?
+	    AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
+	if (!AR_SREV_9280_10_OR_LATER(sc)) {
+		reg |= IEEE80211_IS_CHAN_2GHZ(c) ?
+		    AR_PHY_MODE_RF2GHZ : AR_PHY_MODE_RF5GHZ;
+	} else if (AR_SREV_9280_20(sc) && 0 /* XXX */) {
+		reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
+	}
+	AR_WRITE(sc, AR_PHY_MODE, reg);
+}
+
+static __inline uint32_t
+ar5008_synth_delay(struct athn_softc *sc)
+{
+	uint32_t delay;
+
+	delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY);
+	if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B)
+		delay = (delay * 4) / 22;
+	else
+		delay = delay / 10;	/* in 100ns steps */
+	return (delay);
+}
+
+int
+ar5008_rf_bus_request(struct athn_softc *sc)
+{
+	int ntries;
+
+	/* Request RF Bus grant. */
+	AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
+	for (ntries = 0; ntries < 10000; ntries++) {
+		if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN)
+			return (0);
+		DELAY(10);
+	}
+	DPRINTF(("could not kill baseband Rx"));
+	return (ETIMEDOUT);
+}
+
+void
+ar5008_rf_bus_release(struct athn_softc *sc)
+{
+	/* Wait for the synthesizer to settle. */
+	DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar5008_synth_delay(sc));
+
+	/* Release the RF Bus grant. */
+	AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
+}
+
+void
+ar5008_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	uint32_t phy;
+
+	if (AR_SREV_9285_10_OR_LATER(sc))
+		phy = AR_READ(sc, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO;
+	else
+		phy = 0;
+	phy |= AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
+	    AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
+#ifndef IEEE80211_NO_HT
+	if (extc != NULL) {
+		phy |= AR_PHY_FC_DYN2040_EN;
+		if (extc > c)	/* XXX */
+			phy |= AR_PHY_FC_DYN2040_PRI_CH;
+	}
+#endif
+	AR_WRITE(sc, AR_PHY_TURBO, phy);
+
+	AR_WRITE(sc, AR_2040_MODE,
+	    (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0);
+
+	/* Set global transmit timeout. */
+	AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
+	/* Set carrier sense timeout. */
+	AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
+}
+
+void
+ar5008_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	uint32_t coeff, exp, man, reg;
+
+	/* Set Delta Slope (exponent and mantissa). */
+	coeff = (100 << 24) / c->ic_freq;
+	athn_get_delta_slope(coeff, &exp, &man);
+	DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man));
+
+	reg = AR_READ(sc, AR_PHY_TIMING3);
+	reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
+	reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
+	AR_WRITE(sc, AR_PHY_TIMING3, reg);
+
+	/* For Short GI, coeff is 9/10 that of normal coeff. */
+	coeff = (9 * coeff) / 10;
+	athn_get_delta_slope(coeff, &exp, &man);
+	DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man));
+
+	reg = AR_READ(sc, AR_PHY_HALFGI);
+	reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
+	reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
+	AR_WRITE(sc, AR_PHY_HALFGI, reg);
+}
+
+void
+ar5008_enable_antenna_diversity(struct athn_softc *sc)
+{
+	AR_SETBITS(sc, AR_PHY_CCK_DETECT,
+	    AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+}
+
+void
+ar5008_init_baseband(struct athn_softc *sc)
+{
+	uint32_t synth_delay;
+
+	synth_delay = ar5008_synth_delay(sc);
+	/* Activate the PHY (includes baseband activate and synthesizer on). */
+	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+	DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay);
+}
+
+void
+ar5008_disable_phy(struct athn_softc *sc)
+{
+	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+}
+
+void
+ar5008_init_chains(struct athn_softc *sc)
+{
+	if (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5)
+		AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
+
+	/* Setup chain masks. */
+	if (sc->mac_ver <= AR_SREV_VERSION_9160 &&
+	    (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5)) {
+		AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  0x7);
+		AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, 0x7);
+	} else {
+		AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  sc->rxchainmask);
+		AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
+	}
+	AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask);
+}
+
+void
+ar5008_set_rxchains(struct athn_softc *sc)
+{
+	if (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5) {
+		AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  sc->rxchainmask);
+		AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
+	}
+}
+
+void
+ar5008_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+/* Sign-extend 9-bit value to 16-bit. */
+#define SIGN_EXT(v)	((((int16_t)(v)) << 7) >> 7)
+	uint32_t reg;
+	int i;
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		reg = AR_READ(sc, AR_PHY_CCA(i));
+		if (AR_SREV_9280_10_OR_LATER(sc))
+			nf[i] = MS(reg, AR9280_PHY_MINCCA_PWR);
+		else
+			nf[i] = MS(reg, AR_PHY_MINCCA_PWR);
+		nf[i] = SIGN_EXT(nf[i]);
+
+		reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+		if (AR_SREV_9280_10_OR_LATER(sc))
+			nf_ext[i] = MS(reg, AR9280_PHY_EXT_MINCCA_PWR);
+		else
+			nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);
+		nf_ext[i] = SIGN_EXT(nf_ext[i]);
+	}
+#undef SIGN_EXT
+}
+
+void
+ar5008_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+	uint32_t reg;
+	int i;
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		reg = AR_READ(sc, AR_PHY_CCA(i));
+		reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
+		AR_WRITE(sc, AR_PHY_CCA(i), reg);
+
+		reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+		reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
+		AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
+	}
+}
+
+void
+ar5008_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+	int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+	int i;
+
+	if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
+		/* Noisefloor calibration not finished. */
+		return;
+	}
+	/* Noisefloor calibration is finished. */
+	ar5008_read_noisefloor(sc, nf, nf_ext);
+
+	/* Update noisefloor history. */
+	for (i = 0; i < sc->nrxchains; i++) {
+		sc->nf_hist[sc->nf_hist_cur].nf[i] = nf[i];
+		sc->nf_hist[sc->nf_hist_cur].nf_ext[i] = nf_ext[i];
+	}
+	if (++sc->nf_hist_cur >= ATHN_NF_CAL_HIST_MAX)
+		sc->nf_hist_cur = 0;
+}
+
+void
+ar5008_bb_load_noisefloor(struct athn_softc *sc)
+{
+	int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+	int i, ntries;
+
+	/* Write filtered noisefloor values. */
+	for (i = 0; i < sc->nrxchains; i++) {
+		nf[i] = sc->nf_priv[i] * 2;
+		nf_ext[i] = sc->nf_ext_priv[i] * 2;
+	}
+	ar5008_write_noisefloor(sc, nf, nf_ext);
+
+	/* Load filtered noisefloor values into baseband. */
+	AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+	/* Wait for load to complete. */
+	for (ntries = 0; ntries < 5; ntries++) {
+		if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
+			break;
+		DELAY(50);
+	}
+#ifdef ATHN_DEBUG
+	if (ntries == 5 && athn_debug > 0)
+		printf("failed to load noisefloor values\n");
+#endif
+
+	/* Restore noisefloor values to initial (max) values. */
+	for (i = 0; i < AR_MAX_CHAINS; i++)
+		nf[i] = nf_ext[i] = -50 * 2;
+	ar5008_write_noisefloor(sc, nf, nf_ext);
+}
+
+void
+ar5008_noisefloor_calib(struct athn_softc *sc)
+{
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+}
+
+void
+ar5008_do_noisefloor_calib(struct athn_softc *sc)
+{
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+}
+
+void
+ar5008_do_calib(struct athn_softc *sc)
+{
+	int log = AR_MAX_LOG_CAL;	/* XXX */
+	uint32_t mode = 0, reg;
+
+	reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
+	reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);
+	AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
+
+	if (sc->calib_mask & ATHN_CAL_ADC_GAIN)
+		mode = AR_PHY_CALMODE_ADC_GAIN;
+	else if (sc->calib_mask & ATHN_CAL_ADC_DC)
+		mode = AR_PHY_CALMODE_ADC_DC_PER;
+	else if (sc->calib_mask & ATHN_CAL_IQ)
+		mode = AR_PHY_CALMODE_IQ;
+	AR_WRITE(sc, AR_PHY_CALMODE, mode);
+
+	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, AR_PHY_TIMING_CTRL4_DO_CAL);
+}
+
+void
+ar5008_next_calib(struct athn_softc *sc)
+{
+	if (AR_READ(sc, AR_PHY_TIMING_CTRL4_0) & AR_PHY_TIMING_CTRL4_DO_CAL) {
+		/* Calibration in progress, come back later. */
+		return;
+	}
+	if (sc->calib_mask & ATHN_CAL_ADC_GAIN)
+		ar5008_calib_iq(sc);
+	else if (sc->calib_mask & ATHN_CAL_ADC_DC)
+		ar5008_calib_adc_gain(sc);
+	else if (sc->calib_mask & ATHN_CAL_IQ)
+		ar5008_calib_adc_dc_off(sc);
+}
+
+void
+ar5008_calib_iq(struct athn_softc *sc)
+{
+	struct athn_iq_cal *cal;
+	uint32_t reg, i_coff_denom, q_coff_denom;
+	int32_t i_coff, q_coff;
+	int i, iq_corr_neg;
+
+	for (i = 0; i < AR_MAX_CHAINS; i++) {
+		cal = &sc->calib.iq[i];
+
+		/* Accumulate IQ calibration measures (clear on read). */
+		cal->pwr_meas_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
+		cal->pwr_meas_q += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
+		cal->iq_corr_meas +=
+		    (int32_t)AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
+	}
+	if (++sc->calib.nsamples < AR_CAL_SAMPLES) {
+		/* Not enough samples accumulated, continue. */
+		ar5008_do_calib(sc);
+		return;
+	}
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		cal = &sc->calib.iq[i];
+
+		if (cal->pwr_meas_q == 0)
+			continue;
+
+		if ((iq_corr_neg = cal->iq_corr_meas < 0))
+			cal->iq_corr_meas = -cal->iq_corr_meas;
+
+		i_coff_denom =
+		    (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 128;
+		q_coff_denom = cal->pwr_meas_q / 64;
+
+		if (i_coff_denom == 0 || q_coff_denom == 0)
+			continue;	/* Prevents division by zero. */
+
+		i_coff = cal->iq_corr_meas / i_coff_denom;
+		q_coff = (cal->pwr_meas_i / q_coff_denom) - 64;
+
+		/* Negate i_coff if iq_corr_meas is positive. */
+		if (!iq_corr_neg)
+			i_coff = 0x40 - (i_coff & 0x3f);
+		if (q_coff > 15)
+			q_coff = 15;
+		else if (q_coff <= -16)
+			q_coff = -16;	/* XXX Linux has a bug here? */
+
+		DPRINTFN(2, ("IQ calibration for chain %d\n", i));
+		reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));
+		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
+		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);
+		AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);
+	}
+
+	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
+	    AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
+}
+
+void
+ar5008_calib_adc_gain(struct athn_softc *sc)
+{
+	struct athn_adc_cal *cal;
+	uint32_t reg, gain_mismatch_i, gain_mismatch_q;
+	int i;
+
+	for (i = 0; i < AR_MAX_CHAINS; i++) {
+		cal = &sc->calib.adc_gain[i];
+
+		/* Accumulate ADC gain measures (clear on read). */
+		cal->pwr_meas_odd_i  += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
+		cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
+		cal->pwr_meas_odd_q  += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
+		cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
+	}
+	if (++sc->calib.nsamples < AR_CAL_SAMPLES) {
+		/* Not enough samples accumulated, continue. */
+		ar5008_do_calib(sc);
+		return;
+	}
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		cal = &sc->calib.adc_gain[i];
+
+		if (cal->pwr_meas_odd_i == 0 || cal->pwr_meas_even_q == 0)
+			continue;	/* Prevents division by zero. */
+
+		gain_mismatch_i =
+		    (cal->pwr_meas_even_i * 32) / cal->pwr_meas_odd_i;
+		gain_mismatch_q =
+		    (cal->pwr_meas_odd_q * 32) / cal->pwr_meas_even_q;
+
+		DPRINTFN(2, ("ADC gain calibration for chain %d\n", i));
+		reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
+		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);
+		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);
+		AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
+	}
+
+	AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
+	    AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
+}
+
+void
+ar5008_calib_adc_dc_off(struct athn_softc *sc)
+{
+	struct athn_adc_cal *cal;
+	int32_t dc_offset_mismatch_i, dc_offset_mismatch_q;
+	uint32_t reg;
+	int count, i;
+
+	for (i = 0; i < AR_MAX_CHAINS; i++) {
+		cal = &sc->calib.adc_dc_offset[i];
+
+		/* Accumulate ADC DC offset measures (clear on read). */
+		cal->pwr_meas_odd_i  += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
+		cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
+		cal->pwr_meas_odd_q  += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
+		cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
+	}
+	if (++sc->calib.nsamples < AR_CAL_SAMPLES) {
+		/* Not enough samples accumulated, continue. */
+		ar5008_do_calib(sc);
+		return;
+	}
+
+	count = (1 << (AR_MAX_LOG_CAL + 5)) * sc->calib.nsamples;
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		cal = &sc->calib.adc_dc_offset[i];
+
+		dc_offset_mismatch_i =
+		    (cal->pwr_meas_even_i - cal->pwr_meas_odd_i * 2) / count;
+		dc_offset_mismatch_q =
+		    (cal->pwr_meas_odd_q - cal->pwr_meas_even_q * 2) / count;
+
+		DPRINTFN(2, ("ADC DC offset calibration for chain %d\n", i));
+		reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
+		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,
+		    dc_offset_mismatch_q);
+		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,
+		    dc_offset_mismatch_i);
+		AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
+	}
+
+	AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
+	    AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
+}
+
+void
+ar5008_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
+{
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE1,
+	    (power[ATHN_POWER_OFDM18  ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_OFDM12  ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_OFDM9   ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_OFDM6   ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE2,
+	    (power[ATHN_POWER_OFDM54  ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_OFDM48  ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_OFDM36  ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_OFDM24  ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE3,
+	    (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_XR      ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_CCK1_LP ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE4,
+	    (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 |
+	    (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 |
+	    (power[ATHN_POWER_CCK55_SP] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_CCK55_LP] & 0x3f));
+#ifndef IEEE80211_NO_HT
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE5,
+	    (power[ATHN_POWER_HT20(3) ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT20(2) ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT20(1) ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT20(0) ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE6,
+	    (power[ATHN_POWER_HT20(7) ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT20(6) ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT20(5) ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT20(4) ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE7,
+	    (power[ATHN_POWER_HT40(3) ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT40(2) ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT40(1) ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT40(0) ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE8,
+	    (power[ATHN_POWER_HT40(7) ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT40(6) ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT40(5) ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT40(4) ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_POWER_TX_RATE9,
+	    (power[ATHN_POWER_OFDM_EXT] & 0x3f) << 24 |
+	    (power[ATHN_POWER_CCK_EXT ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_OFDM_DUP] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_CCK_DUP ] & 0x3f));
+#endif
+}
+
+void
+ar5008_set_viterbi_mask(struct athn_softc *sc, int bin)
+{
+	uint32_t mask[4], reg;
+	uint8_t m[62], p[62];	/* XXX use bit arrays? */
+	int i, bit, cur;
+
+	/* Compute pilot mask. */
+	cur = -6000;
+	for (i = 0; i < 4; i++) {
+		mask[i] = 0;
+		for (bit = 0; bit < 30; bit++) {
+			if (abs(cur - bin) < 100)
+				mask[i] |= 1 << bit;
+			cur += 100;
+		}
+		if (cur == 0)	/* Skip entry "0". */
+			cur = 100;
+	}
+	/* Write entries from -6000 to -3100. */
+	AR_WRITE(sc, AR_PHY_TIMING7, mask[0]);
+	AR_WRITE(sc, AR_PHY_TIMING9, mask[0]);
+	/* Write entries from -3000 to -100. */
+	AR_WRITE(sc, AR_PHY_TIMING8, mask[1]);
+	AR_WRITE(sc, AR_PHY_TIMING10, mask[1]);
+	/* Write entries from 100 to 3000. */
+	AR_WRITE(sc, AR_PHY_PILOT_MASK_01_30, mask[2]);
+	AR_WRITE(sc, AR_PHY_CHANNEL_MASK_01_30, mask[2]);
+	/* Write entries from 3100 to 6000. */
+	AR_WRITE(sc, AR_PHY_PILOT_MASK_31_60, mask[3]);
+	AR_WRITE(sc, AR_PHY_CHANNEL_MASK_31_60, mask[3]);
+
+	/* Compute viterbi mask. */
+	for (cur = 6100; cur >= 0; cur -= 100)
+		p[+cur / 100] = abs(cur - bin) < 75;
+	for (cur = -100; cur >= -6100; cur -= 100)
+		m[-cur / 100] = abs(cur - bin) < 75;
+
+	/* Write viterbi mask (XXX needs to be reworked.) */
+	reg =
+	    m[46] << 30 | m[47] << 28 | m[48] << 26 | m[49] << 24 |
+	    m[50] << 22 | m[51] << 20 | m[52] << 18 | m[53] << 16 |
+	    m[54] << 14 | m[55] << 12 | m[56] << 10 | m[57] <<  8 |
+	    m[58] <<  6 | m[59] <<  4 | m[60] <<  2 | m[61] <<  0;
+	AR_WRITE(sc, AR_PHY_BIN_MASK_1, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_46_61, reg);
+
+	/* XXX m[48] should be m[38] ? */
+	reg =             m[31] << 28 | m[32] << 26 | m[33] << 24 |
+	    m[34] << 22 | m[35] << 20 | m[36] << 18 | m[37] << 16 |
+	    m[48] << 14 | m[39] << 12 | m[40] << 10 | m[41] <<  8 |
+	    m[42] <<  6 | m[43] <<  4 | m[44] <<  2 | m[45] <<  0;
+	AR_WRITE(sc, AR_PHY_BIN_MASK_2, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_31_45, reg);
+
+	/* XXX This one is weird too. */
+	reg =
+	    m[16] << 30 | m[16] << 28 | m[18] << 26 | m[18] << 24 |
+	    m[20] << 22 | m[20] << 20 | m[22] << 18 | m[22] << 16 |
+	    m[24] << 14 | m[24] << 12 | m[25] << 10 | m[26] <<  8 |
+	    m[27] <<  6 | m[28] <<  4 | m[29] <<  2 | m[30] <<  0;
+	AR_WRITE(sc, AR_PHY_BIN_MASK_3, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_16_30, reg);
+
+	reg =
+	    m[ 0] << 30 | m[ 1] << 28 | m[ 2] << 26 | m[ 3] << 24 |
+	    m[ 4] << 22 | m[ 5] << 20 | m[ 6] << 18 | m[ 7] << 16 |
+	    m[ 8] << 14 | m[ 9] << 12 | m[10] << 10 | m[11] <<  8 |
+	    m[12] <<  6 | m[13] <<  4 | m[14] <<  2 | m[15] <<  0;
+	AR_WRITE(sc, AR_PHY_MASK_CTL, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_00_15, reg);
+
+	reg =             p[15] << 28 | p[14] << 26 | p[13] << 24 |
+	    p[12] << 22 | p[11] << 20 | p[10] << 18 | p[ 9] << 16 |
+	    p[ 8] << 14 | p[ 7] << 12 | p[ 6] << 10 | p[ 5] <<  8 |
+	    p[ 4] <<  6 | p[ 3] <<  4 | p[ 2] <<  2 | p[ 1] <<  0;
+	AR_WRITE(sc, AR_PHY_BIN_MASK2_1, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_15_01, reg);
+
+	reg =             p[30] << 28 | p[29] << 26 | p[28] << 24 |
+	    p[27] << 22 | p[26] << 20 | p[25] << 18 | p[24] << 16 |
+	    p[23] << 14 | p[22] << 12 | p[21] << 10 | p[20] <<  8 |
+	    p[19] <<  6 | p[18] <<  4 | p[17] <<  2 | p[16] <<  0;
+	AR_WRITE(sc, AR_PHY_BIN_MASK2_2, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_30_16, reg);
+
+	reg =             p[45] << 28 | p[44] << 26 | p[43] << 24 |
+	    p[42] << 22 | p[41] << 20 | p[40] << 18 | p[39] << 16 |
+	    p[38] << 14 | p[37] << 12 | p[36] << 10 | p[35] <<  8 |
+	    p[34] <<  6 | p[33] <<  4 | p[32] <<  2 | p[31] <<  0;
+	AR_WRITE(sc, AR_PHY_BIN_MASK2_3, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_45_31, reg);
+
+	reg =
+	    p[61] << 30 | p[60] << 28 | p[59] << 26 | p[58] << 24 |
+	    p[57] << 22 | p[56] << 20 | p[55] << 18 | p[54] << 16 |
+	    p[53] << 14 | p[52] << 12 | p[51] << 10 | p[50] <<  8 |
+	    p[49] <<  6 | p[48] <<  4 | p[47] <<  2 | p[46] <<  0;
+	AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);
+	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);
+}
+
+void
+ar5008_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	struct athn_ops *ops = &sc->ops;
+	const struct athn_ini *ini = sc->ini;
+	const uint32_t *pvals;
+	int i;
+
+	AR_WRITE(sc, AR_PHY(0), 0x00000007);
+	AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
+
+	if (!AR_SINGLE_CHIP(sc))
+		ar5416_reset_addac(sc, c);
+
+	AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
+
+	/* First initialization step (depends on channel band/bandwidth). */
+#ifndef IEEE80211_NO_HT
+	if (extc != NULL) {
+		if (IEEE80211_IS_CHAN_2GHZ(c))
+			pvals = ini->vals_2g40;
+		else
+			pvals = ini->vals_5g40;
+	} else
+#endif
+	{
+		if (IEEE80211_IS_CHAN_2GHZ(c))
+			pvals = ini->vals_2g20;
+		else
+			pvals = ini->vals_5g20;
+	}
+	DPRINTFN(4, ("writing modal init vals\n"));
+	for (i = 0; i < ini->nregs; i++) {
+		AR_WRITE(sc, ini->regs[i], pvals[i]);
+		if (AR_IS_ANALOG_REG(ini->regs[i]))
+			DELAY(100);
+		if ((i & 0x1f) == 0)
+			DELAY(1);
+	}
+
+	if (sc->rx_gain != NULL)
+		ar9280_reset_rx_gain(sc, c);
+	if (sc->tx_gain != NULL)
+		ar9280_reset_tx_gain(sc, c);
+
+	/* Second initialization step (common to all channels). */
+	DPRINTFN(4, ("writing common init vals\n"));
+	for (i = 0; i < ini->ncmregs; i++) {
+		AR_WRITE(sc, ini->cmregs[i], ini->cmvals[i]);
+		if (AR_IS_ANALOG_REG(ini->cmregs[i]))
+			DELAY(100);
+		if ((i & 0x1f) == 0)
+			DELAY(1);
+	}
+
+	if (!AR_SINGLE_CHIP(sc))
+		ar5416_reset_bb_gain(sc, c);
+
+	/*
+	 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted
+	 * descriptor status.
+	 */
+	AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+
+	/* Hardware workarounds for occasional Rx data corruption. */
+	if (AR_SREV_9287_10_OR_LATER(sc))
+		AR_CLRBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_HWWAR1);
+	else if (AR_SREV_9280_10_OR_LATER(sc))
+		AR_CLRBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_HWWAR1 |
+		    AR_PCU_MISC_MODE2_HWWAR2);
+
+	if (AR_SREV_5416_20_OR_LATER(sc) && !AR_SREV_9280_10_OR_LATER(sc)) {
+		/* Disable baseband clock gating. */
+		AR_WRITE(sc, AR_PHY(651), 0x11);
+
+		if (AR_SREV_9160(sc)) {
+			/* Disable RIFS search to fix baseband hang. */
+			AR_CLRBITS(sc, AR_PHY_HEAVY_CLIP_FACTOR_RIFS,
+			    AR_PHY_RIFS_INIT_DELAY_M);
+		}
+	}
+
+	ar5008_set_phy(sc, c, extc);
+	ar5008_init_chains(sc);
+
+	if (sc->flags & ATHN_FLAG_OLPC)
+		ops->olpc_init(sc);
+	ops->set_txpower(sc, c, extc);
+
+	if (!AR_SINGLE_CHIP(sc))
+		ar5416_rf_reset(sc, c);
+}
+
+uint8_t
+ar5008_get_vpd(uint8_t pwr, const uint8_t *pwrPdg, const uint8_t *vpdPdg,
+    int nicepts)
+{
+	uint8_t vpd;
+	int i, lo, hi;
+
+	for (i = 0; i < nicepts; i++)
+		if (pwrPdg[i] > pwr)
+			break;
+	hi = i;
+	lo = hi - 1;
+	if (lo == -1)
+		lo = hi;
+	else if (hi == nicepts)
+		hi = lo;
+
+	vpd = athn_interpolate(pwr, pwrPdg[lo], vpdPdg[lo],
+	    pwrPdg[hi], vpdPdg[hi]);
+	return (vpd);
+}
+
+void
+ar5008_get_pdadcs(struct athn_softc *sc, uint8_t fbin,
+    struct athn_pier *lopier, struct athn_pier *hipier, int nxpdgains,
+    int nicepts, uint8_t overlap, uint8_t *boundaries, uint8_t *pdadcs)
+{
+#define DB(x)	((x) / 2)	/* Convert half dB to dB. */
+	uint8_t minpwr[AR_PD_GAINS_IN_MASK], maxpwr[AR_PD_GAINS_IN_MASK];
+	uint8_t vpd[AR_MAX_PWR_RANGE_IN_HALF_DB], pwr;
+	uint8_t lovpd, hivpd, boundary;
+	int16_t ss, delta, vpdstep, val;
+	int i, j, npdadcs, nvpds, maxidx, tgtidx;
+
+	/* Compute min and max power in half dB for each pdGain. */
+	for (i = 0; i < nxpdgains; i++) {
+		minpwr[i] = MAX(lopier->pwr[i][0], hipier->pwr[i][0]);
+		maxpwr[i] = MIN(lopier->pwr[i][nicepts - 1],
+		    hipier->pwr[i][nicepts - 1]);
+	}
+
+	npdadcs = 0;
+	for (i = 0; i < nxpdgains; i++) {
+		if (i != nxpdgains - 1)
+			boundaries[i] = DB(maxpwr[i] + minpwr[i + 1]) / 2;
+		else
+			boundaries[i] = DB(maxpwr[i]);
+		if (boundaries[i] > AR_MAX_RATE_POWER)
+			boundaries[i] = AR_MAX_RATE_POWER;
+
+		if (i == 0 && !AR_SREV_5416_20_OR_LATER(sc)) {
+			/* Fix the gain delta (AR5416 1.0 only.) */
+			delta = boundaries[0] - 23;
+			boundaries[0] = 23;
+		} else
+			delta = 0;
+
+		/* Find starting index for this pdGain. */
+		if (i != 0) {
+			ss = boundaries[i - 1] - DB(minpwr[i]) -
+			    overlap + 1 + delta;
+		} else if (AR_SREV_9280_10_OR_LATER(sc)) {
+			ss = -DB(minpwr[i]);
+		} else
+			ss = 0;
+
+		/* Compute Vpd table for this pdGain. */
+		nvpds = DB(maxpwr[i] - minpwr[i]) + 1;
+		memset(vpd, 0, sizeof(vpd));
+		pwr = minpwr[i];
+		for (j = 0; j < nvpds; j++) {
+			/* Get lower and higher Vpd. */
+			lovpd = ar5008_get_vpd(pwr, lopier->pwr[i],
+			    lopier->vpd[i], nicepts);
+			hivpd = ar5008_get_vpd(pwr, hipier->pwr[i],
+			    hipier->vpd[i], nicepts);
+
+			/* Interpolate the final Vpd. */
+			vpd[j] = athn_interpolate(fbin,
+			    lopier->fbin, lovpd, hipier->fbin, hivpd);
+
+			pwr += 2;	/* In half dB. */
+		}
+
+		/* Extrapolate data for ss < 0. */
+		if (vpd[1] > vpd[0])
+			vpdstep = vpd[1] - vpd[0];
+		else
+			vpdstep = 1;
+		while (ss < 0 && npdadcs < AR_NUM_PDADC_VALUES - 1) {
+			val = vpd[0] + ss * vpdstep;
+			pdadcs[npdadcs++] = MAX(val, 0);
+			ss++;
+		}
+
+		tgtidx = boundaries[i] + overlap - DB(minpwr[i]);
+		maxidx = MIN(tgtidx, nvpds);
+		while (ss < maxidx && npdadcs < AR_NUM_PDADC_VALUES - 1)
+			pdadcs[npdadcs++] = vpd[ss++];
+
+		if (tgtidx <= maxidx)
+			continue;
+
+		/* Extrapolate data for maxidx <= ss <= tgtidx. */
+		if (vpd[nvpds - 1] > vpd[nvpds - 2])
+			vpdstep = vpd[nvpds - 1] - vpd[nvpds - 2];
+		else
+			vpdstep = 1;
+		while (ss <= tgtidx && npdadcs < AR_NUM_PDADC_VALUES - 1) {
+			val = vpd[nvpds - 1] + (ss - maxidx + 1) * vpdstep;
+			pdadcs[npdadcs++] = MIN(val, 255);
+			ss++;
+		}
+	}
+
+	/* Fill remaining PDADC and boundaries entries. */
+	if (AR_SREV_9285(sc))
+		boundary = AR9285_PD_GAIN_BOUNDARY_DEFAULT;
+	else	/* Fill with latest. */
+		boundary = boundaries[nxpdgains - 1];
+
+	for (; nxpdgains < AR_PD_GAINS_IN_MASK; nxpdgains++)
+		boundaries[nxpdgains] = boundary;
+
+	for (; npdadcs < AR_NUM_PDADC_VALUES; npdadcs++)
+		pdadcs[npdadcs] = pdadcs[npdadcs - 1];
+#undef DB
+}
+
+void
+ar5008_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+    uint8_t ctl, const struct ar_cal_target_power_leg *tgt, int nchans,
+    uint8_t tpow[4])
+{
+	uint8_t fbin;
+	int i, lo, hi;
+
+	/* Find interval (lower and upper indices.) */
+	fbin = athn_chan2fbin(c);
+	for (i = 0; i < nchans; i++) {
+		if (tgt[i].bChannel == AR_BCHAN_UNUSED ||
+		    tgt[i].bChannel > fbin)
+			break;
+	}
+	hi = i;
+	lo = hi - 1;
+	if (lo == -1)
+		lo = hi;
+	else if (hi == nchans || tgt[hi].bChannel == AR_BCHAN_UNUSED)
+		hi = lo;
+
+	/* Interpolate values. */
+	for (i = 0; i < 4; i++) {
+		tpow[i] = athn_interpolate(fbin,
+		    tgt[lo].bChannel, tgt[lo].tPow2x[i],
+		    tgt[hi].bChannel, tgt[hi].tPow2x[i]);
+	}
+	/* XXX Apply conformance test limit. */
+}
+
+#ifndef IEEE80211_NO_HT
+void
+ar5008_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+    uint8_t ctl, const struct ar_cal_target_power_ht *tgt, int nchans,
+    uint8_t tpow[8])
+{
+	uint8_t fbin;
+	int i, lo, hi;
+
+	/* Find interval (lower and upper indices.) */
+	fbin = athn_chan2fbin(c);
+	for (i = 0; i < nchans; i++) {
+		if (tgt[i].bChannel == AR_BCHAN_UNUSED ||
+		    tgt[i].bChannel > fbin)
+			break;
+	}
+	hi = i;
+	lo = hi - 1;
+	if (lo == -1)
+		lo = hi;
+	else if (hi == nchans || tgt[hi].bChannel == AR_BCHAN_UNUSED)
+		hi = lo;
+
+	/* Interpolate values. */
+	for (i = 0; i < 8; i++) {
+		tpow[i] = athn_interpolate(fbin,
+		    tgt[lo].bChannel, tgt[lo].tPow2x[i],
+		    tgt[hi].bChannel, tgt[hi].tPow2x[i]);
+	}
+	/* XXX Apply conformance test limit. */
+}
+#endif
+
+/*
+ * Adaptive noise immunity.
+ */
+void
+ar5008_set_noise_immunity_level(struct athn_softc *sc, int level)
+{
+	int high = level == 4;
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+	reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
+	AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+	reg = AR_READ(sc, AR_PHY_AGC_CTL1);
+	reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);
+	reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);
+	AR_WRITE(sc, AR_PHY_AGC_CTL1, reg);
+
+	reg = AR_READ(sc, AR_PHY_FIND_SIG);
+	reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
+	AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+}
+
+void
+ar5008_enable_ofdm_weak_signal(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
+	AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR);
+	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
+	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
+	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
+	AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
+	AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+	AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
+	    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+}
+
+void
+ar5008_disable_ofdm_weak_signal(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
+	AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR);
+	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
+	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
+	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
+	AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
+	AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+	AR_CLRBITS(sc, AR_PHY_SFCORR_LOW,
+	    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+}
+
+void
+ar5008_set_cck_weak_signal(struct athn_softc *sc, int high)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_CCK_DETECT);
+	reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
+	AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+}
+
+void
+ar5008_set_firstep_level(struct athn_softc *sc, int level)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_FIND_SIG);
+	reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
+	AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+}
+
+void
+ar5008_set_spur_immunity_level(struct athn_softc *sc, int level)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_TIMING5);
+	reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
+	AR_WRITE(sc, AR_PHY_TIMING5, reg);
+}
diff --git a/sys/dev/ic/ar5008reg.h b/sys/dev/ic/ar5008reg.h
new file mode 100644
index 00000000000..9c9caf27c94
--- /dev/null
+++ b/sys/dev/ic/ar5008reg.h
@@ -0,0 +1,1015 @@
+/*	$OpenBSD: ar5008reg.h,v 1.1 2010/05/10 17:44:21 damien Exp $	*/
+
+/*-
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * MAC registers.
+ */
+#define AR_ISR_S2_S			0x00cc
+#define AR_ISR_S3_S			0x00d0
+#define AR_ISR_S4_S			0x00d4
+#define AR_ISR_S5_S			0x00d8
+#define AR_GPIO_IN_OUT			0x4048
+#define AR_GPIO_OE_OUT			0x404c
+#define AR_GPIO_INTR_POL		0x4050
+#define AR_GPIO_INPUT_EN_VAL		0x4054
+#define AR_GPIO_INPUT_MUX1		0x4058
+#define AR_GPIO_INPUT_MUX2		0x405c
+#define AR_GPIO_OUTPUT_MUX(i)		(0x4060 + (i) * 4)
+#define AR_INPUT_STATE			0x406c
+#define AR_EEPROM_STATUS_DATA		0x407c
+#define AR_OBS				0x4080
+#define AR_GPIO_PDPU			0x4088
+#define AR_PCIE_MSI			0x4094
+
+/*
+ * Analog registers.
+ */
+#define AR_IS_ANALOG_REG(reg)		((reg) >= 0x7800 && (reg) <= 0x78b4)
+#define AR_AN_RF2G1_CH0			0x7810
+#define AR_AN_RF5G1_CH0			0x7818
+#define AR_AN_RF2G1_CH1			0x7834
+#define AR_AN_RF5G1_CH1			0x783c
+#define AR_AN_SYNTH9			0x7868
+#define AR_AN_TOP1			0x7890
+#define AR_AN_TOP2			0x7894
+
+/*
+ * PHY registers.
+ */
+#define AR_PHY_BASE			0x9800
+#define AR_PHY(i)			(AR_PHY_BASE + (i) * 4)
+#define AR_PHY_TEST			0x9800
+#define AR_PHY_TURBO			0x9804
+#define AR_PHY_TEST2			0x9808
+#define AR_PHY_TIMING2			0x9810
+#define AR_PHY_TIMING3			0x9814
+#define AR_PHY_CHIP_ID			0x9818
+#define AR_PHY_ACTIVE			0x981c
+#define AR_PHY_RF_CTL2			0x9824
+#define AR_PHY_RF_CTL3			0x9828
+#define AR_PHY_ADC_CTL			0x982c
+#define AR_PHY_ADC_SERIAL_CTL		0x9830
+#define AR_PHY_RF_CTL4			0x9834
+#define AR_PHY_TSTDAC_CONST		0x983c
+#define AR_PHY_SETTLING			0x9844
+#define AR_PHY_RXGAIN			0x9848
+#define AR_PHY_DESIRED_SZ		0x9850
+#define AR_PHY_FIND_SIG			0x9858
+#define AR_PHY_AGC_CTL1			0x985c
+#define AR_PHY_AGC_CONTROL		0x9860
+#define AR_PHY_CCA(i)			(0x9864 + (i) * 0x1000)
+#define AR_PHY_SFCORR			0x9868
+#define AR_PHY_SFCORR_LOW		0x986c
+#define AR_PHY_SLEEP_CTR_CONTROL	0x9870
+#define AR_PHY_SLEEP_CTR_LIMIT		0x9874
+#define AR_PHY_SLEEP_SCAL		0x9878
+#define AR_PHY_PLL_CTL			0x987c
+#define AR_PHY_BIN_MASK_1		0x9900
+#define AR_PHY_BIN_MASK_2		0x9904
+#define AR_PHY_BIN_MASK_3		0x9908
+#define AR_PHY_MASK_CTL			0x990c
+#define AR_PHY_RX_DELAY			0x9914
+#define AR_PHY_SEARCH_START_DELAY	0x9918
+#define AR_PHY_TIMING_CTRL4_0		0x9920
+#define AR_PHY_TIMING_CTRL4(i)		(0x9920 + (i) * 0x1000)
+#define AR_PHY_TIMING5			0x9924
+#define AR_PHY_POWER_TX_RATE1		0x9934
+#define AR_PHY_POWER_TX_RATE2		0x9938
+#define AR_PHY_POWER_TX_RATE_MAX	0x993c
+#define AR_PHY_RADAR_EXT		0x9940
+#define AR_PHY_FRAME_CTL		0x9944
+#define AR_PHY_SPUR_REG			0x994c
+#define AR_PHY_RADAR_0			0x9954
+#define AR_PHY_RADAR_1			0x9958
+#define AR_PHY_SWITCH_CHAIN_0		0x9960
+#define AR_PHY_SWITCH_COM		0x9964
+#define AR_PHY_SIGMA_DELTA		0x996c
+#define AR_PHY_RESTART			0x9970
+#define AR_PHY_RFBUS_REQ		0x997c
+#define AR_PHY_TIMING7			0x9980
+#define AR_PHY_TIMING8			0x9984
+#define AR_PHY_BIN_MASK2_1		0x9988
+#define AR_PHY_BIN_MASK2_2		0x998c
+#define AR_PHY_BIN_MASK2_3		0x9990
+#define AR_PHY_BIN_MASK2_4		0x9994
+#define AR_PHY_TIMING9			0x9998
+#define AR_PHY_TIMING10			0x999c
+#define AR_PHY_TIMING11			0x99a0
+#define AR_PHY_RX_CHAINMASK		0x99a4
+#define AR_PHY_MULTICHAIN_GAIN_CTL	0x99ac
+#define AR_PHY_NEW_ADC_DC_GAIN_CORR(i)	(0x99b4 + (i) * 0x1000)
+#define AR_PHY_EXT_CCA0			0x99b8
+#define AR_PHY_EXT_CCA(i)		(0x99bc + (i) * 0x1000)
+#define AR_PHY_SFCORR_EXT		0x99c0
+#define AR_PHY_HALFGI			0x99d0
+#define AR_PHY_CHANNEL_MASK_01_30	0x99d4
+#define AR_PHY_CHANNEL_MASK_31_60	0x99d8
+#define AR_PHY_CHAN_INFO_MEMORY		0x99dc
+#define AR_PHY_HEAVY_CLIP_ENABLE	0x99e0
+#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS	0x99ec
+#define AR_PHY_CALMODE			0x99f0
+#define AR_PHY_REFCLKDLY		0x99f4
+#define AR_PHY_REFCLKPD			0x99f8
+#define AR_PHY_BB_RFGAIN(i)		(0x9a00 + (i) * 4)
+#define AR_PHY_CAL_MEAS_0(i)		(0x9c10 + (i) * 0x1000)
+#define AR_PHY_CAL_MEAS_1(i)		(0x9c14 + (i) * 0x1000)
+#define AR_PHY_CAL_MEAS_2(i)		(0x9c18 + (i) * 0x1000)
+#define AR_PHY_CAL_MEAS_3(i)		(0x9c1c + (i) * 0x1000)
+#define AR_PHY_CURRENT_RSSI		0x9c1c
+#define AR_PHY_RFBUS_GRANT		0x9c20
+#define AR9280_PHY_CURRENT_RSSI		0x9c3c
+#define AR_PHY_CHAN_INFO_GAIN_DIFF	0x9cf4
+#define AR_PHY_CHAN_INFO_GAIN		0x9cfc
+#define AR_PHY_MODE			0xa200
+#define AR_PHY_CCK_TX_CTRL		0xa204
+#define AR_PHY_CCK_DETECT		0xa208
+#define AR_PHY_GAIN_2GHZ		0xa20c
+#define AR_PHY_CCK_RXCTRL4		0xa21c
+#define AR_PHY_DAG_CTRLCCK		0xa228
+#define AR_PHY_FORCE_CLKEN_CCK		0xa22c
+#define AR_PHY_POWER_TX_RATE3		0xa234
+#define AR_PHY_POWER_TX_RATE4		0xa238
+#define AR_PHY_SCRM_SEQ_XR		0xa23c
+#define AR_PHY_HEADER_DETECT_XR		0xa240
+#define AR_PHY_CHIRP_DETECTED_XR	0xa244
+#define AR_PHY_BLUETOOTH		0xa254
+#define AR_PHY_TPCRG1			0xa258
+#define AR_PHY_TX_PWRCTRL4		0xa264
+#define AR_PHY_ANALOG_SWAP		0xa268
+#define AR_PHY_TPCRG5			0xa26c
+#define AR_PHY_TX_PWRCTRL6_0		0xa270
+#define AR_PHY_TX_PWRCTRL7		0xa274
+#define AR_PHY_TX_PWRCTRL9		0xa27c
+#define AR_PHY_PDADC_TBL_BASE		0xa280
+#define AR_PHY_TX_GAIN_TBL(i)		(0xa300 + (i) * 4)
+#define AR_PHY_CL_CAL_CTL		0xa358
+#define AR_PHY_CLC_TBL(i)		(0xa35c + (i) * 4)
+#define AR_PHY_POWER_TX_RATE5		0xa38c
+#define AR_PHY_POWER_TX_RATE6		0xa390
+#define AR_PHY_CH0_TX_PWRCTRL11		0xa398
+#define AR_PHY_CAL_CHAINMASK		0xa39c
+#define AR_PHY_VIT_MASK2_M_46_61	0xa3a0
+#define AR_PHY_VIT_MASK2_M_31_45	0xa3a4
+#define AR_PHY_VIT_MASK2_M_16_30	0xa3a8
+#define AR_PHY_VIT_MASK2_M_00_15	0xa3ac
+#define AR_PHY_PILOT_MASK_01_30		0xa3b0
+#define AR_PHY_PILOT_MASK_31_60		0xa3b4
+#define AR_PHY_VIT_MASK2_P_15_01	0xa3b8
+#define AR_PHY_VIT_MASK2_P_30_16	0xa3bc
+#define AR_PHY_VIT_MASK2_P_45_31	0xa3c0
+#define AR_PHY_VIT_MASK2_P_61_46	0xa3c4
+#define AR_PHY_POWER_TX_SUB		0xa3c8
+#define AR_PHY_POWER_TX_RATE7		0xa3cc
+#define AR_PHY_POWER_TX_RATE8		0xa3d0
+#define AR_PHY_POWER_TX_RATE9		0xa3d4
+#define AR_PHY_XPA_CFG			0xa3d8
+#define AR_PHY_TX_PWRCTRL6_1		0xb270
+#define AR_PHY_CH1_TX_PWRCTRL11		0xb398
+
+
+/* Bits for AR_AN_RF2G1_CH0. */
+#define AR_AN_RF2G1_CH0_OB_M	0x03800000
+#define AR_AN_RF2G1_CH0_OB_S	23
+#define AR_AN_RF2G1_CH0_DB_M	0x1c000000
+#define AR_AN_RF2G1_CH0_DB_S	26
+
+/* Bits for AR_AN_RF5G1_CH0. */
+#define AR_AN_RF5G1_CH0_OB5_M	0x00070000
+#define AR_AN_RF5G1_CH0_OB5_S	16
+#define AR_AN_RF5G1_CH0_DB5_M	0x00380000
+#define AR_AN_RF5G1_CH0_DB5_S	19
+
+/* Bits for AR_AN_RF2G1_CH1. */
+#define AR_AN_RF2G1_CH1_OB_M	0x03800000
+#define AR_AN_RF2G1_CH1_OB_S	23
+#define AR_AN_RF2G1_CH1_DB_M	0x1c000000
+#define AR_AN_RF2G1_CH1_DB_S	26
+
+/* Bits for AR_AN_RF5G1_CH1. */
+#define AR_AN_RF5G1_CH1_OB5_M	0x00070000
+#define AR_AN_RF5G1_CH1_OB5_S	16
+#define AR_AN_RF5G1_CH1_DB5_M	0x00380000
+#define AR_AN_RF5G1_CH1_DB5_S	19
+
+/* Bits for AR_AN_SYNTH9. */
+#define AR_AN_SYNTH9_REFDIVA_M	0xf8000000
+#define AR_AN_SYNTH9_REFDIVA_S	27
+
+/* Bits for AR_AN_TOP1. */
+#define AR_AN_TOP1_DACLPMODE	0x00040000
+
+/* Bits for AR_AN_TOP2. */
+#define AR_AN_TOP2_XPABIAS_LVL_M	0xc0000000
+#define AR_AN_TOP2_XPABIAS_LVL_S	30
+#define AR_AN_TOP2_LOCALBIAS		0x00200000
+#define AR_AN_TOP2_PWDCLKIND		0x00400000
+
+/* Bits for AR_PHY_TEST. */
+#define AR_PHY_TEST_RFSILENT_BB	0x00002000
+#define AR_PHY_TEST_AGC_CLR	0x10000000
+
+/* Bits for AR_PHY_TURBO. */
+#define AR_PHY_FC_TURBO_MODE		0x00000001
+#define AR_PHY_FC_TURBO_SHORT		0x00000002
+#define AR_PHY_FC_DYN2040_EN		0x00000004
+#define AR_PHY_FC_DYN2040_PRI_ONLY	0x00000008
+#define AR_PHY_FC_DYN2040_PRI_CH	0x00000010
+#define AR_PHY_FC_DYN2040_EXT_CH	0x00000020
+#define AR_PHY_FC_HT_EN			0x00000040
+#define AR_PHY_FC_SHORT_GI_40		0x00000080
+#define AR_PHY_FC_WALSH			0x00000100
+#define AR_PHY_FC_SINGLE_HT_LTF1	0x00000200
+#define AR_PHY_FC_ENABLE_DAC_FIFO	0x00000800
+
+/* Bits for AR_PHY_TIMING3. */
+#define AR_PHY_TIMING3_DSC_MAN_M	0xfffe0000
+#define AR_PHY_TIMING3_DSC_MAN_S	17
+#define AR_PHY_TIMING3_DSC_EXP_M	0x0001e000
+#define AR_PHY_TIMING3_DSC_EXP_S	13
+
+/* Bits for AR_PHY_CHIP_ID. */
+#define AR_PHY_CHIP_ID_REV_0		0x00000080
+#define AR_PHY_CHIP_ID_REV_1		0x00000081
+#define AR_PHY_CHIP_ID_9160_REV_0	0x000000b0
+
+/* Bits for AR_PHY_ACTIVE. */
+#define AR_PHY_ACTIVE_EN	0x00000001
+#define AR_PHY_ACTIVE_DIS	0x00000000
+
+/* Bits for AR_PHY_RF_CTL2. */
+#define AR_PHY_TX_END_DATA_START_M	0x000000ff
+#define AR_PHY_TX_END_DATA_START_S	0
+#define AR_PHY_TX_END_PA_ON_M		0x0000ff00
+#define AR_PHY_TX_END_PA_ON_S		8
+
+/* Bits for AR_PHY_RF_CTL3. */
+#define AR_PHY_TX_END_TO_A2_RX_ON_M	0x00ff0000
+#define AR_PHY_TX_END_TO_A2_RX_ON_S	16
+
+/* Bits for AR_PHY_ADC_CTL. */
+#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_M	0x00000003
+#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S	0
+#define AR_PHY_ADC_CTL_OFF_PWDDAC	0x00002000
+#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP	0x00004000
+#define AR_PHY_ADC_CTL_OFF_PWDADC	0x00008000
+#define AR_PHY_ADC_CTL_ON_INBUFGAIN_M	0x00030000
+#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S	16
+
+/* Bits for AR_PHY_ADC_SERIAL_CTL. */
+#define AR_PHY_SEL_INTERNAL_ADDAC	0x00000000
+#define AR_PHY_SEL_EXTERNAL_RADIO	0x00000001
+
+/* Bits for AR_PHY_RF_CTL4. */
+#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_M	0xff000000
+#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S	24
+#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_M	0x00ff0000
+#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S	16
+#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_M		0x0000ff00
+#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S		8
+#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_M		0x000000ff
+#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S		0
+
+/* Bits for AR_PHY_SETTLING. */
+#define AR_PHY_SETTLING_SWITCH_M	0x00003f80
+#define AR_PHY_SETTLING_SWITCH_S	7
+
+/* Bits for AR_PHY_RXGAIN. */
+#define AR_PHY_RXGAIN_TXRX_ATTEN_M	0x0003f000
+#define AR_PHY_RXGAIN_TXRX_ATTEN_S	12
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_M	0x007c0000
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_S	18
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN_M	0x00003f80
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S	7
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN_M	0x001fc000
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S	14
+
+/* Bits for AR_PHY_DESIRED_SZ. */
+#define AR_PHY_DESIRED_SZ_ADC_M		0x000000ff
+#define AR_PHY_DESIRED_SZ_ADC_S		0
+#define AR_PHY_DESIRED_SZ_PGA_M		0x0000ff00
+#define AR_PHY_DESIRED_SZ_PGA_S		8
+#define AR_PHY_DESIRED_SZ_TOT_DES_M	0x0ff00000
+#define AR_PHY_DESIRED_SZ_TOT_DES_S	20
+
+/* Bits for AR_PHY_FIND_SIG. */
+#define AR_PHY_FIND_SIG_FIRSTEP_M	0x0003f000
+#define AR_PHY_FIND_SIG_FIRSTEP_S	12
+#define AR_PHY_FIND_SIG_FIRPWR_M	0x03fc0000
+#define AR_PHY_FIND_SIG_FIRPWR_S	18
+
+/* Bits for AR_PHY_AGC_CTL1. */
+#define AR_PHY_AGC_CTL1_COARSE_LOW_M	0x00007f80
+#define AR_PHY_AGC_CTL1_COARSE_LOW_S	7
+#define AR_PHY_AGC_CTL1_COARSE_HIGH_M	0x003f8000
+#define AR_PHY_AGC_CTL1_COARSE_HIGH_S	15
+
+/* Bits for AR_PHY_AGC_CONTROL. */
+#define AR_PHY_AGC_CONTROL_CAL		0x00000001
+#define AR_PHY_AGC_CONTROL_NF		0x00000002
+#define AR_PHY_AGC_CONTROL_ENABLE_NF	0x00008000
+#define AR_PHY_AGC_CONTROL_FLTR_CAL	0x00010000
+#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF	0x00020000
+
+/* Bits for AR_PHY_CCA. */
+#define AR_PHY_MAXCCA_PWR_M		0x000001ff
+#define AR_PHY_MAXCCA_PWR_S		0
+#define AR_PHY_CCA_THRESH62_M		0x0007f000
+#define AR_PHY_CCA_THRESH62_S		12
+#define AR_PHY_MINCCA_PWR_M		0x0ff80000
+#define AR_PHY_MINCCA_PWR_S		19
+#define AR9280_PHY_CCA_THRESH62_M	0x000ff000
+#define AR9280_PHY_CCA_THRESH62_S	12
+#define AR9280_PHY_MINCCA_PWR_M		0x1ff00000
+#define AR9280_PHY_MINCCA_PWR_S		20
+
+/* Bits for AR_PHY_SFCORR_LOW. */
+#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW	0x00000001
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M	0x00003f00
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S	8
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M	0x001fc000
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S	14
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M	0x0fe00000
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S	21
+
+/* Bits for AR_PHY_SFCORR. */
+#define AR_PHY_SFCORR_M2COUNT_THR_M	0x0000001f
+#define AR_PHY_SFCORR_M2COUNT_THR_S	0
+#define AR_PHY_SFCORR_M1_THRESH_M	0x00fe0000
+#define AR_PHY_SFCORR_M1_THRESH_S	17
+#define AR_PHY_SFCORR_M2_THRESH_M	0x7f000000
+#define AR_PHY_SFCORR_M2_THRESH_S	24
+
+/* Bits for AR_PHY_RX_DELAY. */
+#define AR_PHY_RX_DELAY_DELAY_M	0x00003fff
+#define AR_PHY_RX_DELAY_DELAY_S	0
+
+/* Bits for AR_PHY_TIMING_CTRL4_0. */
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M		0x0000001f
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S		0
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M		0x000007e0
+#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S		5
+#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE		0x00000800
+#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M	0x0000f000
+#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S	12
+#define AR_PHY_TIMING_CTRL4_DO_CAL			0x00010000
+#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK		0x10000000
+#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK		0x20000000
+#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER		0x40000000
+#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI		0x80000000
+
+/* Bits for AR_PHY_TIMING5. */
+#define AR_PHY_TIMING5_CYCPWR_THR1_M	0x000000fe
+#define AR_PHY_TIMING5_CYCPWR_THR1_S	1
+
+/* Bits for AR_PHY_POWER_TX_RATE_MAX. */
+#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE	0x00000040
+
+/* Bits for AR_PHY_FRAME_CTL. */
+#define AR_PHY_FRAME_CTL_TX_CLIP_M	0x00000038
+#define AR_PHY_FRAME_CTL_TX_CLIP_S	3
+
+/* Bits for AR_PHY_TXPWRADJ. */
+#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_M	0x00000fc0
+#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S	6
+#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_M	0x00fc0000
+#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S	18
+
+/* Bits for AR_PHY_RADAR_EXT. */
+#define AR_PHY_RADAR_EXT_ENA		0x00004000
+
+/* Bits for AR_PHY_RADAR_0. */
+#define AR_PHY_RADAR_0_ENA		0x00000001
+#define AR_PHY_RADAR_0_INBAND_M		0x0000003e
+#define AR_PHY_RADAR_0_INBAND_S		1
+#define AR_PHY_RADAR_0_PRSSI_M		0x00000fc0
+#define AR_PHY_RADAR_0_PRSSI_S		6
+#define AR_PHY_RADAR_0_HEIGHT_M		0x0003f000
+#define AR_PHY_RADAR_0_HEIGHT_S		12
+#define AR_PHY_RADAR_0_RRSSI_M		0x00fc0000
+#define AR_PHY_RADAR_0_RRSSI_S		18
+#define AR_PHY_RADAR_0_FIRPWR_M		0x7f000000
+#define AR_PHY_RADAR_0_FIRPWR_S		24
+#define AR_PHY_RADAR_0_FFT_ENA		0x80000000
+
+/* Bits for AR_PHY_RADAR_1. */
+#define AR_PHY_RADAR_1_MAXLEN_M		0x000000ff
+#define AR_PHY_RADAR_1_MAXLEN_S		0
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_M	0x00001f00
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_S	8
+#define AR_PHY_RADAR_1_RELSTEP_CHECK	0x00002000
+#define AR_PHY_RADAR_1_MAX_RRSSI	0x00004000
+#define AR_PHY_RADAR_1_BLOCK_CHECK	0x00008000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_M	0x003f0000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_S	16
+#define AR_PHY_RADAR_1_USE_FIR128	0x00400000
+#define AR_PHY_RADAR_1_RELPWR_ENA	0x00800000
+
+/* Bits for AR_PHY_SIGMA_DELTA. */
+#define AR_PHY_SIGMA_DELTA_ADC_SEL_M	0x00000003
+#define AR_PHY_SIGMA_DELTA_ADC_SEL_S	0
+#define AR_PHY_SIGMA_DELTA_FILT2_M	0x000000f8
+#define AR_PHY_SIGMA_DELTA_FILT2_S	3
+#define AR_PHY_SIGMA_DELTA_FILT1_M	0x00001f00
+#define AR_PHY_SIGMA_DELTA_FILT1_S	8
+#define AR_PHY_SIGMA_DELTA_ADC_CLIP_M	0x01ffe000
+#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S	13
+
+/* Bits for AR_PHY_RESTART. */
+#define AR_PHY_RESTART_DIV_GC_M	0x001c0000
+#define AR_PHY_RESTART_DIV_GC_S	18
+
+/* Bits for AR_PHY_RFBUS_REQ. */
+#define AR_PHY_RFBUS_REQ_EN	0x00000001
+
+/* Bits for AR_PHY_TIMING11. */
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M	0x000fffff
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S	0
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_M		0x3ff00000
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_S		20
+#define AR_PHY_TIMING11_USE_SPUR_IN_AGC		0x40000000
+#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR	0x80000000
+
+/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR(). */
+#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE		0x40000000
+#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE	0x80000000
+
+/* Bits for AR_PHY_EXT_CCA0. */
+#define AR_PHY_EXT_CCA0_THRESH62_M	0x000000ff
+#define AR_PHY_EXT_CCA0_THRESH62_S	0
+
+/* Bits for AR_PHY_EXT_CCA. */
+#define AR_PHY_EXT_MAXCCA_PWR_M		0x000001ff
+#define AR_PHY_EXT_MAXCCA_PWR_S		0
+#define AR_PHY_EXT_CCA_CYCPWR_THR1_M	0x0000fe00
+#define AR_PHY_EXT_CCA_CYCPWR_THR1_S	9
+#define AR_PHY_EXT_CCA_THRESH62_M	0x007f0000
+#define AR_PHY_EXT_CCA_THRESH62_S	16
+#define AR_PHY_EXT_MINCCA_PWR_M		0xff800000
+#define AR_PHY_EXT_MINCCA_PWR_S		23
+#define AR9280_PHY_EXT_MINCCA_PWR_M	0x01ff0000
+#define AR9280_PHY_EXT_MINCCA_PWR_S	16
+
+/* Bits for AR_PHY_SFCORR_EXT. */
+#define AR_PHY_SFCORR_EXT_M1_THRESH_M		0x0000007f
+#define AR_PHY_SFCORR_EXT_M1_THRESH_S		0
+#define AR_PHY_SFCORR_EXT_M2_THRESH_M		0x00003f80
+#define AR_PHY_SFCORR_EXT_M2_THRESH_S		7
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M	0x001fc000
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S	14
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M	0x0fe00000
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S	21
+#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_M		0xf0000000
+#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S		28
+
+/* Bits for AR_PHY_HALFGI. */
+#define AR_PHY_HALFGI_DSC_EXP_M	0x0000000f
+#define AR_PHY_HALFGI_DSC_EXP_S	0
+#define AR_PHY_HALFGI_DSC_MAN_M	0x0007fff0
+#define AR_PHY_HALFGI_DSC_MAN_S	4
+
+/* Bits for AR_PHY_CHAN_INFO_MEMORY. */
+#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK	0x00000001
+
+/* Bits for AR_PHY_HEAVY_CLIP_FACTOR_RIFS. */
+#define AR_PHY_RIFS_INIT_DELAY_M	0x03ff0000
+#define AR_PHY_RIFS_INIT_DELAY_S	16
+
+/* Bits for AR_PHY_CALMODE. */
+#define AR_PHY_CALMODE_IQ		0x00000000
+#define AR_PHY_CALMODE_ADC_GAIN		0x00000001
+#define AR_PHY_CALMODE_ADC_DC_PER	0x00000002
+#define AR_PHY_CALMODE_ADC_DC_INIT	0x00000003
+
+/* Bits for AR_PHY_RFBUS_GRANT. */
+#define AR_PHY_RFBUS_GRANT_EN	0x00000001
+
+/* Bits for AR_PHY_CHAN_INFO_GAIN_DIFF. */
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT	320
+
+/* Bits for AR_PHY_MODE. */
+#define AR_PHY_MODE_ASYNCFIFO		0x00000080
+#define AR_PHY_MODE_AR2133		0x00000008
+#define AR_PHY_MODE_AR5111		0x00000000
+#define AR_PHY_MODE_AR5112		0x00000008
+#define AR_PHY_MODE_DYNAMIC		0x00000004
+#define AR_PHY_MODE_RF2GHZ		0x00000002
+#define AR_PHY_MODE_RF5GHZ		0x00000000
+#define AR_PHY_MODE_CCK			0x00000001
+#define AR_PHY_MODE_OFDM		0x00000000
+#define AR_PHY_MODE_DYN_CCK_DISABLE	0x00000100
+
+/* Bits for AR_PHY_CCK_TX_CTRL. */
+#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_M	0x0000000c
+#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S	2
+#define AR_PHY_CCK_TX_CTRL_JAPAN		0x00000010
+
+/* Bits for AR_PHY_CCK_DETECT. */
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M		0x0000003f
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S		0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M		0x00001fc0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S		6
+#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x00002000
+
+/* Bits for AR_PHY_GAIN_2GHZ. */
+#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_M		0x0000003f
+#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S		0
+#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_M		0x0000001f
+#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S		0
+#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_M		0x00000fc0
+#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S		6
+#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_M		0x00003c00
+#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S		10
+#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_M	0x0001f000
+#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S	12
+#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_M	0x003e0000
+#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S	17
+#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_M		0x00fc0000
+#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S		18
+
+/* Bit for AR_PHY_CCK_RXCTRL4. */
+#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_M	0x01f80000
+#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S	19
+
+/* Bits for AR_PHY_DAG_CTRLCCK. */
+#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR	0x00000200
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M	0x0001fc00
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S	10
+
+/* Bits for AR_PHY_FORCE_CLKEN_CCK. */
+#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX	0x00000040
+
+/* Bits for AR_PHY_TPCRG1. */
+#define AR_PHY_TPCRG1_NUM_PD_GAIN_M	0x0000c000
+#define AR_PHY_TPCRG1_NUM_PD_GAIN_S	14
+#define AR_PHY_TPCRG1_PD_GAIN_1_M	0x00030000
+#define AR_PHY_TPCRG1_PD_GAIN_1_S	16
+#define AR_PHY_TPCRG1_PD_GAIN_2_M	0x000c0000
+#define AR_PHY_TPCRG1_PD_GAIN_2_S	18
+#define AR_PHY_TPCRG1_PD_GAIN_3_M	0x00300000
+#define AR_PHY_TPCRG1_PD_GAIN_3_S	20
+#define AR_PHY_TPCRG1_PD_CAL_ENABLE	0x00400000
+
+/* Bits for AR_PHY_TX_PWRCTRL4. */
+#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID	0x00000001
+#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_M	0x000001fe
+#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S	1
+
+/* Bits for AR_PHY_TX_PWRCTRL6_[01]. */
+#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_M	0x03000000
+#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S	24
+
+/* Bits for AR_PHY_TX_PWRCTRL7. */
+#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_M	0x0007e000
+#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S	13
+#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_M	0x01f80000
+#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S	19
+
+/* Bits for AR_PHY_TX_PWRCTRL9. */
+#define AR_PHY_TX_DESIRED_SCALE_CCK_M		0x00007c00
+#define AR_PHY_TX_DESIRED_SCALE_CCK_S		10	/* XXX should be 9? */
+#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL	0x80000000
+
+/* Bits for AR_PHY_TX_GAIN_TBL. */
+#define AR_PHY_TX_GAIN_CLC_M	0x0000001e
+#define AR_PHY_TX_GAIN_CLC_S	1
+#define AR_PHY_TX_GAIN_M	0x0007f000
+#define AR_PHY_TX_GAIN_S	12
+
+/* Bits for AR_PHY_SPUR_REG. */
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M	0x0000007f
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S	0
+#define AR_SPUR_RSSI_THRESH			40
+#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI	0x00000100
+#define AR_PHY_SPUR_REG_MASK_RATE_SELECT	0x0001fe00
+#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM		0x00020000
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL		0x03fc0000
+
+/* Bits for AR_PHY_ANALOG_SWAP. */
+#define AR_PHY_SWAP_ALT_CHAIN	0x00000040
+
+/* Bits for AR_PHY_TPCRG5. */
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_M		0x0000000f
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S		0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_M	0x000003f0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S	4
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_M	0x0000fc00
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S	10
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_M	0x003f0000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S	16
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_M	0x0fc00000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S	22
+
+/* Bits for AR_PHY_CL_CAL_CTL. */
+#define AR_PHY_PARALLEL_CAL_ENABLE	0x00000001
+#define AR_PHY_CL_CAL_ENABLE		0x00000002
+
+/* Bits for AR_PHY_CLC_TBL. */
+#define AR_PHY_CLC_Q0_M		0x0000ffd0
+#define AR_PHY_CLC_Q0_S		5
+#define AR_PHY_CLC_I0_M		0x07ff0000
+#define AR_PHY_CLC_I0_S		16
+
+/* Bits for AR_PHY_XPA_CFG. */
+#define AR_PHY_FORCE_XPA_CFG	0x000000001
+
+/* Bits for AR_PHY_CH[01]_TX_PWRCTRL11. */
+#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_M	0x0000fc00
+#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S	10
+#define AR_PHY_TX_PWRCTRL_OLPC_PWR_M		0x00ff0000
+#define AR_PHY_TX_PWRCTRL_OLPC_PWR_S		16
+
+/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR. */
+#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_M	0x0000003f
+#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_S	0
+#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_M	0x00000fc0
+#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_S	6
+#define AR_PHY_NEW_ADC_DC_GAIN_QDC_M	0x001ff000
+#define AR_PHY_NEW_ADC_DC_GAIN_QDC_S	12
+#define AR_PHY_NEW_ADC_DC_GAIN_IDC_M	0x3fe00000
+#define AR_PHY_NEW_ADC_DC_GAIN_IDC_S	21
+
+/* Bits for AR_PHY(0x37). */
+#define AR5416_BMODE_SYNTH	0x00000002
+#define AR5416_AMODE_REFSEL_M	0x0000000c
+#define AR5416_AMODE_REFSEL_S	2
+
+
+#define AR5008_MAX_SCATTER	16	/* NB: not a hardware limit. */
+
+/*
+ * Tx DMA descriptor.
+ */
+struct ar_tx_desc {
+	uint32_t	ds_link;
+	uint32_t	ds_data;
+	uint32_t	ds_ctl0;
+	uint32_t	ds_ctl1;
+	uint32_t	ds_ctl2;
+	uint32_t	ds_ctl3;
+	uint32_t	ds_ctl4;
+	uint32_t	ds_ctl5;
+	uint32_t	ds_ctl6;
+	uint32_t	ds_ctl7;
+	uint32_t	ds_ctl8;
+	uint32_t	ds_ctl9;
+	uint32_t	ds_ctl10;
+	uint32_t	ds_ctl11;
+	uint32_t	ds_status0;
+	uint32_t	ds_status1;
+	uint32_t	ds_tstamp;
+	uint32_t	ds_ba_bitmap_lo;
+	uint32_t	ds_ba_bitmap_hi;
+	uint32_t	ds_evm0;
+	uint32_t	ds_evm1;
+	uint32_t	ds_evm2;
+	uint32_t	ds_status8;
+	uint32_t	ds_status9;
+	/*
+	 * Padding to make Tx descriptors 128 bytes such that they will
+	 * not cross a 4KB boundary.
+	 */
+	uint32_t	pad[8];
+} __packed;
+
+/* Bits for ds_ctl0. */
+#define AR_TXC0_FRAME_LEN_M		0x00000fff
+#define AR_TXC0_FRAME_LEN_S		0
+#define AR_TXC0_VIRT_MORE_FRAG		0x00001000
+#define AR_TXC0_XMIT_POWER_M		0x003f0000
+#define AR_TXC0_XMIT_POWER_S		16
+#define AR_TXC0_RTS_ENABLE		0x00400000
+#define AR_TXC0_VEOL			0x00800000
+#define AR_TXC0_CLR_DEST_MASK		0x01000000
+#define AR_TXC0_INTR_REQ		0x20000000
+#define AR_TXC0_DEST_IDX_VALID		0x40000000
+#define AR_TXC0_CTS_ENABLE		0x80000000
+
+/* Bits for ds_ctl1. */
+#define AR_TXC1_BUF_LEN_M		0x00000fff
+#define AR_TXC1_BUF_LEN_S		0
+#define AR_TXC1_MORE			0x00001000
+#define AR_TXC1_DEST_IDX_M		0x000fe000
+#define AR_TXC1_DEST_IDX_S		13
+#define AR_TXC1_FRAME_TYPE_M		0x00f00000
+#define AR_TXC1_FRAME_TYPE_S		20
+#define AR_FRAME_TYPE_NORMAL		0
+#define AR_FRAME_TYPE_ATIM		1
+#define AR_FRAME_TYPE_PSPOLL		2
+#define AR_FRAME_TYPE_BEACON		3
+#define AR_FRAME_TYPE_PROBE_RESP	4
+#define AR_TXC1_NO_ACK			0x01000000
+#define AR_TXC1_INSERT_TS		0x02000000
+#define AR_TXC1_EXT_ONLY		0x08000000
+#define AR_TXC1_EXT_AND_CTL		0x10000000
+#define AR_TXC1_MORE_AGGR		0x20000000
+#define AR_TXC1_IS_AGGR			0x40000000
+
+/* Bits for ds_ctl2. */
+#define AR_TXC2_BURST_DUR_M		0x00007fff
+#define AR_TXC2_BURST_DUR_S		0
+#define AR_TXC2_DUR_UPDATE_ENA		0x00008000
+#define AR_TXC2_XMIT_DATA_TRIES0_M	0x000f0000
+#define AR_TXC2_XMIT_DATA_TRIES0_S	16
+#define AR_TXC2_XMIT_DATA_TRIES1_M	0x00f00000
+#define AR_TXC2_XMIT_DATA_TRIES1_S	20
+#define AR_TXC2_XMIT_DATA_TRIES2_M	0x0f000000
+#define AR_TXC2_XMIT_DATA_TRIES2_S	24
+#define AR_TXC2_XMIT_DATA_TRIES3_M	0xf0000000
+#define AR_TXC2_XMIT_DATA_TRIES3_S	28
+
+/* Bits for ds_ctl3. */
+#define AR_TXC3_XMIT_RATE0_M		0x000000ff
+#define AR_TXC3_XMIT_RATE0_S		0
+#define AR_TXC3_XMIT_RATE1_M		0x0000ff00
+#define AR_TXC3_XMIT_RATE1_S		8
+#define AR_TXC3_XMIT_RATE2_M		0x00ff0000
+#define AR_TXC3_XMIT_RATE2_S		16
+#define AR_TXC3_XMIT_RATE3_M		0xff000000
+#define AR_TXC3_XMIT_RATE3_S		24
+
+/* Bits for ds_ctl4. */
+#define AR_TXC4_PACKET_DUR0_M		0x00007fff
+#define AR_TXC4_PACKET_DUR0_S		0
+#define AR_TXC4_RTSCTS_QUAL0		0x00008000
+#define AR_TXC4_PACKET_DUR1_M		0x7fff0000
+#define AR_TXC4_PACKET_DUR1_S		16
+#define AR_TXC4_RTSCTS_QUAL1		0x80000000
+/* Shortcut. */
+#define AR_TXC4_RTSCTS_QUAL01	\
+	(AR_TXC4_RTSCTS_QUAL0 | AR_TXC4_RTSCTS_QUAL1)
+
+/* Bits for ds_ctl5. */
+#define AR_TXC5_PACKET_DUR2_M		0x00007fff
+#define AR_TXC5_PACKET_DUR2_S		0
+#define AR_TXC5_RTSCTS_QUAL2		0x00008000
+#define AR_TXC5_PACKET_DUR3_M		0x7fff0000
+#define AR_TXC5_PACKET_DUR3_S		16
+#define AR_TXC5_RTSCTS_QUAL3		0x80000000
+/* Shortcut. */
+#define AR_TXC5_RTSCTS_QUAL23	\
+	(AR_TXC5_RTSCTS_QUAL2 | AR_TXC5_RTSCTS_QUAL3)
+
+/* Bits for ds_ctl6. */
+#define AR_TXC6_AGGR_LEN_M		0x0000ffff
+#define AR_TXC6_AGGR_LEN_S		0
+#define AR_TXC6_PAD_DELIM_M		0x03fc0000
+#define AR_TXC6_PAD_DELIM_S		18
+#define AR_TXC6_ENCR_TYPE_M		0x0c000000
+#define AR_TXC6_ENCR_TYPE_S		26
+#define AR_ENCR_TYPE_CLEAR		0
+#define AR_ENCR_TYPE_WEP		1
+#define AR_ENCR_TYPE_AES		2
+#define AR_ENCR_TYPE_TKIP		3
+
+/* Bits for ds_ctl7. */
+#define AR_TXC7_2040_0			0x00000001
+#define AR_TXC7_GI0			0x00000002
+#define AR_TXC7_CHAIN_SEL0_M		0x0000001c
+#define AR_TXC7_CHAIN_SEL0_S		2
+#define AR_TXC7_2040_1			0x00000020
+#define AR_TXC7_GI1			0x00000040
+#define AR_TXC7_CHAIN_SEL1_M		0x00000380
+#define AR_TXC7_CHAIN_SEL1_S		7
+#define AR_TXC7_2040_2			0x00000400
+#define AR_TXC7_GI2			0x00000800
+#define AR_TXC7_CHAIN_SEL2_M		0x00007000
+#define AR_TXC7_CHAIN_SEL2_S		12
+#define AR_TXC7_2040_3			0x00008000
+#define AR_TXC7_GI3			0x00010000
+#define AR_TXC7_CHAIN_SEL3_M		0x000e0000
+#define AR_TXC7_CHAIN_SEL3_S		17
+#define AR_TXC7_RTSCTS_RATE_M		0x0ff00000
+#define AR_TXC7_RTSCTS_RATE_S		20
+/* Shortcuts. */
+#define AR_TXC7_2040_0123	\
+	(AR_TXC7_2040_0 | AR_TXC7_2040_1 | AR_TXC7_2040_2 | AR_TXC7_2040_3)
+#define AR_TXC7_GI0123		\
+	(AR_TXC7_GI0 | AR_TXC7_GI1 | AR_TXC7_GI2 | AR_TXC7_GI3)
+
+/* Bits for ds_status0. */
+#define AR_TXS0_RSSI_ANT0(i)		(((x) >> ((i) * 8)) & 0xff)
+#define AR_TXS0_BA_STATUS		0x40000000
+
+/* Bits for ds_status1. */
+#define AR_TXS1_FRM_XMIT_OK		0x00000001
+#define AR_TXS1_EXCESSIVE_RETRIES	0x00000002
+#define AR_TXS1_FIFO_UNDERRUN		0x00000004
+#define AR_TXS1_FILTERED		0x00000008
+#define AR_TXS1_RTS_FAIL_CNT_M		0x000000f0
+#define AR_TXS1_RTS_FAIL_CNT_S		4
+#define AR_TXS1_DATA_FAIL_CNT_M		0x00000f00
+#define AR_TXS1_DATA_FAIL_CNT_S		8
+#define AR_TXS1_VIRT_RETRY_CNT_M	0x0000f000
+#define AR_TXS1_VIRT_RETRY_CNT_S	12
+#define AR_TXS1_TX_DELIM_UNDERRUN	0x00010000
+#define AR_TXS1_TX_DATA_UNDERRUN	0x00020000
+#define AR_TXS1_DESC_CFG_ERR		0x00040000
+#define AR_TXS1_TX_TIMER_EXPIRED	0x00080000
+/* Shortcut. */
+#define AR_TXS1_UNDERRUN		\
+	(AR_TXS1_FIFO_UNDERRUN |	\
+	 AR_TXS1_TX_DELIM_UNDERRUN |	\
+	 AR_TXS1_TX_DATA_UNDERRUN)
+
+/* Bits for ds_status9. */
+#define AR_TXS9_DONE			0x00000001
+#define AR_TXS9_SEQNUM_M		0x00001ffe
+#define AR_TXS9_SEQNUM_S		1
+#define AR_TXS9_TXOP_EXCEEDED		0x00020000
+#define AR_TXS9_FINAL_IDX_M		0x00600000
+#define AR_TXS9_FINAL_IDX_S		21
+#define AR_TXS9_POWER_MGMT		0x02000000
+
+/*
+ * Rx DMA descriptor.
+ */
+struct ar_rx_desc {
+	uint32_t	ds_link;
+	uint32_t	ds_data;
+	uint32_t	ds_ctl0;
+	uint32_t	ds_ctl1;
+	uint32_t	ds_status0;
+	uint32_t	ds_status1;
+	uint32_t	ds_status2;
+	uint32_t	ds_status3;
+	uint32_t	ds_status4;
+	uint32_t	ds_status5;
+	uint32_t	ds_status6;
+	uint32_t	ds_status7;
+	uint32_t	ds_status8;
+	/*
+	 * Padding to make Rx descriptors 64 bytes such that they will
+	 * not cross a 4KB boundary.
+	 */
+	uint32_t	pad[3];
+} __packed;
+
+/* Bits for ds_ctl1. */
+#define AR_RXC1_BUF_LEN_M		0x00000fff
+#define AR_RXC1_BUF_LEN_S		0
+#define AR_RXC1_INTR_REQ		0x00002000
+
+/* Bits for ds_ctl2. */
+#define AR_RXS0_RSSI_ANT00(x)		(((x) >>  0) & 0xff)
+#define AR_RXS0_RSSI_ANT01(x)		(((x) >>  8) & 0xff)
+#define AR_RXS0_RSSI_ANT02(x)		(((x) >> 16) & 0xff)
+#define AR_RXS0_RATE_M			0xff000000
+#define AR_RXS0_RATE_S			24
+
+/* Bits for ds_status1. */
+#define AR_RXS1_DATA_LEN_M		0x00000fff
+#define AR_RXS1_DATA_LEN_S		0
+#define AR_RXS1_MORE			0x00001000
+
+/* Bits for ds_status3. */
+#define AR_RXS3_GI			0x00000001
+#define AR_RXS3_2040			0x00000002
+#define AR_RXS3_PARALLEL_40		0x00000004
+#define AR_RXS3_ANTENNA_M		0xffffff00
+#define AR_RXS3_ANTENNA_S		8
+#define AR_RXS3_RATE_M			0x000003fc
+#define AR_RXS3_RATE_S			2
+
+/* Bits for ds_status4. */
+#define AR_RXS4_RSSI_COMBINED_M		0xff000000
+#define AR_RXS4_RSSI_COMBINED_S		24
+
+/* Bits for ds_status8. */
+#define AR_RXS8_DONE			0x00000001
+#define AR_RXS8_FRAME_OK		0x00000002
+#define AR_RXS8_CRC_ERR			0x00000004
+#define AR_RXS8_DECRYPT_CRC_ERR		0x00000008
+#define AR_RXS8_PHY_ERR			0x00000010
+#define AR_RXS8_MICHAEL_ERR		0x00000020
+#define AR_RXS8_PRE_DELIM_CRC_ERR	0x00000040
+#define AR_RXS8_PHY_ERR_CODE_M		0x0000ff00
+#define AR_RXS8_PHY_ERR_CODE_S		8
+#define AR_RXS8_KEY_IDX_VALID		0x00000100
+#define AR_RXS8_KEY_IDX_M		0x0000fe00
+#define AR_RXS8_KEY_IDX_S		9
+#define AR_RXS8_POST_DELIM_CRC_ERR	0x00040000
+#define AR_RXS8_DECRYPT_BUSY_ERR	0x40000000
+
+#define AR_MAX_PWR_RANGE_IN_HALF_DB	64
+#define AR9285_PD_GAIN_BOUNDARY_DEFAULT	58
+
+/*
+ * AR5008 family common ROM header.
+ */
+#define AR_EEPROM_MAGIC_OFFSET	0x0000
+#if BYTE_ORDER == BIG_ENDIAN
+#define AR_EEPROM_MAGIC		0x5aa5
+#else
+#define AR_EEPROM_MAGIC		0xa55a
+#endif
+
+#define AR_NO_SPUR		0x8000
+#define AR_NUM_PDADC_VALUES	128
+
+struct ar_base_eep_header {
+	uint16_t	length;
+	uint16_t	checksum;
+	uint16_t	version;
+#define AR_EEP_VER			0xe
+#define AR_EEP_VER_MINOR_MASK		0x0fff
+#define AR_EEP_MINOR_VER_2		2
+#define AR_EEP_MINOR_VER_3		3
+#define AR_EEP_MINOR_VER_7		7
+#define AR_EEP_MINOR_VER_9		9
+#define AR_EEP_MINOR_VER_10		10
+#define AR_EEP_MINOR_VER_16		16
+#define AR_EEP_MINOR_VER_17		17
+#define AR_EEP_MINOR_VER_19		19
+#define AR_EEP_MINOR_VER_20		20
+#define AR_EEP_MINOR_VER_21		21
+#define AR_EEP_MINOR_VER_22		22
+
+	uint8_t		opCapFlags;
+#define AR_OPFLAGS_11A			0x01
+#define AR_OPFLAGS_11G			0x02
+#define AR_OPFLAGS_11N_5G40		0x04
+#define AR_OPFLAGS_11N_2G40		0x08
+#define AR_OPFLAGS_11N_5G20		0x10
+#define AR_OPFLAGS_11N_2G20		0x20
+/* Shortcut. */
+#define AR_OPFLAGS_11N			0x3c
+
+	uint8_t		eepMisc;
+	uint16_t	regDmn[2];
+	uint8_t		macAddr[6];
+	uint8_t		rxMask;
+	uint8_t		txMask;
+	uint16_t	rfSilent;
+#define AR_EEP_RFSILENT_ENABLED		0x0001
+#define AR_EEP_RFSILENT_GPIO_SEL_M	0x001c
+#define AR_EEP_RFSILENT_GPIO_SEL_S	2
+#define AR_EEP_RFSILENT_POLARITY	0x0002
+
+	uint16_t	blueToothOptions;
+	uint16_t	deviceCap;
+#define AR_EEP_DEVCAP_COMPRESS_DIS	0x0001
+#define AR_EEP_DEVCAP_AES_DIS		0x0002
+#define AR_EEP_DEVCAP_FASTFRAME_DIS	0x0004
+#define AR_EEP_DEVCAP_BURST_DIS		0x0008
+#define AR_EEP_DEVCAP_MAXQCU_M		0x01f0
+#define AR_EEP_DEVCAP_MAXQCU_S		4
+#define AR_EEP_DEVCAP_HEAVY_CLIP_EN	0x0200
+#define AR_EEP_DEVCAP_KC_ENTRIES_M	0xf000
+#define AR_EEP_DEVCAP_KC_ENTRIES_S	12
+
+	uint32_t	binBuildNumber;
+	uint8_t		deviceType;
+} __packed;
+
+#define AR_EEP_TXGAIN_ORIGINAL		0
+#define AR_EEP_TXGAIN_HIGH_POWER	1
+
+#define AR_EEPROM_MODAL_SPURS		5
+
+struct ar_spur_chan {
+	uint16_t	spurChan;
+	uint8_t		spurRangeLow;
+	uint8_t		spurRangeHigh;
+} __packed;
+
+struct ar_cal_data_per_freq_olpc {
+	uint8_t	pwrPdg[2][5];
+	uint8_t	vpdPdg[2][5];
+	uint8_t	pcdac[2][5];
+	uint8_t	empty[2][5];
+} __packed;
+
+struct ar_cal_target_power_leg {
+	uint8_t	bChannel;
+	uint8_t	tPow2x[4];
+} __packed;
+
+struct ar_cal_target_power_ht {
+	uint8_t	bChannel;
+	uint8_t	tPow2x[8];
+} __packed;
+
+struct ar_cal_ctl_edges {
+	uint8_t	bChannel;
+	uint8_t	tPowerFlag;
+#define AR_CAL_CTL_EDGES_POWER_M	0x3f
+#define AR_CAL_CTL_EDGES_POWER_S	0
+#define AR_CAL_CTL_EDGES_FLAG_M		0xc0
+#define AR_CAL_CTL_EDGES_FLAG_S		6
+} __packed;
diff --git a/sys/dev/ic/ar5416.c b/sys/dev/ic/ar5416.c
index 12f88985598..64bf3606889 100644
--- a/sys/dev/ic/ar5416.c
+++ b/sys/dev/ic/ar5416.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5416.c,v 1.7 2010/04/20 22:05:41 tedu Exp $	*/
+/*	$OpenBSD: ar5416.c,v 1.8 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -62,20 +62,26 @@
 #include <dev/ic/athnreg.h>
 #include <dev/ic/athnvar.h>
 
+#include <dev/ic/ar5008reg.h>
 #include <dev/ic/ar5416reg.h>
 
 int	ar5416_attach(struct athn_softc *);
 void	ar5416_setup(struct athn_softc *);
+void	ar5416_swap_rom(struct athn_softc *);
+const struct ar_spur_chan *
+	ar5416_get_spur_chans(struct athn_softc *, int);
 int	ar5416_set_synth(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
+uint8_t	ar5416_reverse_bits(uint8_t, int);
+uint8_t	ar5416_get_rf_rev(struct athn_softc *);
 void	ar5416_init_from_rom(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
 int	ar5416_init_calib(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
-void	ar5416_get_pdadcs(struct athn_softc *, struct ieee80211_channel *,
-	    int, int, uint8_t, uint8_t *, uint8_t *);
 void	ar5416_set_power_calib(struct athn_softc *,
 	    struct ieee80211_channel *);
+void	ar5416_set_txpower(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
 void	ar5416_spur_mitigate(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
 void	ar5416_rw_rfbits(uint32_t *, int, int, uint32_t, int);
@@ -87,12 +93,30 @@ void	ar5416_force_bias(struct athn_softc *, struct ieee80211_channel *);
 void	ar9160_rw_addac(struct athn_softc *, struct ieee80211_channel *,
 	    uint32_t *);
 void	ar5416_reset_addac(struct athn_softc *, struct ieee80211_channel *);
+void	ar5416_get_pdadcs(struct athn_softc *, struct ieee80211_channel *,
+	    int, int, uint8_t, uint8_t *, uint8_t *);
+
+/* Extern functions. */
+uint8_t	athn_chan2fbin(struct ieee80211_channel *);
+void	athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
+int	ar5008_attach(struct athn_softc *);
+void	ar5008_write_txpower(struct athn_softc *, int16_t power[]);
+void	ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *,
+	    struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *);
+void	ar5008_set_viterbi_mask(struct athn_softc *, int);
+void	ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]);
+void	ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]);
+void	ar9280_2_0_olpc_get_pdadcs(struct athn_softc *,
+	    struct ieee80211_channel *, int, uint8_t *, uint8_t *, uint8_t *);
+
 
 int
 ar5416_attach(struct athn_softc *sc)
 {
 	sc->eep_base = AR5416_EEP_START_LOC;
-	sc->eep_size = sizeof (struct ar5416_eeprom);
+	sc->eep_size = sizeof(struct ar5416_eeprom);
 	sc->def_nf = AR5416_PHY_CCA_MAX_GOOD_VALUE;
 	sc->ngpiopins = 14;
 	sc->led_pin = 1;
@@ -110,7 +134,8 @@ ar5416_attach(struct athn_softc *sc)
 	else
 		sc->ini = &ar5416_ini;
 	sc->serdes = ar5416_serdes;
-	return (0);
+
+	return (ar5008_attach(sc));
 }
 
 void
@@ -154,7 +179,7 @@ ar5416_get_spur_chans(struct athn_softc *sc, int is2ghz)
 {
 	const struct ar5416_eeprom *eep = sc->eep;
 
-	return eep->modalHeader[is2ghz].spurChans;
+	return (eep->modalHeader[is2ghz].spurChans);
 }
 
 int
@@ -204,7 +229,7 @@ ar5416_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
 		} else
 			return (EINVAL);
 	}
-	chansel = athn_reverse_bits(chansel, 8);
+	chansel = ar5416_reverse_bits(chansel, 8);
 	phy |= chansel << 8 | 1 << 5 | 1;
 	DPRINTFN(4, ("AR_PHY(0x37)=0x%08x\n", phy));
 	AR_WRITE(sc, AR_PHY(0x37), phy);
@@ -376,7 +401,7 @@ ar5416_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
 		hipier.pwr[i] = pierdata[lo].pwrPdg[i];
 		hipier.vpd[i] = pierdata[lo].vpdPdg[i];
 	}
-	athn_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
+	ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
 	    AR5416_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
 
 	if (!AR_SREV_9280_20_OR_LATER(sc))
@@ -432,7 +457,7 @@ ar5416_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
 	}
 
 	nxpdgains = 0;
-	memset(xpdgains, 0, sizeof xpdgains);
+	memset(xpdgains, 0, sizeof(xpdgains));
 	for (i = AR5416_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
 		if (nxpdgains >= AR5416_NUM_PD_GAINS)
 			break;	/* Can't happen. */
@@ -515,7 +540,7 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	uint8_t ht40inc;
 #endif
 	int16_t pwr = 0, pwroff, max_ant_gain, power[ATHN_POWER_COUNT];
-	int8_t cckinc;
+	uint8_t cckinc;
 	int i;
 
 	ar5416_set_power_calib(sc, c);
@@ -540,55 +565,55 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 
 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
 		/* Get CCK target powers. */
-		athn_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
+		ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
 		    AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
 
 		/* Get OFDM target powers. */
-		athn_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
+		ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
 		    AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
 
 #ifndef IEEE80211_NO_HT
 		/* Get HT-20 target powers. */
-		athn_get_ht_tpow(sc, c, AR_CTL_2GHT20,
+		ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20,
 		    eep->calTargetPower2GHT20, AR5416_NUM_2G_20_TARGET_POWERS,
 		    tpow_ht20);
 
 		if (extc != NULL) {
 			/* Get HT-40 target powers. */
-			athn_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+			ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
 			    eep->calTargetPower2GHT40,
 			    AR5416_NUM_2G_40_TARGET_POWERS, tpow_ht40);
 
 			/* Get secondary channel CCK target powers. */
-			athn_get_lg_tpow(sc, extc, AR_CTL_11B,
+			ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
 			    eep->calTargetPowerCck,
 			    AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck_ext);
 
 			/* Get secondary channel OFDM target powers. */
-			athn_get_lg_tpow(sc, extc, AR_CTL_11G,
+			ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
 			    eep->calTargetPower2G,
 			    AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm_ext);
 		}
 #endif
 	} else {
 		/* Get OFDM target powers. */
-		athn_get_lg_tpow(sc, c, AR_CTL_11A, eep->calTargetPower5G,
+		ar5008_get_lg_tpow(sc, c, AR_CTL_11A, eep->calTargetPower5G,
 		    AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm);
 
 #ifndef IEEE80211_NO_HT
 		/* Get HT-20 target powers. */
-		athn_get_ht_tpow(sc, c, AR_CTL_5GHT20,
+		ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT20,
 		    eep->calTargetPower5GHT20, AR5416_NUM_5G_20_TARGET_POWERS,
 		    tpow_ht20);
 
 		if (extc != NULL) {
 			/* Get HT-40 target powers. */
-			athn_get_ht_tpow(sc, c, AR_CTL_5GHT40,
+			ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT40,
 			    eep->calTargetPower5GHT40,
 			    AR5416_NUM_5G_40_TARGET_POWERS, tpow_ht40);
 
 			/* Get secondary channel OFDM target powers. */
-			athn_get_lg_tpow(sc, extc, AR_CTL_11A,
+			ar5008_get_lg_tpow(sc, extc, AR_CTL_11A,
 			    eep->calTargetPower5G,
 			    AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm_ext);
 		}
@@ -598,7 +623,7 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	/* Compute CCK/OFDM delta. */
 	cckinc = (sc->flags & ATHN_FLAG_OLPC) ? -2 : 0;
 
-	memset(power, 0, sizeof power);
+	memset(power, 0, sizeof(power));
 	/* Shuffle target powers accross transmit rates. */
 	power[ATHN_POWER_OFDM6 ] =
 	power[ATHN_POWER_OFDM9 ] =
@@ -651,7 +676,7 @@ ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 
 	/* Write transmit power values to hardware. */
-	athn_write_txpower(sc, power);
+	ar5008_write_txpower(sc, power);
 
 	/*
 	 * Write transmit power substraction for dynamic chain changing
@@ -708,7 +733,38 @@ ar5416_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 	    SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
 
 	bin = spur * 32;
-	athn_set_viterbi_mask(sc, bin);
+	ar5008_set_viterbi_mask(sc, bin);
+}
+
+uint8_t
+ar5416_reverse_bits(uint8_t v, int nbits)
+{
+	KASSERT(nbits <= 8);
+	v = ((v >> 1) & 0x55) | ((v & 0x55) << 1);
+	v = ((v >> 2) & 0x33) | ((v & 0x33) << 2);
+	v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4);
+	return (v >> (8 - nbits));
+}
+
+uint8_t
+ar5416_get_rf_rev(struct athn_softc *sc)
+{
+	uint8_t rev, reg;
+	int i;
+
+	/* Allow access to analog chips. */
+	AR_WRITE(sc, AR_PHY(0), 0x00000007);
+
+	AR_WRITE(sc, AR_PHY(0x36), 0x00007058);
+	for (i = 0; i < 8; i++)
+		AR_WRITE(sc, AR_PHY(0x20), 0x00010000);
+	reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff;
+	reg = (reg & 0xf0) >> 4 | (reg & 0x0f) << 4;
+
+	rev = ar5416_reverse_bits(reg, 8);
+	if ((rev & AR_RADIO_SREV_MAJOR) == 0)
+		rev = AR_RAD5133_SREV_MAJOR;
+	return (rev);
 }
 
 /*
@@ -744,13 +800,13 @@ ar5416_rw_bank6tpc(struct athn_softc *sc, struct ieee80211_channel *c,
 
 	if (IEEE80211_IS_CHAN_5GHZ(c)) {
 		modal = &eep->modalHeader[0];
-		/* 5GHz db in column 0, bits [200-202] */
+		/* 5GHz db in column 0, bits [200-202]. */
 		ar5416_rw_rfbits(rwbank6tpc, 0, 200, modal->db, 3);
 		/* 5GHz ob in column 0, bits [203-205]. */
 		ar5416_rw_rfbits(rwbank6tpc, 0, 203, modal->ob, 3);
 	} else {
 		modal = &eep->modalHeader[1];
-		/* 2GHz db in column 0, bits [194-196] */
+		/* 2GHz db in column 0, bits [194-196]. */
 		ar5416_rw_rfbits(rwbank6tpc, 0, 194, modal->db, 3);
 		/* 2GHz ob in column 0, bits [197-199]. */
 		ar5416_rw_rfbits(rwbank6tpc, 0, 197, modal->ob, 3);
@@ -793,7 +849,7 @@ ar5416_rf_reset(struct athn_softc *sc, struct ieee80211_channel *c)
 		uint32_t *rwbank6tpc = sc->rwbuf;
 
 		/* Copy values from .rodata to writable buffer. */
-		memcpy(rwbank6tpc, bank6tpc, 32 * sizeof (uint32_t));
+		memcpy(rwbank6tpc, bank6tpc, 32 * sizeof(uint32_t));
 		ar5416_rw_bank6tpc(sc, c, rwbank6tpc);
 		bank6tpc = rwbank6tpc;
 	}
@@ -839,7 +895,7 @@ ar5416_force_bias(struct athn_softc *sc, struct ieee80211_channel *c)
 	KASSERT(IEEE80211_IS_CHAN_2GHZ(c));
 
 	/* Copy values from .rodata to writable buffer. */
-	memcpy(rwbank6, ar5416_bank6_vals, sizeof ar5416_bank6_vals);
+	memcpy(rwbank6, ar5416_bank6_vals, sizeof(ar5416_bank6_vals));
 
 	if (c->ic_freq < 2412)
 		bias = 0;
@@ -847,7 +903,7 @@ ar5416_force_bias(struct athn_softc *sc, struct ieee80211_channel *c)
 		bias = 1;
 	else
 		bias = 2;
-	athn_reverse_bits(bias, 3);
+	ar5416_reverse_bits(bias, 3);
 
 	/* Overwrite "rf_pwd_icsyndiv" (column 3, bits [181-183].) */
 	ar5416_rw_rfbits(rwbank6, 3, 181, bias, 3);
@@ -887,7 +943,7 @@ ar9160_rw_addac(struct athn_softc *sc, struct ieee80211_channel *c,
 	} else
 		bias = modal->xpaBiasLvl & 0x3;
 
-	bias = athn_reverse_bits(bias, 2);	/* Put in host bit-order. */
+	bias = ar5416_reverse_bits(bias, 2);	/* Put in host bit-order. */
 	DPRINTFN(4, ("bias level=%d\n", bias));
 	if (IEEE80211_IS_CHAN_2GHZ(c))
 		ar5416_rw_rfbits(addac, 0, 60, bias, 2);
@@ -906,7 +962,7 @@ ar5416_reset_addac(struct athn_softc *sc, struct ieee80211_channel *c)
 		uint32_t *rwaddac = sc->rwbuf;
 
 		/* Copy values from .rodata to writable buffer. */
-		memcpy(rwaddac, addac->vals, addac->nvals * sizeof (uint32_t));
+		memcpy(rwaddac, addac->vals, addac->nvals * sizeof(uint32_t));
 		ar9160_rw_addac(sc, c, rwaddac);
 		pvals = rwaddac;
 	} else
diff --git a/sys/dev/ic/ar5416reg.h b/sys/dev/ic/ar5416reg.h
index bc6cd868055..13d0b84567e 100644
--- a/sys/dev/ic/ar5416reg.h
+++ b/sys/dev/ic/ar5416reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5416reg.h,v 1.1 2009/11/14 16:55:11 damien Exp $	*/
+/*	$OpenBSD: ar5416reg.h,v 1.2 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -21,11 +21,6 @@
 
 #define AR5416_PHY_CCA_MAX_GOOD_VALUE	( -85)
 
-/* Bits for AR_PHY(0x37). */
-#define AR5416_BMODE_SYNTH	0x00000002
-#define AR5416_AMODE_REFSEL_M	0x0000000c
-#define AR5416_AMODE_REFSEL_S	2
-
 /*
  * ROM layout used by AR5416, AR9160 and AR9280.
  */
@@ -60,7 +55,8 @@ struct ar5416_base_eep_header {
 	uint8_t		deviceType;
 	/* End of common header. */
 	uint8_t		pwdclkind;
-	uint8_t		futureBase_1[2];
+	uint8_t		fastClk5g;
+	uint8_t		divChain;
 	uint8_t		rxGainType;
 #define AR5416_EEP_RXGAIN_23DB_BACKOFF	0
 #define AR5416_EEP_RXGAIN_13DB_BACKOFF	1
@@ -74,7 +70,7 @@ struct ar5416_base_eep_header {
 	uint8_t		desiredScaleCCK;
 	uint8_t		pwrTableOffset;
 	uint8_t		frac_n_5g;
-	uint8_t		futureBase_2[21];
+	uint8_t		futureBase[21];
 } __packed;
 
 struct ar5416_modal_eep_header {
diff --git a/sys/dev/ic/ar9003.c b/sys/dev/ic/ar9003.c
new file mode 100644
index 00000000000..cbeacc966d3
--- /dev/null
+++ b/sys/dev/ic/ar9003.c
@@ -0,0 +1,2407 @@
+/*	$OpenBSD: ar9003.c,v 1.1 2010/05/10 17:44:21 damien Exp $	*/
+
+/*-
+ * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR9003 family.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/timeout.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+#include <sys/stdint.h>	/* uintptr_t */
+
+#include <machine/bus.h>
+#include <machine/endian.h>
+#include <machine/intr.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/if_ether.h>
+#include <netinet/ip.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/ar9003reg.h>
+
+int	ar9003_attach(struct athn_softc *);
+int	ar9003_read_rom_word(struct athn_softc *, uint32_t, uint16_t *);
+int	ar9003_read_rom_data(struct athn_softc *, uint32_t, void *, int);
+int	ar9003_restore_rom_block(struct athn_softc *, uint8_t, uint8_t,
+	    const uint8_t *, int);
+int	ar9003_read_rom(struct athn_softc *);
+int	ar9003_gpio_read(struct athn_softc *, int);
+void	ar9003_gpio_write(struct athn_softc *, int, int);
+void	ar9003_gpio_config_input(struct athn_softc *, int);
+void	ar9003_gpio_config_output(struct athn_softc *, int, int);
+void	ar9003_rfsilent_init(struct athn_softc *);
+int	ar9003_dma_alloc(struct athn_softc *);
+void	ar9003_dma_free(struct athn_softc *);
+int	ar9003_tx_alloc(struct athn_softc *);
+void	ar9003_tx_free(struct athn_softc *);
+int	ar9003_rx_alloc(struct athn_softc *, int, int);
+void	ar9003_rx_free(struct athn_softc *, int);
+void	ar9003_reset_txsring(struct athn_softc *);
+void	ar9003_rx_enable(struct athn_softc *);
+void	ar9003_rx_radiotap(struct athn_softc *, struct mbuf *,
+	    struct ar_rx_status *);
+int	ar9003_rx_process(struct athn_softc *, int);
+void	ar9003_rx_intr(struct athn_softc *, int);
+int	ar9003_tx_process(struct athn_softc *);
+void	ar9003_tx_intr(struct athn_softc *);
+int	ar9003_intr(struct athn_softc *);
+int	ar9003_tx(struct athn_softc *, struct mbuf *, struct ieee80211_node *);
+void	ar9003_set_rf_mode(struct athn_softc *, struct ieee80211_channel *);
+int	ar9003_rf_bus_request(struct athn_softc *);
+void	ar9003_rf_bus_release(struct athn_softc *);
+void	ar9003_set_phy(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9003_set_delta_slope(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9003_enable_antenna_diversity(struct athn_softc *);
+void	ar9003_init_baseband(struct athn_softc *);
+void	ar9003_disable_phy(struct athn_softc *);
+void	ar9003_init_chains(struct athn_softc *);
+void	ar9003_set_rxchains(struct athn_softc *);
+void	ar9003_read_noisefloor(struct athn_softc *, int16_t *, int16_t *);
+void	ar9003_write_noisefloor(struct athn_softc *, int16_t *, int16_t *);
+void	ar9003_get_noisefloor(struct athn_softc *, struct ieee80211_channel *);
+void	ar9003_bb_load_noisefloor(struct athn_softc *);
+void	ar9300_noisefloor_calib(struct athn_softc *);
+void	ar9003_do_noisefloor_calib(struct athn_softc *);
+int	ar9003_init_calib(struct athn_softc *);
+void	ar9003_do_calib(struct athn_softc *);
+void	ar9003_next_calib(struct athn_softc *);
+void	ar9003_calib_iq(struct athn_softc *);
+int	ar9003_get_iq_corr(struct athn_softc *, int32_t[], int32_t[]);
+int	ar9003_calib_tx_iq(struct athn_softc *);
+void	ar9003_write_txpower(struct athn_softc *, int16_t power[]);
+void	ar9003_reset_rx_gain(struct athn_softc *, struct ieee80211_channel *);
+void	ar9003_reset_tx_gain(struct athn_softc *, struct ieee80211_channel *);
+void	ar9003_hw_init(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9003_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const uint8_t *, const struct ar_cal_target_power_leg *,
+	    int, uint8_t[]);
+void	ar9003_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const uint8_t *, const struct ar_cal_target_power_ht *,
+	    int, uint8_t[]);
+void	ar9003_set_noise_immunity_level(struct athn_softc *, int);
+void	ar9003_enable_ofdm_weak_signal(struct athn_softc *);
+void	ar9003_disable_ofdm_weak_signal(struct athn_softc *);
+void	ar9003_set_cck_weak_signal(struct athn_softc *, int);
+void	ar9003_set_firstep_level(struct athn_softc *, int);
+void	ar9003_set_spur_immunity_level(struct athn_softc *, int);
+
+/* Extern functions. */
+void	athn_stop(struct ifnet *, int);
+int	athn_interpolate(int, int, int, int, int);
+int	athn_txtime(struct athn_softc *, int, int, u_int);
+void	athn_inc_tx_trigger_level(struct athn_softc *);
+void	athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);
+void	athn_config_pcie(struct athn_softc *);
+void	athn_config_nonpcie(struct athn_softc *);
+uint8_t	athn_chan2fbin(struct ieee80211_channel *);
+
+
+int
+ar9003_attach(struct athn_softc *sc)
+{
+	struct athn_ops *ops = &sc->ops;
+	int error;
+
+	/* Set callbacks for AR9003 family. */
+	ops->gpio_read = ar9003_gpio_read;
+	ops->gpio_write = ar9003_gpio_write;
+	ops->gpio_config_input = ar9003_gpio_config_input;
+	ops->gpio_config_output = ar9003_gpio_config_output;
+	ops->rfsilent_init = ar9003_rfsilent_init;
+
+	ops->dma_alloc = ar9003_dma_alloc;
+	ops->dma_free = ar9003_dma_free;
+	ops->rx_enable = ar9003_rx_enable;
+	ops->intr = ar9003_intr;
+	ops->tx = ar9003_tx;
+
+	ops->set_rf_mode = ar9003_set_rf_mode;
+	ops->rf_bus_request = ar9003_rf_bus_request;
+	ops->rf_bus_release = ar9003_rf_bus_release;
+	ops->set_phy = ar9003_set_phy;
+	ops->set_delta_slope = ar9003_set_delta_slope;
+	ops->enable_antenna_diversity = ar9003_enable_antenna_diversity;
+	ops->init_baseband = ar9003_init_baseband;
+	ops->disable_phy = ar9003_disable_phy;
+	ops->set_rxchains = ar9003_set_rxchains;
+	ops->noisefloor_calib = ar9003_do_noisefloor_calib;
+	ops->do_calib = ar9003_do_calib;
+	ops->next_calib = ar9003_next_calib;
+	ops->hw_init = ar9003_hw_init;
+
+	ops->set_noise_immunity_level = ar9003_set_noise_immunity_level;
+	ops->enable_ofdm_weak_signal = ar9003_enable_ofdm_weak_signal;
+	ops->disable_ofdm_weak_signal = ar9003_disable_ofdm_weak_signal;
+	ops->set_cck_weak_signal = ar9003_set_cck_weak_signal;
+	ops->set_firstep_level = ar9003_set_firstep_level;
+	ops->set_spur_immunity_level = ar9003_set_spur_immunity_level;
+
+	/* Set MAC registers offsets. */
+	sc->obs_off = AR_OBS;
+	sc->gpio_input_en_off = AR_GPIO_INPUT_EN_VAL;
+
+	if (!(sc->flags & ATHN_FLAG_PCIE))
+		athn_config_nonpcie(sc);
+	else
+		athn_config_pcie(sc);
+
+	/* Read entire ROM content in memory. */
+	if ((error = ar9003_read_rom(sc)) != 0) {
+		printf(": could not read ROM\n");
+		return (error);
+	}
+
+	ops->setup(sc);
+	return (0);
+}
+
+/*
+ * Read 16-bit value from ROM.
+ */
+int
+ar9003_read_rom_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)
+{
+	uint32_t reg;
+	int ntries;
+
+	reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
+	for (ntries = 0; ntries < 1000; ntries++) {
+		reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
+		if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |
+		    AR_EEPROM_STATUS_DATA_PROT_ACCESS))) {
+			*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
+			return (0);
+		}
+		DELAY(10);
+	}
+	*val = 0xffff;
+	return (ETIMEDOUT);
+}
+
+/*
+ * Read an arbitrary number of bytes at a specified address in ROM.
+ * NB: The address may not be 16-bit aligned.
+ */
+int
+ar9003_read_rom_data(struct athn_softc *sc, uint32_t addr, void *buf, int len)
+{
+	uint8_t *dst = buf;
+	uint16_t val;
+	int error;
+
+	if (len > 0 && (addr & 1)) {
+		/* Deal with non-aligned reads. */
+		addr >>= 1;
+		error = ar9003_read_rom_word(sc, addr, &val);
+		if (error != 0)
+			return (error);
+		*dst++ = val & 0xff;
+		addr--;
+		len--;
+	} else
+		addr >>= 1;
+	for (; len >= 2; addr--, len -= 2) {
+		error = ar9003_read_rom_word(sc, addr, &val);
+		if (error != 0)
+			return (error);
+		*dst++ = val >> 8;
+		*dst++ = val & 0xff;
+	}
+	if (len > 0) {
+		error = ar9003_read_rom_word(sc, addr, &val);
+		if (error != 0)
+			return (error);
+		*dst++ = val >> 8;
+	}
+	return (0);
+}
+
+int
+ar9003_restore_rom_block(struct athn_softc *sc, uint8_t alg, uint8_t ref,
+    const uint8_t *buf, int len)
+{
+	const uint8_t *ptr, *end;
+	uint8_t *eep = sc->eep;
+	int off, clen;
+
+	if (alg == AR_EEP_COMPRESS_BLOCK) {
+		/* Block contains chunks of ROM image. */
+		if (ref != 0 && ref != 2) {
+			DPRINTF(("bad reference %d\n", ref));
+			return (EINVAL);
+		}
+		off = 0;	/* Offset in ROM image. */
+		ptr = buf;	/* Offset in block. */
+		end = buf + len;
+		/* Process chunks. */
+		while (ptr + 2 <= end) {
+			off += *ptr++;	/* Gap with previous chunk. */
+			clen = *ptr++;	/* Chunk length. */
+			/* Make sure block is large enough. */
+			if (ptr + clen > end)
+				return (EINVAL);
+			/* Make sure chunk fits in ROM image. */
+			if (off + clen > sc->eep_size)
+				return (EINVAL);
+			/* Restore chunk. */
+			DPRINTFN(2, ("ROM chunk @%d/%d\n", off, clen));
+			memcpy(&eep[off], ptr, clen);
+			ptr += clen;
+			off += clen;
+		}
+	} else if (alg == AR_EEP_COMPRESS_NONE) {
+		/* Block contains full ROM image. */
+		if (len != sc->eep_size) {
+			DPRINTF(("block length mismatch %d\n", len));
+			return (EINVAL);
+		}
+		memcpy(eep, buf, len);
+	}
+	return (0);
+}
+
+int
+ar9003_read_rom(struct athn_softc *sc)
+{
+	uint8_t *buf, *ptr, alg, ref;
+	uint16_t sum, rsum;
+	uint32_t hdr;
+	int error, addr, len, i, j;
+
+	/* Allocate space to store ROM in host memory. */
+	sc->eep = malloc(sc->eep_size, M_DEVBUF, M_NOWAIT);
+	if (sc->eep == NULL)
+		return (ENOMEM);
+	/* Initialize with default ROM image (little endian.) */
+	memcpy(sc->eep, sc->eep_def, sc->eep_size);
+
+	/* Allocate temporary buffer to store ROM blocks. */
+	buf = malloc(2048, M_DEVBUF, M_NOWAIT);
+	if (buf == NULL)
+		return (ENOMEM);
+
+	/* Restore vendor-specified ROM blocks. */
+	addr = sc->eep_base;
+	for (i = 0; i < 100; i++) {
+		/* Read block header. */
+		error = ar9003_read_rom_data(sc, addr, &hdr, sizeof(hdr));
+		if (error != 0)
+			break;
+		if (hdr == 0 || hdr == 0xffffffff)
+			break;
+		addr -= sizeof(hdr);
+
+		/* Extract bits from header. */
+		ptr = (uint8_t *)&hdr;
+		alg = (ptr[0] & 0xe0) >> 5;
+		ref = (ptr[1] & 0x80) >> 2 | (ptr[0] & 0x1f);
+		len = (ptr[1] & 0x7f) << 4 | (ptr[2] & 0xf0) >> 4;
+		DPRINTFN(2, ("ROM block %d: alg=%d ref=%d len=%d\n",
+		    i, alg, ref, len));
+
+		/* Read block data (len <= 0x7ff). */
+		error = ar9003_read_rom_data(sc, addr, buf, len);
+		if (error != 0)
+			break;
+		addr -= len;
+
+		/* Read block checksum. */
+		error = ar9003_read_rom_data(sc, addr, &sum, sizeof(sum));
+		if (error != 0)
+			break;
+		addr -= sizeof(sum);
+
+		/* Compute block checksum. */
+		rsum = 0;
+		for (j = 0; j < len; j++)
+			rsum += buf[j];
+		/* Compare to that in ROM. */
+		if (letoh16(sum) != rsum) {
+			DPRINTF(("bad block checksum 0x%x/0x%x\n",
+			    letoh16(sum), rsum));
+			continue;	/* Skip bad block. */
+		}
+		/* Checksum is correct, restore block. */
+		ar9003_restore_rom_block(sc, alg, ref, buf, len);
+	}
+#if BYTE_ORDER == BIG_ENDIAN
+	/* NB: ROM is always little endian. */
+	if (error == 0)
+		sc->ops.swap_rom(sc);
+#endif
+	free(buf, M_DEVBUF);
+	return (error);
+}
+
+/*
+ * Access to General Purpose Input/Output ports.
+ */
+int
+ar9003_gpio_read(struct athn_softc *sc, int pin)
+{
+	KASSERT(pin < sc->ngpiopins);
+	return ((AR_READ(sc, AR_GPIO_IN_OUT) >> pin) & 1);
+}
+
+void
+ar9003_gpio_write(struct athn_softc *sc, int pin, int set)
+{
+	uint32_t reg;
+
+	KASSERT(pin < sc->ngpiopins);
+	reg = AR_READ(sc, AR_GPIO_IN_OUT);
+	if (set)
+		reg |= 1 << pin;
+	else
+		reg &= ~(1 << pin);
+	AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
+}
+
+void
+ar9003_gpio_config_input(struct athn_softc *sc, int pin)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_GPIO_OE_OUT);
+	reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+	reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
+	AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+}
+
+void
+ar9003_gpio_config_output(struct athn_softc *sc, int pin, int type)
+{
+	uint32_t reg;
+	int mux, off;
+
+	mux = pin / 6;
+	off = pin % 6;
+
+	reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
+	reg &= ~(0x1f << (off * 5));
+	reg |= (type & 0x1f) << (off * 5);
+	AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
+
+	reg = AR_READ(sc, AR_GPIO_OE_OUT);
+	reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
+	reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
+	AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+}
+
+void
+ar9003_rfsilent_init(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	/* Configure hardware radio switch. */
+	AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
+	reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
+	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
+	AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
+	ar9003_gpio_config_input(sc, sc->rfsilent_pin);
+	AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
+	if (!(sc->flags & ATHN_FLAG_RFSILENT_REVERSED)) {
+		AR_SETBITS(sc, AR_GPIO_INTR_POL,
+		    AR_GPIO_INTR_POL_PIN(sc->rfsilent_pin));
+	}
+}
+
+int
+ar9003_dma_alloc(struct athn_softc *sc)
+{
+	int error;
+
+	error = ar9003_tx_alloc(sc);
+	if (error != 0)
+		return (error);
+
+	error = ar9003_rx_alloc(sc, ATHN_QID_LP, AR9003_RX_LP_QDEPTH);
+	if (error != 0)
+		return (error);
+
+	error = ar9003_rx_alloc(sc, ATHN_QID_HP, AR9003_RX_HP_QDEPTH);
+	if (error != 0)
+		return (error);
+
+	return (0);
+}
+
+void
+ar9003_dma_free(struct athn_softc *sc)
+{
+	ar9003_tx_free(sc);
+	ar9003_rx_free(sc, ATHN_QID_LP);
+	ar9003_rx_free(sc, ATHN_QID_HP);
+}
+
+int
+ar9003_tx_alloc(struct athn_softc *sc)
+{
+	struct athn_tx_buf *bf;
+	bus_size_t size;
+	int error, nsegs, i;
+
+	/*
+	 * Allocate Tx status ring.
+	 */
+	size = AR9003_NTXSTATUS * sizeof(struct ar_tx_status);
+
+	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+	    BUS_DMA_NOWAIT, &sc->txsmap);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->txsseg, 1,
+	    &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_map(sc->sc_dmat, &sc->txsseg, 1, size,
+	    (caddr_t *)&sc->txsring, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamap_load_raw(sc->sc_dmat, sc->txsmap, &sc->txsseg,
+	    1, size, BUS_DMA_NOWAIT | BUS_DMA_READ);
+	if (error != 0)
+		goto fail;
+
+	/*
+	 * Allocate a pool of Tx descriptors shared between all Tx queues.
+	 */
+	size = ATHN_NTXBUFS * sizeof(struct ar_tx_desc);
+
+	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
+	    BUS_DMA_NOWAIT, &sc->map);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->seg, 1,
+	    &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamem_map(sc->sc_dmat, &sc->seg, 1, size,
+	    (caddr_t *)&sc->descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
+	if (error != 0)
+		goto fail;
+
+	error = bus_dmamap_load_raw(sc->sc_dmat, sc->map, &sc->seg, 1, size,
+	    BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+	if (error != 0)
+		goto fail;
+
+	SIMPLEQ_INIT(&sc->txbufs);
+	for (i = 0; i < ATHN_NTXBUFS; i++) {
+		bf = &sc->txpool[i];
+
+		error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ,
+		    AR9003_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT,
+		    &bf->bf_map);
+		if (error != 0) {
+			printf("%s: could not create Tx buf DMA map\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+
+		bf->bf_descs = &((struct ar_tx_desc *)sc->descs)[i];
+		bf->bf_daddr = sc->map->dm_segs[0].ds_addr +
+		    i * sizeof(struct ar_tx_desc);
+
+		SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
+	}
+	return (0);
+ fail:
+	ar9003_tx_free(sc);
+	return (error);
+}
+
+void
+ar9003_tx_free(struct athn_softc *sc)
+{
+	struct athn_tx_buf *bf;
+	int i;
+
+	for (i = 0; i < ATHN_NTXBUFS; i++) {
+		bf = &sc->txpool[i];
+
+		if (bf->bf_map != NULL)
+			bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+	}
+	/* Free Tx descriptors. */
+	if (sc->map != NULL) {
+		if (sc->descs != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, sc->map);
+			bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->descs,
+			    ATHN_NTXBUFS * sizeof(struct ar_tx_desc));
+			bus_dmamem_free(sc->sc_dmat, &sc->seg, 1);
+		}
+		bus_dmamap_destroy(sc->sc_dmat, sc->map);
+	}
+	/* Free Tx status ring. */
+	if (sc->txsmap != NULL) {
+		if (sc->txsring != NULL) {
+			bus_dmamap_unload(sc->sc_dmat, sc->txsmap);
+			bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->txsring,
+			     AR9003_NTXSTATUS * sizeof(struct ar_tx_status));
+			bus_dmamem_free(sc->sc_dmat, &sc->txsseg, 1);
+		}
+		bus_dmamap_destroy(sc->sc_dmat, sc->txsmap);
+	}
+}
+
+int
+ar9003_rx_alloc(struct athn_softc *sc, int qid, int count)
+{
+	struct athn_rxq *rxq = &sc->rxq[qid];
+	struct athn_rx_buf *bf;
+	struct ar_rx_status *ds;
+	int error, i;
+
+	rxq->bf = malloc(count * sizeof(*bf), M_DEVBUF, M_NOWAIT | M_ZERO);
+	if (rxq->bf == NULL)
+		return (ENOMEM);
+
+	rxq->count = count;
+
+	for (i = 0; i < rxq->count; i++) {
+		bf = &rxq->bf[i];
+
+		error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1,
+		    ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
+		    &bf->bf_map);
+		if (error != 0) {
+			printf("%s: could not create Rx buf DMA map\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+		/*
+		 * Assumes MCLGETI returns cache-line-size aligned buffers.
+		 */
+		bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+		if (bf->bf_m == NULL) {
+			printf("%s: could not allocate Rx mbuf\n",
+			    sc->sc_dev.dv_xname);
+			error = ENOBUFS;
+			goto fail;
+		}
+
+		error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+		    mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+		    BUS_DMA_NOWAIT);
+		if (error != 0) {
+			printf("%s: could not DMA map Rx buffer\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+
+		ds = mtod(bf->bf_m, struct ar_rx_status *);
+		memset(ds, 0, sizeof(*ds));
+		bf->bf_desc = ds;
+		bf->bf_daddr = bf->bf_map->dm_segs[0].ds_addr;
+
+		bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
+		    bf->bf_map->dm_mapsize, BUS_DMASYNC_PREREAD);
+	}
+	return (0);
+ fail:
+	ar9003_rx_free(sc, qid);
+	return (error);
+}
+
+void
+ar9003_rx_free(struct athn_softc *sc, int qid)
+{
+	struct athn_rxq *rxq = &sc->rxq[qid];
+	struct athn_rx_buf *bf;
+	int i;
+
+	for (i = 0; i < rxq->count; i++) {
+		bf = &rxq->bf[i];
+
+		if (bf->bf_map != NULL)
+			bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
+		if (bf->bf_m != NULL)
+			m_freem(bf->bf_m);
+	}
+	if (rxq->bf != NULL)
+		free(rxq->bf, M_DEVBUF);
+}
+
+void
+ar9003_reset_txsring(struct athn_softc *sc)
+{
+	sc->txscur = 0;
+	memset(sc->txsring, 0, sc->txsmap->dm_mapsize);
+	AR_WRITE(sc, AR_Q_STATUS_RING_START,
+	    sc->txsmap->dm_segs[0].ds_addr);
+	AR_WRITE(sc, AR_Q_STATUS_RING_END,
+	    sc->txsmap->dm_segs[0].ds_addr + sc->txsmap->dm_segs[0].ds_len);
+}
+
+void
+ar9003_rx_enable(struct athn_softc *sc)
+{
+	struct athn_rxq *rxq;
+	struct athn_rx_buf *bf;
+	struct ar_rx_status *ds;
+	uint32_t reg;
+	int qid, i;
+
+	reg = AR_READ(sc, AR_RXBP_THRESH);
+	reg = RW(reg, AR_RXBP_THRESH_HP, 1);
+	reg = RW(reg, AR_RXBP_THRESH_LP, 1);
+	AR_WRITE(sc, AR_RXBP_THRESH, reg);
+
+	/* Set Rx buffer size. */
+	AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds));
+
+	for (qid = 0; qid < 2; qid++) {
+		rxq = &sc->rxq[qid];
+
+		/* Setup Rx status descriptors. */
+		SIMPLEQ_INIT(&rxq->head);
+		for (i = 0; i < rxq->count; i++) {
+			bf = &rxq->bf[i];
+			ds = bf->bf_desc;
+
+			memset(ds, 0, sizeof(*ds));
+			if (qid == ATHN_QID_LP)
+				AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
+			else
+				AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
+			SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+		}
+	}
+	/* Enable Rx. */
+	AR_WRITE(sc, AR_CR, AR_CR_RXE);
+}
+
+#if NBPFILTER > 0
+void
+ar9003_rx_radiotap(struct athn_softc *sc, struct mbuf *m,
+    struct ar_rx_status *ds)
+{
+#define IEEE80211_RADIOTAP_F_SHORTGI	0x80	/* XXX from FBSD */
+
+	struct athn_rx_radiotap_header *tap = &sc->sc_rxtap;
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct mbuf mb;
+	uint64_t tsf;
+	uint32_t tstamp;
+	uint8_t rate;
+
+	/* Extend the 15-bit timestamp from Rx status to 64-bit TSF. */
+	tstamp = ds->ds_status3;
+	tsf = AR_READ(sc, AR_TSF_U32);
+	tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32);
+	if ((tsf & 0x7fff) < tstamp)
+		tsf -= 0x8000;
+	tsf = (tsf & ~0x7fff) | tstamp;
+
+	tap->wr_flags = IEEE80211_RADIOTAP_F_FCS;
+	tap->wr_tsft = htole64(tsf);
+	tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
+	tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
+	tap->wr_dbm_antsignal = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED);
+	/* XXX noise. */
+	tap->wr_antenna = MS(ds->ds_status4, AR_RXS4_ANTENNA);
+	tap->wr_rate = 0;	/* In case it can't be found below. */
+	rate = MS(ds->ds_status1, AR_RXS1_RATE);
+	if (rate & 0x80) {		/* HT. */
+		/* Bit 7 set means HT MCS instead of rate. */
+		tap->wr_rate = rate;
+		if (!(ds->ds_status4 & AR_RXS4_GI))
+			tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
+
+	} else if (rate & 0x10) {	/* CCK. */
+		if (rate & 0x04)
+			tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+		switch (rate & ~0x14) {
+		case 0xb: tap->wr_rate =   2; break;
+		case 0xa: tap->wr_rate =   4; break;
+		case 0x9: tap->wr_rate =  11; break;
+		case 0x8: tap->wr_rate =  22; break;
+		}
+	} else {			/* OFDM. */
+		switch (rate) {
+		case 0xb: tap->wr_rate =  12; break;
+		case 0xf: tap->wr_rate =  18; break;
+		case 0xa: tap->wr_rate =  24; break;
+		case 0xe: tap->wr_rate =  36; break;
+		case 0x9: tap->wr_rate =  48; break;
+		case 0xd: tap->wr_rate =  72; break;
+		case 0x8: tap->wr_rate =  96; break;
+		case 0xc: tap->wr_rate = 108; break;
+		}
+	}
+	mb.m_data = (caddr_t)tap;
+	mb.m_len = sc->sc_rxtap_len;
+	mb.m_next = m;
+	mb.m_nextpkt = NULL;
+	mb.m_type = 0;
+	mb.m_flags = 0;
+	bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN);
+}
+#endif
+
+int
+ar9003_rx_process(struct athn_softc *sc, int qid)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ifnet *ifp = &ic->ic_if;
+	struct athn_rxq *rxq = &sc->rxq[qid];
+	struct athn_rx_buf *bf;
+	struct ar_rx_status *ds;
+	struct ieee80211_frame *wh;
+	struct ieee80211_rxinfo rxi;
+	struct ieee80211_node *ni;
+	struct mbuf *m, *m1;
+	int error, len;
+
+	bf = SIMPLEQ_FIRST(&rxq->head);
+	if (__predict_false(bf == NULL)) {	/* Should not happen. */
+		printf("%s: Rx queue is empty!\n", sc->sc_dev.dv_xname);
+		return (ENOENT);
+	}
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
+	    bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
+
+	ds = mtod(m, struct ar_rx_status *);
+	if (!(ds->ds_status1 & AR_RXS1_DONE))
+		return (EBUSY);
+
+	/* Check that it is a valid Rx status descriptor. */
+	if ((ds->ds_info & (AR_RXI_DESC_ID_M | AR_RXI_DESC_TX |
+	    AR_RXI_CTRL_STAT)) != SM(AR_RXI_DESC_ID, AR_VENDOR_ATHEROS))
+		return (0);
+
+	if (!(ds->ds_status11 & AR_RXS11_FRAME_OK)) {
+		if (ds->ds_status11 & AR_RXS11_CRC_ERR)
+			DPRINTFN(6, ("CRC error\n"));
+		else if (ds->ds_status11 & AR_RXS11_PHY_ERR)
+			DPRINTFN(6, ("PHY error=0x%x\n",
+			    MS(ds->ds_status11, AR_RXS11_PHY_ERR_CODE)));
+		else if (ds->ds_status11 & AR_RXS11_DECRYPT_CRC_ERR)
+			DPRINTFN(6, ("Decryption CRC error\n"));
+		else if (ds->ds_status11 & AR_RXS11_MICHAEL_ERR) {
+			DPRINTFN(2, ("Michael MIC failure\n"));
+			/* Report Michael MIC failures to net80211. */
+			ic->ic_stats.is_rx_locmicfail++;
+			ieee80211_michael_mic_failure(ic, 0);
+			/*
+			 * XXX Check that it is not a control frame
+			 * (invalid MIC failures on valid ctl frames.)
+			 */
+		}
+		ifp->if_ierrors++;
+		goto skip;
+	}
+
+	len = MS(ds->ds_status2, AR_RXS2_DATA_LEN);
+	if (__predict_false(len == 0 || len > ATHN_RXBUFSZ)) {
+		DPRINTF(("corrupted descriptor length=%d\n", len));
+		ifp->if_ierrors++;
+		goto skip;
+	}
+
+	/* Allocate a new Rx buffer. */
+	m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
+	if (__predict_false(m1 == NULL)) {
+		ic->ic_stats.is_rx_nombuf++;
+		ifp->if_ierrors++;
+		goto skip;
+	}
+
+	/* Sync and unmap the old Rx buffer. */
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
+	    BUS_DMASYNC_POSTREAD);
+	bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+	/* Map the new Rx buffer. */
+	error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *),
+	    ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ);
+	if (__predict_false(error != 0)) {
+		m_freem(m1);
+
+		/* Remap the old Rx buffer or panic. */
+		error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
+		    mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
+		    BUS_DMA_NOWAIT | BUS_DMA_READ);
+		KASSERT(error != 0);
+		ifp->if_ierrors++;
+		goto skip;
+	}
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+	    BUS_DMASYNC_PREREAD);
+
+	m = bf->bf_m;
+	bf->bf_m = m1;
+
+	/* Finalize mbuf. */
+	m->m_pkthdr.rcvif = ifp;
+	/* Strip Rx descriptor from head. */
+	m->m_data = (caddr_t)&ds[1];
+	m->m_pkthdr.len = m->m_len = len;
+
+	/* Grab a reference to the source node. */
+	wh = mtod(m, struct ieee80211_frame *);
+	ni = ieee80211_find_rxnode(ic, wh);
+
+#if NBPFILTER > 0
+	if (__predict_false(sc->sc_drvbpf != NULL))
+		ar9003_rx_radiotap(sc, m, ds);
+#endif
+	/* Trim 802.11 FCS after radiotap. */
+	m_adj(m, -IEEE80211_CRC_LEN);
+
+	/* Send the frame to the 802.11 layer. */
+	rxi.rxi_flags = 0;	/* XXX */
+	rxi.rxi_rssi = MS(ds->ds_status5, AR_RXS5_RSSI_COMBINED);
+	rxi.rxi_tstamp = ds->ds_status3;
+	ieee80211_input(ifp, m, ni, &rxi);
+
+	/* Node is no longer needed. */
+	ieee80211_release_node(ic, ni);
+
+ skip:
+	/* Unlink this descriptor from head. */
+	SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list);
+	memset(ds, 0, sizeof(*ds));
+
+	/* Re-use this descriptor and link it to tail. */
+	if (qid == ATHN_QID_LP)
+		AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr);
+	else
+		AR_WRITE(sc, AR_HP_RXDP, bf->bf_daddr);
+	SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
+
+	/* Re-enable Rx. */
+	AR_WRITE(sc, AR_CR, 0);
+	return (0);
+}
+
+void
+ar9003_rx_intr(struct athn_softc *sc, int qid)
+{
+	while (ar9003_rx_process(sc, qid) == 0);
+}
+
+int
+ar9003_tx_process(struct athn_softc *sc)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ifnet *ifp = &ic->ic_if;
+	struct athn_txq *txq;
+	struct athn_node *an;
+	struct athn_tx_buf *bf;
+	struct ar_tx_status *ds;
+	uint8_t qid, failcnt;
+
+	ds = &((struct ar_tx_status *)sc->txsring)[sc->txscur];
+	if (!(ds->ds_status8 & AR_TXS8_DONE))
+		return (EBUSY);
+
+	sc->txscur = (sc->txscur + 1) % AR9003_NTXSTATUS;
+
+	/* Check that it is a valid Tx status descriptor. */
+	if ((ds->ds_info & (AR_TXI_DESC_ID_M | AR_TXI_DESC_TX)) !=
+	    (SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) | AR_TXI_DESC_TX))
+		return (0);
+
+	/* Retrieve the queue that was used to send this PDU. */
+	qid = MS(ds->ds_info, AR_TXI_QCU_NUM);
+	txq = &sc->txq[qid];
+
+	bf = SIMPLEQ_FIRST(&txq->head);
+	if (__predict_false(bf == NULL))
+		return (0);
+
+	SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
+	ifp->if_opackets++;
+
+	sc->sc_tx_timer = 0;
+
+	if (ds->ds_status3 & AR_TXS3_EXCESSIVE_RETRIES)
+		ifp->if_oerrors++;
+
+	if (ds->ds_status3 & AR_TXS3_UNDERRUN)
+		athn_inc_tx_trigger_level(sc);
+
+	an = (struct athn_node *)bf->bf_ni;
+	/*
+	 * NB: the data fail count contains the number of un-acked tries
+	 * for the final series used.  We must add the number of tries for
+	 * each series that was fully processed.
+	 */
+	failcnt  = MS(ds->ds_status3, AR_TXS3_DATA_FAIL_CNT);
+	/* NB: Assume two tries per series. */
+	failcnt += MS(ds->ds_status8, AR_TXS8_FINAL_IDX) * 2;
+
+	/* Update rate control statistics. */
+	an->amn.amn_txcnt++;
+	if (failcnt > 0)
+		an->amn.amn_retrycnt++;
+
+	DPRINTFN(5, ("Tx done qid=%d status3=%d fail count=%d\n",
+	    qid, ds->ds_status3, failcnt));
+
+	/* Reset Tx status descriptor. */
+	memset(ds, 0, sizeof(*ds));
+
+	/* Unmap Tx buffer. */
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+	    BUS_DMASYNC_POSTWRITE);
+	bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+
+	m_freem(bf->bf_m);
+	bf->bf_m = NULL;
+	ieee80211_release_node(ic, bf->bf_ni);
+	bf->bf_ni = NULL;
+
+	/* Link Tx buffer back to global free list. */
+	SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
+	return (0);
+}
+
+void
+ar9003_tx_intr(struct athn_softc *sc)
+{
+	while (ar9003_tx_process(sc) == 0);
+}
+
+int
+ar9003_intr(struct athn_softc *sc)
+{
+	uint32_t intr, intr2, intr5, sync;
+
+	/* Get pending interrupts. */
+	intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
+	if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
+		intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
+		if (intr == AR_INTR_SPURIOUS || (intr & sc->isync) == 0)
+			return (0);	/* Not for us. */
+	}
+
+	if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
+	    (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
+		intr = AR_READ(sc, AR_ISR);
+	else
+		intr = 0;
+	sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->isync;
+	if (intr == 0 && sync == 0)
+		return (0);	/* Not for us. */
+
+	if (intr != 0) {
+		if (intr & AR_ISR_BCNMISC) {
+			intr2 = AR_READ(sc, AR_ISR_S2);
+			if (intr2 & AR_ISR_S2_TIM)
+				/* TBD */;
+			if (intr2 & AR_ISR_S2_TSFOOR)
+				/* TBD */;
+		}
+		intr = AR_READ(sc, AR_ISR_RAC);
+		if (intr == AR_INTR_SPURIOUS)
+			return (1);
+
+		if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
+			ar9003_rx_intr(sc, ATHN_QID_LP);
+		if (intr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
+			ar9003_rx_intr(sc, ATHN_QID_LP);
+		if (intr & AR_ISR_HP_RXOK)
+			ar9003_rx_intr(sc, ATHN_QID_HP);
+
+		if (intr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
+			ar9003_tx_intr(sc);
+		if (intr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL))
+			ar9003_tx_intr(sc);
+
+		if (intr & AR_ISR_GENTMR) {
+			intr5 = AR_READ(sc, AR_ISR_S5_S);
+			DPRINTF(("GENTMR trigger=%d thresh=%d\n",
+			    MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
+			    MS(intr5, AR_ISR_S5_GENTIMER_THRESH)));
+		}
+	}
+	if (sync != 0) {
+		if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
+			AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
+			AR_WRITE(sc, AR_RC, 0);
+		}
+
+		if ((sc->flags & ATHN_FLAG_RFSILENT) &&
+		    (sync & AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin))) {
+			struct ifnet *ifp = &sc->sc_ic.ic_if;
+
+			printf("%s: radio switch turned off\n",
+			    sc->sc_dev.dv_xname);
+			/* Turn the interface down. */
+			ifp->if_flags &= ~IFF_UP;
+			athn_stop(ifp, 1);
+			return (1);
+		}
+
+		AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
+		(void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
+	}
+	return (1);
+}
+
+int
+ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ieee80211_key *k = NULL;
+	struct ieee80211_frame *wh;
+	struct athn_series series[4];
+	struct ar_tx_desc *ds;
+	struct athn_txq *txq;
+	struct athn_tx_buf *bf;
+	struct athn_node *an = (void *)ni;
+	struct mbuf *m1;
+	uintptr_t entry;
+	uint32_t sum;
+	uint16_t qos;
+	uint8_t txpower, type, encrtype, tid, ridx[4];
+	int i, error, totlen, hasqos, qid;
+
+	/* Grab a Tx buffer from our global free list. */
+	bf = SIMPLEQ_FIRST(&sc->txbufs);
+	KASSERT(bf != NULL);
+	SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list);
+
+	/* Map 802.11 frame type to hardware frame type. */
+	wh = mtod(m, struct ieee80211_frame *);
+	if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
+	    IEEE80211_FC0_TYPE_MGT) {
+		if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+		    IEEE80211_FC0_SUBTYPE_BEACON)
+			type = AR_FRAME_TYPE_BEACON;
+		else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+		    IEEE80211_FC0_SUBTYPE_PROBE_RESP)
+			type = AR_FRAME_TYPE_PROBE_RESP;
+		else if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
+		    IEEE80211_FC0_SUBTYPE_ATIM)
+			type = AR_FRAME_TYPE_ATIM;
+		else
+			type = AR_FRAME_TYPE_NORMAL;
+	} else if ((wh->i_fc[0] &
+	    (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
+	    (IEEE80211_FC0_TYPE_CTL  | IEEE80211_FC0_SUBTYPE_PS_POLL)) {
+		type = AR_FRAME_TYPE_PSPOLL;
+	} else
+		type = AR_FRAME_TYPE_NORMAL;
+
+	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
+		k = ieee80211_get_txkey(ic, wh, ni);
+		if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
+			return (ENOBUFS);
+		wh = mtod(m, struct ieee80211_frame *);
+	}
+
+	/* XXX 2-byte padding for QoS and 4-addr headers. */
+
+	/* Select the HW Tx queue to use for this frame. */
+	if ((hasqos = ieee80211_has_qos(wh))) {
+		qos = ieee80211_get_qos(wh);
+		tid = qos & IEEE80211_QOS_TID;
+		qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)];
+	} else if (type == AR_FRAME_TYPE_BEACON) {
+		qid = ATHN_QID_BEACON;
+	} else if (type == AR_FRAME_TYPE_PSPOLL) {
+		qid = ATHN_QID_PSPOLL;
+	} else
+		qid = ATHN_QID_AC_BE;
+	txq = &sc->txq[qid];
+
+	/* Select the transmit rates to use for this frame. */
+	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+	    (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
+	    IEEE80211_FC0_TYPE_DATA) {
+		/* Use lowest rate for all tries. */
+		ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+		    (ic->ic_curmode == IEEE80211_MODE_11A) ?
+			ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1;
+	} else if (ic->ic_fixed_rate != -1) {
+		/* Use same fixed rate for all tries. */
+		ridx[0] = ridx[1] = ridx[2] = ridx[3] =
+		    sc->fixed_ridx;
+	} else {
+		int txrate = ni->ni_txrate;
+		/* Use fallback table of the node. */
+		for (i = 0; i < 4; i++) {
+			ridx[i] = an->ridx[txrate];
+			txrate = an->fallback[txrate];
+		}
+	}
+
+#if NBPFILTER > 0
+	if (__predict_false(sc->sc_drvbpf != NULL)) {
+		struct athn_tx_radiotap_header *tap = &sc->sc_txtap;
+		struct mbuf mb;
+
+		tap->wt_flags = 0;
+		/* Use initial transmit rate. */
+		tap->wt_rate = athn_rates[ridx[0]].rate;
+		tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
+		tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
+		tap->wt_hwqueue = qid;
+		if (ridx[0] != ATHN_RIDX_CCK1 &&
+		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+			tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
+		mb.m_data = (caddr_t)tap;
+		mb.m_len = sc->sc_txtap_len;
+		mb.m_next = m;
+		mb.m_nextpkt = NULL;
+		mb.m_type = 0;
+		mb.m_flags = 0;
+		bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT);
+	}
+#endif
+
+	/* DMA map mbuf. */
+	error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+	    BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+	if (__predict_false(error != 0)) {
+		if (error != EFBIG) {
+			printf("%s: can't map mbuf (error %d)\n",
+			    sc->sc_dev.dv_xname, error);
+			m_freem(m);
+			return (error);
+		}
+		/*
+		 * DMA mapping requires too many DMA segments; linearize
+		 * mbuf in kernel virtual address space and retry.
+		 */
+		MGETHDR(m1, M_DONTWAIT, MT_DATA);
+		if (m1 == NULL) {
+			m_freem(m);
+			return (ENOBUFS);
+		}
+		if (m->m_pkthdr.len > MHLEN) {
+			MCLGET(m1, M_DONTWAIT);
+			if (!(m1->m_flags & M_EXT)) {
+				m_freem(m);
+				m_freem(m1);
+				return (ENOBUFS);
+			}
+		}
+		m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t));
+		m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len;
+		m_freem(m);
+		m = m1;
+
+		error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
+		    BUS_DMA_NOWAIT | BUS_DMA_WRITE);
+		if (error != 0) {
+			printf("%s: can't map mbuf (error %d)\n",
+			    sc->sc_dev.dv_xname, error);
+			m_freem(m);
+			return (error);
+		}
+	}
+	bf->bf_m = m;
+	bf->bf_ni = ni;
+
+	wh = mtod(m, struct ieee80211_frame *);
+
+	totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
+
+	/* Setup Tx descriptor. */
+	ds = bf->bf_descs;
+	memset(ds, 0, sizeof(*ds));
+
+	ds->ds_info =
+	    SM(AR_TXI_DESC_ID, AR_VENDOR_ATHEROS) |
+	    SM(AR_TXI_DESC_NDWORDS, 23) |
+	    SM(AR_TXI_QCU_NUM, qid) |
+	    AR_TXI_DESC_TX | AR_TXI_CTRL_STAT;
+
+	ds->ds_ctl11 = AR_TXC11_CLR_DEST_MASK;
+	txpower = AR_MAX_RATE_POWER;	/* Get from per-rate registers. */
+	ds->ds_ctl11 |= SM(AR_TXC11_XMIT_POWER, txpower);
+
+	ds->ds_ctl12 = SM(AR_TXC12_FRAME_TYPE, type);
+
+	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
+	    (hasqos && (qos & IEEE80211_QOS_ACK_POLICY_MASK) ==
+	     IEEE80211_QOS_ACK_POLICY_NOACK))
+		ds->ds_ctl12 |= AR_TXC12_NO_ACK;
+
+	if (0 && wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
+		/* Retrieve key for encryption. */
+		k = ieee80211_get_txkey(ic, wh, ni);
+		/*
+		 * Map 802.11 cipher to hardware encryption type and
+		 * compute crypto overhead.
+		 */
+		switch (k->k_cipher) {
+		case IEEE80211_CIPHER_WEP40:
+		case IEEE80211_CIPHER_WEP104:
+			encrtype = AR_ENCR_TYPE_WEP;
+			totlen += 8;
+			break;
+		case IEEE80211_CIPHER_TKIP:
+			encrtype = AR_ENCR_TYPE_TKIP;
+			totlen += 20;
+			break;
+		case IEEE80211_CIPHER_CCMP:
+			encrtype = AR_ENCR_TYPE_AES;
+			totlen += 16;
+			break;
+		default:
+			panic("unsupported cipher");	/* XXX BIP? */
+		}
+		/*
+		 * NB: The key cache entry index is stored in the key
+		 * private field when the key is installed.
+		 */
+		entry = (uintptr_t)k->k_priv;
+		ds->ds_ctl12 |= SM(AR_TXC12_DEST_IDX, entry);
+		ds->ds_ctl11 |= AR_TXC11_DEST_IDX_VALID;
+	} else
+		encrtype = AR_ENCR_TYPE_CLEAR;
+	ds->ds_ctl17 = SM(AR_TXC17_ENCR_TYPE, encrtype);
+
+	/* Check if frame must be protected using RTS/CTS or CTS-to-self. */
+	if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
+		/* NB: Group frames are sent using CCK in 802.11b/g. */
+		if (totlen > ic->ic_rtsthreshold) {
+			ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE;
+		} else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
+		    athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) {
+			if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
+				ds->ds_ctl11 |= AR_TXC11_RTS_ENABLE;
+			else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
+				ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE;
+		}
+	}
+	if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) {
+		/* Disable multi-rate retries when protection is used. */
+		ridx[1] = ridx[2] = ridx[3] = ridx[0];
+	}
+	/* Setup multi-rate retries. */
+	for (i = 0; i < 4; i++) {
+		series[i].hwrate = athn_rates[ridx[i]].hwrate;
+		if (athn_rates[ridx[i]].phy == IEEE80211_T_DS &&
+		    ridx[i] != ATHN_RIDX_CCK1 &&
+		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+			series[i].hwrate |= 0x04;
+		series[i].dur = 0;
+	}
+	if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) {
+		/* Compute duration for each series. */
+		for (i = 0; i < 4; i++) {
+			series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN,
+			    athn_rates[ridx[i]].rspridx, ic->ic_flags);
+		}
+	}
+
+	/* Write number of tries for each series. */
+	ds->ds_ctl13 =
+	    SM(AR_TXC13_XMIT_DATA_TRIES0, 2) |
+	    SM(AR_TXC13_XMIT_DATA_TRIES1, 2) |
+	    SM(AR_TXC13_XMIT_DATA_TRIES2, 2) |
+	    SM(AR_TXC13_XMIT_DATA_TRIES3, 4);
+
+	/* Tell HW to update duration field in 802.11 header. */
+	if (type != AR_FRAME_TYPE_PSPOLL)
+		ds->ds_ctl13 |= AR_TXC13_DUR_UPDATE_ENA;
+
+	/* Write Tx rate for each series. */
+	ds->ds_ctl14 =
+	    SM(AR_TXC14_XMIT_RATE0, series[0].hwrate) |
+	    SM(AR_TXC14_XMIT_RATE1, series[1].hwrate) |
+	    SM(AR_TXC14_XMIT_RATE2, series[2].hwrate) |
+	    SM(AR_TXC14_XMIT_RATE3, series[3].hwrate);
+
+	/* Write duration for each series. */
+	ds->ds_ctl15 =
+	    SM(AR_TXC15_PACKET_DUR0, series[0].dur) |
+	    SM(AR_TXC15_PACKET_DUR1, series[1].dur);
+	ds->ds_ctl16 =
+	    SM(AR_TXC16_PACKET_DUR2, series[2].dur) |
+	    SM(AR_TXC16_PACKET_DUR3, series[3].dur);
+
+	/* Use the same Tx chains for all tries. */
+	ds->ds_ctl18 =
+	    SM(AR_TXC18_CHAIN_SEL0, sc->txchainmask) |
+	    SM(AR_TXC18_CHAIN_SEL1, sc->txchainmask) |
+	    SM(AR_TXC18_CHAIN_SEL2, sc->txchainmask) |
+	    SM(AR_TXC18_CHAIN_SEL3, sc->txchainmask);
+#ifdef notyet
+#ifndef IEEE80211_NO_HT
+	/* Use the same short GI setting for all tries. */
+	if (ic->ic_flags & IEEE80211_F_SHGI)
+		ds->ds_ctl18 |= AR_TXC18_GI0123;
+	/* Use the same channel width for all tries. */
+	if (ic->ic_flags & IEEE80211_F_CBW40)
+		ds->ds_ctl18 |= AR_TXC18_2040_0123;
+#endif
+#endif
+
+	if (ds->ds_ctl11 & (AR_TXC11_RTS_ENABLE | AR_TXC11_CTS_ENABLE)) {
+		uint8_t protridx, hwrate;
+		uint16_t dur = 0;
+
+		/* Use the same protection mode for all tries. */
+		if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) {
+			ds->ds_ctl15 |= AR_TXC15_RTSCTS_QUAL01;
+			ds->ds_ctl16 |= AR_TXC16_RTSCTS_QUAL23;
+		}
+		/* Select protection rate (suboptimal but ok.) */
+		protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
+		    ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2;
+		if (ds->ds_ctl11 & AR_TXC11_RTS_ENABLE) {
+			/* Account for CTS duration. */
+			dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+			    athn_rates[protridx].rspridx, ic->ic_flags);
+		}
+		dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags);
+		if (!(ds->ds_ctl12 & AR_TXC12_NO_ACK)) {
+			/* Account for ACK duration. */
+			dur += athn_txtime(sc, IEEE80211_ACK_LEN,
+			    athn_rates[ridx[0]].rspridx, ic->ic_flags);
+		}
+		/* Write protection frame duration and rate. */
+		ds->ds_ctl13 |= SM(AR_TXC13_BURST_DUR, dur);
+		hwrate = athn_rates[protridx].hwrate;
+		if (protridx == ATHN_RIDX_CCK2 &&
+		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
+			hwrate |= 0x04;
+		ds->ds_ctl18 |= SM(AR_TXC18_RTSCTS_RATE, hwrate);
+	}
+
+	ds->ds_ctl11 |= SM(AR_TXC11_FRAME_LEN, totlen);
+	ds->ds_ctl19 = AR_TXC19_NOT_SOUNDING;
+
+	for (i = 0; i < bf->bf_map->dm_nsegs; i++) {
+		ds->ds_segs[i].ds_data = bf->bf_map->dm_segs[i].ds_addr;
+		ds->ds_segs[i].ds_ctl = SM(AR_TXC_BUF_LEN,
+		    bf->bf_map->dm_segs[i].ds_len);
+	}
+	/* Compute Tx descriptor checksum. */
+	sum = ds->ds_info + ds->ds_link;
+	for (i = 0; i < 4; i++) {
+		sum += ds->ds_segs[i].ds_data;
+		sum += ds->ds_segs[i].ds_ctl;
+	}
+	sum = (sum >> 16) + (sum & 0xffff);
+	ds->ds_ctl10 = SM(AR_TXC10_PTR_CHK_SUM, sum);
+
+	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
+	    BUS_DMASYNC_PREWRITE);
+
+	if (!SIMPLEQ_EMPTY(&txq->head))
+		((struct ar_tx_desc *)txq->lastds)->ds_link = bf->bf_daddr;
+	else
+		AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
+	txq->lastds = ds;
+	SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list);
+
+	DPRINTFN(6, ("Tx qid=%d nsegs=%d ctl11=0x%x ctl12=0x%x ctl14=0x%x\n",
+	    qid, bf->bf_map->dm_nsegs, ds->ds_ctl11, ds->ds_ctl12,
+	    ds->ds_ctl14));
+
+	/* Kick Tx. */
+	AR_WRITE(sc, AR_Q_TXE, 1 << qid);
+	return (0);
+}
+
+void
+ar9003_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+	if (IEEE80211_IS_CHAN_2GHZ(c))
+		AR_WRITE(sc, AR_PHY_MODE, AR_PHY_MODE_DYNAMIC);
+	else
+		AR_WRITE(sc, AR_PHY_MODE, AR_PHY_MODE_OFDM);
+}
+
+static __inline uint32_t
+ar9003_synth_delay(struct athn_softc *sc)
+{
+	uint32_t delay;
+
+	delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY);
+	if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B)
+		delay = (delay * 4) / 22;
+	else
+		delay = delay / 10;	/* in 100ns steps */
+	return (delay);
+}
+
+int
+ar9003_rf_bus_request(struct athn_softc *sc)
+{
+	int ntries;
+
+	/* Request RF Bus grant. */
+	AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
+	for (ntries = 0; ntries < 10000; ntries++) {
+		if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN)
+			return (0);
+		DELAY(10);
+	}
+	DPRINTF(("could not kill baseband Rx"));
+	return (ETIMEDOUT);
+}
+
+void
+ar9003_rf_bus_release(struct athn_softc *sc)
+{
+	/* Wait for the synthesizer to settle. */
+	DELAY(AR_BASE_PHY_ACTIVE_DELAY + ar9003_synth_delay(sc));
+
+	/* Release the RF Bus grant. */
+	AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
+}
+
+void
+ar9003_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	uint32_t phy;
+
+	phy = AR_READ(sc, AR_PHY_GEN_CTRL);
+	phy |= AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 |
+	    AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH;
+#ifndef IEEE80211_NO_HT
+	if (extc != NULL) {
+		phy |= AR_PHY_GC_DYN2040_EN;
+		if (extc > c)	/* XXX */
+			phy |= AR_PHY_GC_DYN2040_PRI_CH;
+	}
+#endif
+	/* Turn off Green Field detection for now. */
+	phy &= ~AR_PHY_GC_GF_DETECT_EN;
+	AR_WRITE(sc, AR_PHY_GEN_CTRL, phy);
+
+	AR_WRITE(sc, AR_2040_MODE,
+	    (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0);
+
+	/* Set global transmit timeout. */
+	AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
+	/* Set carrier sense timeout. */
+	AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
+}
+
+void
+ar9003_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	uint32_t coeff, exp, man, reg;
+
+	/* Set Delta Slope (exponent and mantissa). */
+	coeff = (100 << 24) / c->ic_freq;
+	athn_get_delta_slope(coeff, &exp, &man);
+	DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man));
+
+	reg = AR_READ(sc, AR_PHY_TIMING3);
+	reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
+	reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
+	AR_WRITE(sc, AR_PHY_TIMING3, reg);
+
+	/* For Short GI, coeff is 9/10 that of normal coeff. */
+	coeff = (9 * coeff) / 10;
+	athn_get_delta_slope(coeff, &exp, &man);
+	DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man));
+
+	reg = AR_READ(sc, AR_PHY_SGI_DELTA);
+	reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp);
+	reg = RW(reg, AR_PHY_SGI_DSC_MAN, man);
+	AR_WRITE(sc, AR_PHY_SGI_DELTA, reg);
+}
+
+void
+ar9003_enable_antenna_diversity(struct athn_softc *sc)
+{
+	AR_SETBITS(sc, AR_PHY_CCK_DETECT,
+	    AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+}
+
+void
+ar9003_init_baseband(struct athn_softc *sc)
+{
+	uint32_t synth_delay;
+
+	synth_delay = ar9003_synth_delay(sc);
+	/* Activate the PHY (includes baseband activate and synthesizer on). */
+	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
+	DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay);
+}
+
+void
+ar9003_disable_phy(struct athn_softc *sc)
+{
+	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+}
+
+void
+ar9003_init_chains(struct athn_softc *sc)
+{
+	if (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5)
+		AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
+
+	/* Setup chain masks. */
+	AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  sc->rxchainmask);
+	AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
+
+	AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask);
+}
+
+void
+ar9003_set_rxchains(struct athn_softc *sc)
+{
+	if (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5) {
+		AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  sc->rxchainmask);
+		AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
+	}
+}
+
+void
+ar9003_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+/* Sign-extend 9-bit value to 16-bit. */
+#define SIGN_EXT(v)	((((int16_t)(v)) << 7) >> 7)
+	uint32_t reg;
+	int i;
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		reg = AR_READ(sc, AR_PHY_CCA(i));
+		nf[i] = MS(reg, AR_PHY_MINCCA_PWR);
+		nf[i] = SIGN_EXT(nf[i]);
+
+		reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+		nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);
+		nf_ext[i] = SIGN_EXT(nf_ext[i]);
+	}
+#undef SIGN_EXT
+}
+
+void
+ar9003_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
+{
+	uint32_t reg;
+	int i;
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		reg = AR_READ(sc, AR_PHY_CCA(i));
+		reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
+		AR_WRITE(sc, AR_PHY_CCA(i), reg);
+
+		reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
+		reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
+		AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
+	}
+}
+
+void
+ar9003_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+	int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+	int16_t min, max;
+	int i;
+
+	if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
+		/* Noisefloor calibration not finished. */
+		return;
+	}
+	/* Noisefloor calibration is finished. */
+	ar9003_read_noisefloor(sc, nf, nf_ext);
+
+	if (IEEE80211_IS_CHAN_2GHZ(c)) {
+		min = sc->cca_min_2g;
+		max = sc->cca_max_2g;
+	} else {
+		min = sc->cca_min_5g;
+		max = sc->cca_max_5g;
+	}
+	/* Update noisefloor history. */
+	for (i = 0; i < sc->nrxchains; i++) {
+		if (nf[i] < min)
+			nf[i] = min;
+		else if (nf[i] > max)
+			nf[i] = max;
+		if (nf_ext[i] < min)
+			nf_ext[i] = min;
+		else if (nf_ext[i] > max)
+			nf_ext[i] = max;
+
+		sc->nf_hist[sc->nf_hist_cur].nf[i] = nf[i];
+		sc->nf_hist[sc->nf_hist_cur].nf_ext[i] = nf_ext[i];
+	}
+	if (++sc->nf_hist_cur >= ATHN_NF_CAL_HIST_MAX)
+		sc->nf_hist_cur = 0;
+}
+
+void
+ar9003_bb_load_noisefloor(struct athn_softc *sc)
+{
+	int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
+	int i, ntries;
+
+	/* Write filtered noisefloor values. */
+	for (i = 0; i < sc->nrxchains; i++) {
+		nf[i] = sc->nf_priv[i] * 2;
+		nf_ext[i] = sc->nf_ext_priv[i] * 2;
+	}
+	ar9003_write_noisefloor(sc, nf, nf_ext);
+
+	/* Load filtered noisefloor values into baseband. */
+	AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+	/* Wait for load to complete. */
+	for (ntries = 0; ntries < 1000; ntries++) {
+		if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
+			break;
+		DELAY(10);
+	}
+	if (ntries == 1000) {
+		DPRINTF(("failed to load noisefloor values\n"));
+		return;
+	}
+
+	/* Restore noisefloor values to initial (max) values. */
+	for (i = 0; i < AR_MAX_CHAINS; i++)
+		nf[i] = nf_ext[i] = -50 * 2;
+	ar9003_write_noisefloor(sc, nf, nf_ext);
+}
+
+void
+ar9300_noisefloor_calib(struct athn_softc *sc)
+{
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+}
+
+void
+ar9003_do_noisefloor_calib(struct athn_softc *sc)
+{
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+}
+
+int
+ar9003_init_calib(struct athn_softc *sc)
+{
+	uint8_t txchainmask, rxchainmask;
+	uint32_t reg;
+	int ntries;
+
+	/* Save chains masks. */
+	txchainmask = sc->txchainmask;
+	rxchainmask = sc->rxchainmask;
+	/* Configure for 3-chain mode before calibration. */
+	txchainmask = rxchainmask = 0x7;
+	ar9003_init_chains(sc);
+
+	/* Calibrate the AGC. */
+	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
+	/* Poll for offset calibration completion. */
+	for (ntries = 0; ntries < 10000; ntries++) {
+		reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
+		if (!(reg & AR_PHY_AGC_CONTROL_CAL))
+			break;
+		DELAY(10);
+	}
+	if (ntries == 10000)
+		return (ETIMEDOUT);
+
+#ifdef notyet
+	/* Perform Tx I/Q calibration. */
+	ar9003_calib_tx_iq(sc);
+#endif
+
+	/* Restore chains masks. */
+	sc->txchainmask = txchainmask;
+	sc->rxchainmask = rxchainmask;
+	ar9003_init_chains(sc);
+
+	return (0);
+}
+
+void
+ar9003_do_calib(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	if (sc->calib_mask & ATHN_CAL_IQ) {
+		reg = AR_READ(sc, AR_PHY_TIMING4);
+		reg = RW(reg, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
+		    AR_MAX_LOG_CAL);
+		AR_WRITE(sc, AR_PHY_TIMING4, reg);
+		AR_WRITE(sc, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
+		AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
+	} else if (sc->calib_mask & ATHN_CAL_TEMP) {
+		AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
+		    AR_PHY_65NM_CH0_THERM_LOCAL);
+		AR_SETBITS(sc, AR_PHY_65NM_CH0_THERM,
+		    AR_PHY_65NM_CH0_THERM_START);
+	}
+}
+
+void
+ar9003_next_calib(struct athn_softc *sc)
+{
+	if (AR_READ(sc, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL) {
+		/* Calibration in progress, come back later. */
+		return;
+	}
+	if (sc->calib_mask & ATHN_CAL_IQ)
+		ar9003_calib_iq(sc);
+}
+
+void
+ar9003_calib_iq(struct athn_softc *sc)
+{
+	struct athn_iq_cal *cal;
+	uint32_t reg, i_coff_denom, q_coff_denom;
+	int32_t i_coff, q_coff;
+	int i, iq_corr_neg;
+
+	for (i = 0; i < AR_MAX_CHAINS; i++) {
+		cal = &sc->calib.iq[i];
+
+		/* Accumulate IQ calibration measures (clear on read). */
+		cal->pwr_meas_i += AR_READ(sc, AR_PHY_IQ_ADC_MEAS_0_B(i));
+		cal->pwr_meas_q += AR_READ(sc, AR_PHY_IQ_ADC_MEAS_1_B(i));
+		cal->iq_corr_meas +=
+		    (int32_t)AR_READ(sc, AR_PHY_IQ_ADC_MEAS_2_B(i));
+	}
+	if (++sc->calib.nsamples < AR_CAL_SAMPLES) {
+		/* Not enough samples accumulated, continue. */
+		ar9003_do_calib(sc);
+		return;
+	}
+
+	for (i = 0; i < sc->nrxchains; i++) {
+		cal = &sc->calib.iq[i];
+
+		if (cal->pwr_meas_q == 0)
+			continue;
+
+		if ((iq_corr_neg = cal->iq_corr_meas < 0))
+			cal->iq_corr_meas = -cal->iq_corr_meas;
+
+		i_coff_denom =
+		    (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 256;
+		q_coff_denom = cal->pwr_meas_q / 64;
+
+		if (i_coff_denom == 0 || q_coff_denom == 0)
+			continue;	/* Prevents division by zero. */
+
+		i_coff = cal->iq_corr_meas / i_coff_denom;
+		q_coff = (cal->pwr_meas_i / q_coff_denom) - 64;
+
+		if (i_coff > 63)
+			i_coff = 63;
+		else if (i_coff < -63)
+			i_coff = -63;
+		/* Negate i_coff if iq_corr_meas is positive. */
+		if (!iq_corr_neg)
+			i_coff = -i_coff;
+		if (q_coff > 63)
+			q_coff = 63;
+		else if (q_coff < -63)
+			q_coff = -63;
+
+		DPRINTFN(2, ("IQ calibration for chain %d\n", i));
+		reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
+		reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, i_coff);
+		reg = RW(reg, AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, q_coff);
+		AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
+	}
+
+	AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
+	    AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
+}
+
+#define DELPT	32
+int
+ar9003_get_iq_corr(struct athn_softc *sc, int32_t res[6], int32_t coeff[2])
+{
+/* Sign-extend 12-bit values to 32-bit. */
+#define SIGN_EXT(v)	((((int32_t)(v)) << 20) >> 20)
+#define SCALE		(1 << 15)
+#define SHIFT		(1 <<  8)
+	struct {
+		int32_t	m, p, c;
+	} val[2][2];
+	int32_t mag[2][2], phs[2][2], cos[2], sin[2];
+	int32_t min, max, div, f1, f2, f3, m, p, c;
+	int32_t txmag, txphs, rxmag, rxphs;
+	int32_t q_coff, i_coff;
+	int i, j;
+
+	/* Extract our twelve signed 12-bit values from res[] array. */
+	val[0][0].m = res[0] & 0xfff;
+	val[0][0].p = (res[0] >> 12) & 0xfff;
+	val[0][0].c = ((res[0] >> 24) & 0xff) | (res[1] & 0xf) << 8;
+
+	val[0][1].m = (res[1] >> 4) & 0xfff;
+	val[0][1].p = res[2] & 0xfff;
+	val[0][1].c = (res[2] >> 12) & 0xfff;
+
+	val[1][0].m = ((res[2] >> 24) & 0xff) | (res[3] & 0xf) << 8;
+	val[1][0].p = (res[3] >> 4) & 0xfff;
+	val[1][0].c = res[4] & 0xfff;
+
+	val[1][1].m = (res[4] >> 12) & 0xfff;
+	val[1][1].p = ((res[4] >> 24) & 0xff) | (res[5] & 0xf) << 8;
+	val[1][1].c = (res[5] >> 4) & 0xfff;
+
+	for (i = 0; i < 2; i++) {
+		for (j = 0; j < 2; j++) {
+			m = SIGN_EXT(val[i][j].m);
+			p = SIGN_EXT(val[i][j].p);
+			c = SIGN_EXT(val[i][j].c);
+
+			if (p == 0)
+				return (1);	/* Prevent division by 0. */
+
+			mag[i][j] = (m * SCALE) / p;
+			phs[i][j] = (c * SCALE) / p;
+		}
+		sin[i] = ((mag[i][0] - mag[i][1]) * SHIFT) / DELPT;
+		cos[i] = ((phs[i][0] - phs[i][1]) * SHIFT) / DELPT;
+		/* Find magnitude by approximation. */
+		min = MIN(abs(sin[i]), abs(cos[i]));
+		max = MAX(abs(sin[i]), abs(cos[i]));
+		div = max - (max / 32) + (min / 8) + (min / 4);
+		if (div == 0)
+			return (1);	/* Prevent division by 0. */
+		/* Normalize sin and cos by magnitude. */
+		sin[i] = (sin[i] * SCALE) / div;
+		cos[i] = (cos[i] * SCALE) / div;
+	}
+
+	/* Compute I/Q mismatch (solve 4x4 linear equation.) */
+	f1 = cos[0] - cos[1];
+	f3 = sin[0] - sin[1];
+	f2 = (f1 * f1 + f3 * f3) / SCALE;
+	if (f2 == 0)
+		return (1);	/* Prevent division by 0. */
+
+	/* Compute Tx magnitude mismatch. */
+	txmag = (f1 * ( mag[0][0] - mag[1][0]) +
+		 f3 * ( phs[0][0] - phs[1][0])) / f2;
+	/* Compute Tx phase mismatch. */
+	txphs = (f3 * (-mag[0][0] + mag[1][0]) +
+		 f1 * ( phs[0][0] - phs[1][0])) / f2;
+
+	if (txmag == SCALE)
+		return (1);	/* Prevent division by 0. */
+
+	/* Compute Rx magnitude mismatch. */
+	rxmag = mag[0][0] - (cos[0] * txmag + sin[0] * txphs) / SCALE;
+	/* Compute Rx phase mismatch. */
+	rxphs = phs[0][0] + (sin[0] * txmag - cos[0] * txphs) / SCALE;
+
+	if (rxmag == SCALE)
+		return (1);	/* Prevent division by 0. */
+
+	txmag = (txmag * SCALE) / (SCALE - txmag);
+	txphs = -txphs;
+
+	q_coff = (txmag * 128) / SCALE;
+	if (q_coff < -63)
+		q_coff = -63;
+	else if (q_coff > 63)
+		q_coff = 63;
+	i_coff = (txphs * 256) / SCALE;
+	if (i_coff < -63)
+		i_coff = -63;
+	else if (i_coff > 63)
+		i_coff = 63;
+	coeff[0] = q_coff * 128 + i_coff;
+
+	rxmag = (-rxmag * SCALE) / (SCALE + rxmag);
+	rxphs = -rxphs;
+
+	q_coff = (rxmag * 128) / SCALE;
+	if (q_coff < -63)
+		q_coff = -63;
+	else if (q_coff > 63)
+		q_coff = 63;
+	i_coff = (rxphs * 256) / SCALE;
+	if (i_coff < -63)
+		i_coff = -63;
+	else if (i_coff > 63)
+		i_coff = 63;
+	coeff[1] = q_coff * 128 + i_coff;
+
+	return (0);
+#undef SHIFT
+#undef SCALE
+#undef SIGN_EXT
+}
+
+int
+ar9003_calib_tx_iq(struct athn_softc *sc)
+{
+	uint32_t reg;
+	int32_t res[6], coeff[2];
+	int i, j, ntries;
+
+	reg = AR_READ(sc, AR_PHY_TX_IQCAL_CONTROL_1);
+	reg = RW(reg, AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
+	AR_WRITE(sc, AR_PHY_TX_IQCAL_CONTROL_1, reg);
+
+	/* Start Tx I/Q calibration. */
+	AR_SETBITS(sc, AR_PHY_TX_IQCAL_START, AR_PHY_TX_IQCAL_START_DO_CAL);
+	/* Wait for completion. */
+	for (ntries = 0; ntries < 10000; ntries++) {
+		reg = AR_READ(sc, AR_PHY_TX_IQCAL_START);
+		if (!(reg & AR_PHY_TX_IQCAL_START_DO_CAL))
+			break;
+		DELAY(10);
+	}
+	if (ntries == 10000)
+		return (ETIMEDOUT);
+
+	for (i = 0; i < sc->ntxchains; i++) {
+		/* Read Tx I/Q calibration status for this chain. */
+		reg = AR_READ(sc, AR_PHY_TX_IQCAL_STATUS_B(i));
+		if (reg & AR_PHY_TX_IQCAL_STATUS_FAILED)
+			return (EIO);
+		/*
+		 * Read Tx I/Q calibration results for this chain.
+		 * This consists in twelve signed 12-bit values.
+		 */
+		for (j = 0; j < 3; j++) {
+			AR_CLRBITS(sc, AR_PHY_CHAN_INFO_MEMORY,
+			    AR_PHY_CHAN_INFO_TAB_S2_READ);
+			reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
+			res[j * 2 + 0] = reg;
+
+			AR_SETBITS(sc, AR_PHY_CHAN_INFO_MEMORY,
+			    AR_PHY_CHAN_INFO_TAB_S2_READ);
+			reg = AR_READ(sc, AR_PHY_CHAN_INFO_TAB(i, j));
+			res[j * 2 + 1] = reg & 0xffff;
+		}
+
+		/* Compute Tx I/Q correction. */
+		if (ar9003_get_iq_corr(sc, res, coeff) != 0)
+			return (EIO);
+
+		/* Write Tx I/Q correction coefficients. */
+		reg = AR_READ(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i));
+		reg = RW(reg, AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
+		    coeff[0]);
+		AR_WRITE(sc, AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i), reg);
+
+		reg = AR_READ(sc, AR_PHY_RX_IQCAL_CORR_B(i));
+		reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
+		    coeff[1] >> 7);
+		reg = RW(reg, AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
+		    coeff[1]);
+		AR_WRITE(sc, AR_PHY_RX_IQCAL_CORR_B(i), reg);
+	}
+
+	/* Enable Tx I/Q correction. */
+	AR_SETBITS(sc, AR_PHY_TX_IQCAL_CONTROL_3,
+	    AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN);
+	AR_SETBITS(sc, AR_PHY_RX_IQCAL_CORR_B(0),
+	    AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN);
+	return (0);
+}
+#undef DELPT
+
+void
+ar9003_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
+{
+	/* Make sure forced gain is disabled. */
+	AR_WRITE(sc, AR_PHY_TX_FORCED_GAIN, 0);
+
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE1,
+	    (power[ATHN_POWER_OFDM18  ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_OFDM12  ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_OFDM9   ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_OFDM6   ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE2,
+	    (power[ATHN_POWER_OFDM54  ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_OFDM48  ] & 0x3f) << 16 |
+	    (power[ATHN_POWER_OFDM36  ] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_OFDM24  ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE3,
+	    (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 |
+	    (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 |
+	    /* NB: No eXtended Range for AR9003. */
+	    (power[ATHN_POWER_CCK1_LP ] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE4,
+	    (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 |
+	    (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 |
+	    (power[ATHN_POWER_CCK55_SP] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_CCK55_LP] & 0x3f));
+#ifndef IEEE80211_NO_HT
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE5,
+	    (power[ATHN_POWER_HT20( 5)] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT20( 4)] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT20( 1)] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT20( 0)] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE6,
+	    (power[ATHN_POWER_HT20(13)] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT20(12)] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT20( 7)] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT20( 6)] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE7,
+	    (power[ATHN_POWER_HT40( 5)] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT40( 4)] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT40( 1)] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT40( 0)] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE8,
+	    (power[ATHN_POWER_HT40(13)] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT40(12)] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT40( 7)] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT40( 6)] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE10,
+	    (power[ATHN_POWER_HT20(21)] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT20(20)] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT20(15)] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT20(14)] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE11,
+	    (power[ATHN_POWER_HT40(23)] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT40(22)] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT20(23)] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT20(22)] & 0x3f));
+	AR_WRITE(sc, AR_PHY_PWRTX_RATE12,
+	    (power[ATHN_POWER_HT40(21)] & 0x3f) << 24 |
+	    (power[ATHN_POWER_HT40(20)] & 0x3f) << 16 |
+	    (power[ATHN_POWER_HT40(15)] & 0x3f) <<  8 |
+	    (power[ATHN_POWER_HT40(14)] & 0x3f));
+#endif
+}
+
+void
+ar9003_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+#define X(x)	((uint32_t)(x) << 2)
+	const struct athn_gain *prog = sc->rx_gain;
+	const uint32_t *pvals;
+	int i;
+
+	if (IEEE80211_IS_CHAN_2GHZ(c))
+		pvals = prog->vals_2g;
+	else
+		pvals = prog->vals_5g;
+	for (i = 0; i < prog->nregs; i++)
+		AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
+#undef X
+}
+
+void
+ar9003_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+#define X(x)	((uint32_t)(x) << 2)
+	const struct athn_gain *prog = sc->tx_gain;
+	const uint32_t *pvals;
+	int i;
+
+	if (IEEE80211_IS_CHAN_2GHZ(c))
+		pvals = prog->vals_2g;
+	else
+		pvals = prog->vals_5g;
+	for (i = 0; i < prog->nregs; i++)
+		AR_WRITE(sc, X(prog->regs[i]), pvals[i]);
+#undef X
+}
+
+void
+ar9003_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+#define X(x)	((uint32_t)(x) << 2)
+	struct athn_ops *ops = &sc->ops;
+	const struct athn_ini *ini = sc->ini;
+	const uint32_t *pvals;
+	uint32_t reg;
+	int i;
+
+	/*
+	 * The common init values include the pre and core phases for the
+	 * SoC, MAC, BB and Radio subsystems.
+	 */
+	DPRINTFN(4, ("writing pre and core init vals\n"));
+	for (i = 0; i < ini->ncmregs; i++) {
+		AR_WRITE(sc, X(ini->cmregs[i]), ini->cmvals[i]);
+		if (AR_IS_ANALOG_REG(X(ini->cmregs[i])))
+			DELAY(100);
+		if ((i & 0x1f) == 0)
+			DELAY(1);
+	}
+
+	/*
+	 * The modal init values include the post phase for the SoC, MAC,
+	 * BB and Radio subsystems.
+	 */
+#ifndef IEEE80211_NO_HT
+	if (extc != NULL) {
+		if (IEEE80211_IS_CHAN_2GHZ(c))
+			pvals = ini->vals_2g40;
+		else
+			pvals = ini->vals_5g40;
+	} else
+#endif
+	{
+		if (IEEE80211_IS_CHAN_2GHZ(c))
+			pvals = ini->vals_2g20;
+		else
+			pvals = ini->vals_5g20;
+	}
+	DPRINTFN(4, ("writing post init vals\n"));
+	for (i = 0; i < ini->nregs; i++) {
+		AR_WRITE(sc, X(ini->regs[i]), pvals[i]);
+		if (AR_IS_ANALOG_REG(X(ini->regs[i])))
+			DELAY(100);
+		if ((i & 0x1f) == 0)
+			DELAY(1);
+	}
+
+	if (sc->rx_gain != NULL)
+		ar9003_reset_rx_gain(sc, c);
+	if (sc->tx_gain != NULL)
+		ar9003_reset_tx_gain(sc, c);
+
+	/*
+	 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted
+	 * descriptor status.
+	 */
+	AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
+
+	reg = AR_READ(sc, AR_PCU_MISC_MODE2);
+	reg &= ~AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE;
+	reg |= AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX;
+	reg |= AR_PCU_MISC_MODE2_ENABLE_AGGWEP;
+	AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
+
+	ar9003_set_phy(sc, c, extc);
+	ar9003_init_chains(sc);
+
+	ops->set_txpower(sc, c, extc);
+#undef X
+}
+
+void
+ar9003_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+    uint8_t ctl, const uint8_t *fbins,
+    const struct ar_cal_target_power_leg *tgt, int nchans, uint8_t tpow[4])
+{
+	uint8_t fbin;
+	int i, delta, lo, hi;
+
+	lo = hi = -1;
+	fbin = athn_chan2fbin(c);
+	for (i = 0; i < nchans; i++) {
+		delta = fbin - fbins[i];
+		/* Find the largest sample that is <= our frequency. */
+		if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo]))
+			lo = i;
+		/* Find the smallest sample that is >= our frequency. */
+		if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi]))
+			hi = i;
+	}
+	if (lo == -1)
+		lo = hi;
+	else if (hi == -1)
+		hi = lo;
+	/* Interpolate values. */
+	for (i = 0; i < 4; i++) {
+		tpow[i] = athn_interpolate(fbin,
+		    fbins[lo], tgt[lo].tPow2x[i],
+		    fbins[hi], tgt[hi].tPow2x[i]);
+	}
+	/* XXX Apply conformance test limit. */
+}
+
+#ifndef IEEE80211_NO_HT
+void
+ar9003_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
+    uint8_t ctl, const uint8_t *fbins,
+    const struct ar_cal_target_power_ht *tgt, int nchans, uint8_t tpow[14])
+{
+	uint8_t fbin;
+	int i, delta, lo, hi;
+
+	lo = hi = -1;
+	fbin = athn_chan2fbin(c);
+	for (i = 0; i < nchans; i++) {
+		delta = fbin - fbins[i];
+		/* Find the largest sample that is <= our frequency. */
+		if (delta >= 0 && (lo == -1 || delta < fbin - fbins[lo]))
+			lo = i;
+		/* Find the smallest sample that is >= our frequency. */
+		if (delta <= 0 && (hi == -1 || delta > fbin - fbins[hi]))
+			hi = i;
+	}
+	if (lo == -1)
+		lo = hi;
+	else if (hi == -1)
+		hi = lo;
+	/* Interpolate values. */
+	for (i = 0; i < 14; i++) {
+		tpow[i] = athn_interpolate(fbin,
+		    fbins[lo], tgt[lo].tPow2x[i],
+		    fbins[hi], tgt[hi].tPow2x[i]);
+	}
+	/* XXX Apply conformance test limit. */
+}
+#endif
+
+/*
+ * Adaptive noise immunity.
+ */
+void
+ar9003_set_noise_immunity_level(struct athn_softc *sc, int level)
+{
+	int high = level == 4;
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
+	reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
+	AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
+
+	reg = AR_READ(sc, AR_PHY_AGC);
+	reg = RW(reg, AR_PHY_AGC_COARSE_LOW, high ? -70 : -64);
+	reg = RW(reg, AR_PHY_AGC_COARSE_HIGH, high ? -12 : -14);
+	AR_WRITE(sc, AR_PHY_AGC, reg);
+
+	reg = AR_READ(sc, AR_PHY_FIND_SIG);
+	reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
+	AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+}
+
+void
+ar9003_enable_ofdm_weak_signal(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
+	AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR);
+	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
+	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
+	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
+	AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
+	AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+	AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
+	    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+}
+
+void
+ar9003_disable_ofdm_weak_signal(struct athn_softc *sc)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
+	AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR);
+	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
+	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
+	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
+	AR_WRITE(sc, AR_PHY_SFCORR, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
+	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
+	AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+	AR_CLRBITS(sc, AR_PHY_SFCORR_LOW,
+	    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
+}
+
+void
+ar9003_set_cck_weak_signal(struct athn_softc *sc, int high)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_CCK_DETECT);
+	reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
+	AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
+}
+
+void
+ar9003_set_firstep_level(struct athn_softc *sc, int level)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_FIND_SIG);
+	reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
+	AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
+}
+
+void
+ar9003_set_spur_immunity_level(struct athn_softc *sc, int level)
+{
+	uint32_t reg;
+
+	reg = AR_READ(sc, AR_PHY_TIMING5);
+	reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
+	AR_WRITE(sc, AR_PHY_TIMING5, reg);
+}
diff --git a/sys/dev/ic/ar9003reg.h b/sys/dev/ic/ar9003reg.h
new file mode 100644
index 00000000000..83419e804fa
--- /dev/null
+++ b/sys/dev/ic/ar9003reg.h
@@ -0,0 +1,941 @@
+/*	$OpenBSD: ar9003reg.h,v 1.1 2010/05/10 17:44:21 damien Exp $	*/
+
+/*-
+ * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * MAC registers.
+ */
+#define AR_ISR_S2_S			0x00d0
+#define AR_ISR_S3_S			0x00d4
+#define AR_ISR_S4_S			0x00d8
+#define AR_ISR_S5_S			0x00dc
+#define AR_GPIO_IN_OUT			0x4048
+#define AR_GPIO_OE_OUT			0x4050
+#define AR_GPIO_INTR_POL		0x4058
+#define AR_GPIO_INPUT_EN_VAL		0x405c
+#define AR_GPIO_INPUT_MUX1		0x4060
+#define AR_GPIO_INPUT_MUX2		0x4064
+#define AR_GPIO_OUTPUT_MUX(i)		(0x4068 + (i) * 4)
+#define AR_INPUT_STATE			0x4074
+#define AR_EEPROM_STATUS_DATA		0x4084
+#define AR_OBS				0x4088
+#define AR_GPIO_PDPU			0x4090
+#define AR_PCIE_MSI			0x40a4
+
+/*
+ * PHY registers.
+ */
+#define AR_PHY_TIMING1			0x09800
+#define AR_PHY_TIMING2			0x09804
+#define AR_PHY_TIMING3			0x09808
+#define AR_PHY_TIMING4			0x0980c
+#define AR_PHY_TIMING5			0x09810
+#define AR_PHY_TIMING6			0x09814
+#define AR_PHY_TIMING11			0x09818
+#define AR_PHY_SPUR_REG			0x0981c
+#define AR_PHY_FIND_SIG_LOW		0x09820
+#define AR_PHY_SFCORR			0x09824
+#define AR_PHY_SFCORR_LOW		0x09828
+#define AR_PHY_SFCORR_EXT		0x0982c
+#define AR_PHY_EXT_CCA(i)		(0x09830 + (i) * 0x1000)
+#define AR_PHY_RADAR_0			0x09834
+#define AR_PHY_RADAR_1			0x09838
+#define AR_PHY_RADAR_EXT		0x0983c
+#define AR_PHY_MULTICHAIN_CTRL		0x09880
+#define AR_PHY_PERCHAIN_CSD		0x09884
+#define AR_PHY_TX_CRC			0x098a0
+#define AR_PHY_TST_DAC_CONST		0x098a4
+#define AR_PHY_SPUR_REPORT_0		0x098a8
+#define AR_PHY_TX_IQCAL_CONTROL_3	0x098b0
+#define AR_PHY_IQ_ADC_MEAS_0_B(i)	(0x098c0 + (i) * 0x1000)
+#define AR_PHY_IQ_ADC_MEAS_1_B(i)	(0x098c4 + (i) * 0x1000)
+#define AR_PHY_IQ_ADC_MEAS_2_B(i)	(0x098c8 + (i) * 0x1000)
+#define AR_PHY_IQ_ADC_MEAS_3_B(i)	(0x098cc + (i) * 0x1000)
+#define AR_PHY_TX_PHASE_RAMP_0		0x098d0
+#define AR_PHY_ADC_DC_GAIN_CORR(i)	(0x098d4 + (i) * 0x1000)
+#define AR_PHY_RX_IQCAL_CORR_B(i)	(0x098dc + (i) * 0x1000)
+#define AR_PHY_CHAN_INFO_TAB(i, j)	(0x09b00 + (i) * 0x1000 + (j) * 4)
+#define AR_PHY_TIMING_3A		0x09c00
+#define AR_PHY_LDPC_CNTL1		0x09c04
+#define AR_PHY_LDPC_CNTL2		0x09c08
+#define AR_PHY_PILOT_SPUR_MASK		0x09c0c
+#define AR_PHY_CHAN_SPUR_MASK		0x09c10
+#define AR_PHY_SGI_DELTA		0x09c14
+#define AR_PHY_ML_CNTL_1		0x09c18
+#define AR_PHY_ML_CNTL_2		0x09c1c
+#define AR_PHY_TST_ADC			0x09c20
+#define AR_PHY_SETTLING			0x09e00
+#define AR_PHY_RXGAIN(i)		(0x09e04 + (i) * 0x1000)
+#define AR_PHY_GAINS_MINOFF0		0x09e08
+#define AR_PHY_DESIRED_SZ		0x09e0c
+#define AR_PHY_FIND_SIG			0x09e10
+#define AR_PHY_AGC			0x09e14
+#define AR_PHY_EXT_ATTEN_CTL(i)		(0x09e18 + (i) * 0x1000)
+#define AR_PHY_CCA(i)			(0x09e1c + (i) * 0x1000)
+#define AR_PHY_CCA_CTRL(i)		(0x09e20 + (i) * 0x1000)
+#define AR_PHY_RESTART			0x09e24
+#define AR_PHY_MC_GAIN_CTRL		0x09e28
+#define AR_PHY_EXTCHN_PWRTHR1		0x09e2c
+#define AR_PHY_EXT_CHN_WIN		0x09e30
+#define AR_PHY_20_40_DET_THR		0x09e34
+#define AR_PHY_RIFS_SRCH		0x09e38
+#define AR_PHY_PEAK_DET_CTRL_1		0x09e3c
+#define AR_PHY_PEAK_DET_CTRL_2		0x09e40
+#define AR_PHY_RX_GAIN_BOUNDS_1		0x09e44
+#define AR_PHY_RX_GAIN_BOUNDS_2		0x09e48
+#define AR_PHY_RSSI(i)			(0x09f80 + (i) * 0x1000)
+#define AR_PHY_SPUR_CCK_REP0		0x09f84
+#define AR_PHY_CCK_DETECT		0x09fc0
+#define AR_PHY_DAG_CTRLCCK		0x09fc4
+#define AR_PHY_IQCORR_CTRL_CCK		0x09fc8
+#define AR_PHY_CCK_SPUR_MIT		0x09fcc
+#define AR_PHY_RX_OCGAIN		0x0a000
+#define AR_PHY_D2_CHIP_ID		0x0a200
+#define AR_PHY_GEN_CTRL			0x0a204
+#define AR_PHY_MODE			0x0a208
+#define AR_PHY_ACTIVE			0x0a20c
+#define AR_PHY_SPUR_MASK_A		0x0a220
+#define AR_PHY_SPUR_MASK_B		0x0a224
+#define AR_PHY_SPECTRAL_SCAN		0x0a228
+#define AR_PHY_RADAR_BW_FILTER		0x0a22c
+#define AR_PHY_SEARCH_START_DELAY	0x0a230
+#define AR_PHY_MAX_RX_LEN		0x0a234
+#define AR_PHY_FRAME_CTL		0x0a238
+#define AR_PHY_RFBUS_REQ		0x0a23c
+#define AR_PHY_RFBUS_GRANT		0x0a240
+#define AR_PHY_RIFS			0x0a244
+#define AR_PHY_RX_CLR_DELAY		0x0a250
+#define AR_PHY_RX_DELAY			0x0a254
+#define AR_PHY_XPA_TIMING_CTL		0x0a264
+#define AR_PHY_MISC_PA_CTL		0x0a280
+#define AR_PHY_SWITCH_CHAIN(i)		(0x0a284 + (i) * 0x1000)
+#define AR_PHY_SWITCH_COM		0x0a288
+#define AR_PHY_SWITCH_COM_2		0x0a28c
+#define AR_PHY_RX_CHAINMASK		0x0a2a0
+#define AR_PHY_CAL_CHAINMASK		0x0a2c0
+#define AR_PHY_AGC_CONTROL		0x0a2c4
+#define AR_PHY_CALMODE			0x0a2c8
+#define AR_PHY_FCAL_1			0x0a2cc
+#define AR_PHY_FCAL_2_0			0x0a2d0
+#define AR_PHY_DFT_TONE_CTL_0		0x0a2d4
+#define AR_PHY_CL_CAL_CTL		0x0a2d8
+#define AR_PHY_CL_TAB_0			0x0a300
+#define AR_PHY_SYNTH_CONTROL		0x0a340
+#define AR_PHY_ADDAC_CLK_SEL		0x0a344
+#define AR_PHY_PLL_CTL			0x0a348
+#define AR_PHY_ANALOG_SWAP		0x0a34c
+#define AR_PHY_ADDAC_PARA_CTL		0x0a350
+#define AR_PHY_XPA_CFG			0x0a358
+#define AR_PHY_TEST			0x0a360
+#define AR_PHY_TEST_CTL_STATUS		0x0a364
+#define AR_PHY_TSTDAC			0x0a368
+#define AR_PHY_CHAN_STATUS		0x0a36c
+#define AR_PHY_CHAN_INFO_MEMORY		0x0a370
+#define AR_PHY_CHNINFO_NOISEPWR		0x0a374
+#define AR_PHY_CHNINFO_GAINDIFF		0x0a378
+#define AR_PHY_CHNINFO_FINETIM		0x0a37c
+#define AR_PHY_CHAN_INFO_GAIN_0		0x0a380
+#define AR_PHY_SCRAMBLER_SEED		0x0a390
+#define AR_PHY_CCK_TX_CTRL		0x0a394
+#define AR_PHY_HEAVYCLIP_CTL		0x0a3a4
+#define AR_PHY_HEAVYCLIP_20		0x0a3a8
+#define AR_PHY_HEAVYCLIP_40		0x0a3ac
+#define AR_PHY_ILLEGAL_TXRATE		0x0a3b0
+#define AR_PHY_PWRTX_RATE1		0x0a3c0
+#define AR_PHY_PWRTX_RATE2		0x0a3c4
+#define AR_PHY_PWRTX_RATE3		0x0a3c8
+#define AR_PHY_PWRTX_RATE4		0x0a3cc
+#define AR_PHY_PWRTX_RATE5		0x0a3d0
+#define AR_PHY_PWRTX_RATE6		0x0a3d4
+#define AR_PHY_PWRTX_RATE7		0x0a3d8
+#define AR_PHY_PWRTX_RATE8		0x0a3dc
+#define AR_PHY_PWRTX_RATE10		0x0a3e4
+#define AR_PHY_PWRTX_RATE11		0x0a3e8
+#define AR_PHY_PWRTX_RATE12		0x0a3ec
+#define AR_PHY_PWRTX_MAX		0x0a3f0
+#define AR_PHY_POWER_TX_SUB		0x0a3f4
+#define AR_PHY_TPC_4_B0			0x0a404
+#define AR_PHY_TPCRG5(i)		(0x0a408 + (i) * 0x1000)
+#define AR_PHY_TPC_6_B(i)		(0x0a40c + (i) * 0x1000)
+#define AR_PHY_TPC_11_B(i)		(0x0a420 + (i) * 0x1000)
+#define AR_PHY_TPC_18			0x0a43c
+#define AR_PHY_TPC_19			0x0a440
+#define AR_PHY_BB_THERM_ADC_1		0x0a448
+#define AR_PHY_TX_FORCED_GAIN		0x0a458
+#define AR_PHY_PDADC_TAB(i)		(0x0a480 + (i) * 0x1000)
+#define AR_PHY_TX_IQCAL_CONTROL_1	0x0a648
+#define AR_PHY_TX_IQCAL_START		0x0a640
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i)	\
+					(0x0a650 + (i) * 0x1000)
+#define AR_PHY_TX_IQCAL_STATUS_B(i)	(0x0a68c + (i) * 0x1000)
+#define AR_PHY_PANIC_WD_STATUS		0x0a7c0
+#define AR_PHY_PANIC_WD_CTL_1		0x0a7c4
+#define AR_PHY_PANIC_WD_CTL_2		0x0a7c8
+#define AR_PHY_BT_CTL			0x0a7cc
+#define AR_PHY_ONLY_WARMRESET		0x0a7d0
+#define AR_PHY_ONLY_CTL			0x0a7d4
+#define AR_PHY_ECO_CTRL			0x0a7dc
+
+/*
+ * Analog registers.
+ */
+#define AR_IS_ANALOG_REG(reg)		((reg) >= 0x16000 && (reg) <= 0x17000)
+#define AR_PHY_65NM_CH0_SYNTH4		0x1608c
+#define AR_PHY_65NM_CH0_SYNTH7		0x16098
+#define AR_PHY_65NM_CH0_BIAS1		0x160c0
+#define AR_PHY_65NM_CH0_BIAS2		0x160c4
+#define AR_PHY_65NM_CH0_BIAS4		0x160cc
+#define AR_PHY_65NM_CH0_RXTX1		0x16100
+#define AR_PHY_65NM_CH0_RXTX2		0x16104
+#define AR_PHY_65NM_CH0_RXTX4		0x1610c
+#define AR_PHY_65NM_CH0_TOP		0x16288
+#define AR_PHY_65NM_CH0_THERM		0x16290
+#define AR_PHY_65NM_CH1_RXTX1		0x16500
+#define AR_PHY_65NM_CH1_RXTX2		0x16504
+#define AR_PHY_65NM_CH2_RXTX1		0x16900
+#define AR_PHY_65NM_CH2_RXTX2		0x16904
+
+
+/* Bits for AR_PHY_TIMING2. */
+#define AR_PHY_TIMING2_FORCE_PPM_VAL_M	0x00000fff
+#define AR_PHY_TIMING2_FORCE_PPM_VAL_S	0
+#define AR_PHY_TIMING2_USE_FORCE_PPM	0x00001000
+
+/* Bits for AR_PHY_TIMING3. */
+#define AR_PHY_TIMING3_DSC_EXP_M	0x0001e000
+#define AR_PHY_TIMING3_DSC_EXP_S	13
+#define AR_PHY_TIMING3_DSC_MAN_M	0xfffe0000
+#define AR_PHY_TIMING3_DSC_MAN_S	17
+
+/* Bits for AR_PHY_TIMING4. */
+#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_M	0x0000f000
+#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S	12
+#define AR_PHY_TIMING4_DO_CAL			0x00010000
+#define AR_PHY_TIMING4_ENABLE_PILOT_MASK	0x10000000
+#define AR_PHY_TIMING4_ENABLE_CHAN_MASK		0x20000000
+#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER	0x40000000
+#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI		0x80000000
+
+/* Bits for AR_PHY_TIMING5. */
+#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE	0x00000001
+#define AR_PHY_TIMING5_CYCPWR_THR1_M		0x000000fe
+#define AR_PHY_TIMING5_CYCPWR_THR1_S		1
+#define AR_PHY_TIMING5_RSSI_THR1A_ENA		0x00008000
+#define AR_PHY_TIMING5_CYCPWR_THR1A_M		0x007f0000
+#define AR_PHY_TIMING5_CYCPWR_THR1A_S		16
+#define AR_PHY_TIMING5_RSSI_THR1A_M		0x007f0000
+#define AR_PHY_TIMING5_RSSI_THR1A_S		16
+
+/* Bits for AR_PHY_TIMING11. */
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_M		0x000fffff
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S		0
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_M			0x3ff00000
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_S			20
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC		0x40000000
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR	0x80000000
+
+/* Bits for AR_PHY_SPUR_REG. */
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M	0x000000ff
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S	0
+#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI	0x00000100
+#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM		0x00020000
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_M	0x03fc0000
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S	18
+#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT	0x04000000
+
+/* Bits for AR_PHY_FIND_SIG_LOW. */
+#define AR_PHY_FIND_SIG_LOW_RELSTEP_M		0x0000001f
+#define AR_PHY_FIND_SIG_LOW_RELSTEP_S		0
+#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_M	0x00000fc0
+#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S	6
+#define AR_PHY_FIND_SIG_LOW_FIRPWR_M		0x0007f000
+#define AR_PHY_FIND_SIG_LOW_FIRPWR_S		12
+
+/* Bits for AR_PHY_SFCORR. */
+#define AR_PHY_SFCORR_M2COUNT_THR_M		0x0000001f
+#define AR_PHY_SFCORR_M2COUNT_THR_S		0
+#define AR_PHY_SFCORR_M1_THRESH_M		0x00fe0000
+#define AR_PHY_SFCORR_M1_THRESH_S		17
+#define AR_PHY_SFCORR_M2_THRESH_M		0x7f000000
+#define AR_PHY_SFCORR_M2_THRESH_S		24
+
+/* Bits for AR_PHY_SFCORR_LOW. */
+#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW	0x00000001
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M	0x00003f00
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S	8
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M	0x001fc000
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S	14
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M	0x0fe00000
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S	21
+
+/* Bits for AR_PHY_SFCORR_EXT. */
+#define AR_PHY_SFCORR_EXT_M1_THRESH_M		0x0000007f
+#define AR_PHY_SFCORR_EXT_M1_THRESH_S		0
+#define AR_PHY_SFCORR_EXT_M2_THRESH_M		0x00003f80
+#define AR_PHY_SFCORR_EXT_M2_THRESH_S		7
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M	0x001fc000
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S	14
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M	0x0fe00000
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S	21
+#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD	0x10000000
+
+/* Bits for AR_PHY_RADAR_0. */
+#define AR_PHY_RADAR_0_ENA		0x00000001
+#define AR_PHY_RADAR_0_INBAND_M		0x0000003e
+#define AR_PHY_RADAR_0_INBAND_S		1
+#define AR_PHY_RADAR_0_PRSSI_M		0x00000fc0
+#define AR_PHY_RADAR_0_PRSSI_S		6
+#define AR_PHY_RADAR_0_HEIGHT_M		0x0003f000
+#define AR_PHY_RADAR_0_HEIGHT_S		12
+#define AR_PHY_RADAR_0_RRSSI_M		0x00fc0000
+#define AR_PHY_RADAR_0_RRSSI_S		18
+#define AR_PHY_RADAR_0_FIRPWR_M		0x7f000000
+#define AR_PHY_RADAR_0_FIRPWR_S		24
+#define AR_PHY_RADAR_0_FFT_ENA		0x80000000
+
+/* Bits for AR_PHY_RADAR_1. */
+#define AR_PHY_RADAR_1_MAXLEN_M		0x000000ff
+#define AR_PHY_RADAR_1_MAXLEN_S		0
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_M	0x00001f00
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_S	8
+#define AR_PHY_RADAR_1_RELSTEP_CHECK	0x00002000
+#define AR_PHY_RADAR_1_MAX_RRSSI	0x00004000
+#define AR_PHY_RADAR_1_BLOCK_CHECK	0x00008000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_M	0x003f0000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_S	16
+#define AR_PHY_RADAR_1_USE_FIR128	0x00400000
+#define AR_PHY_RADAR_1_RELPWR_ENA	0x00800000
+
+/* Bits for AR_PHY_RADAR_EXT. */
+#define AR_PHY_RADAR_EXT_ENA		0x00004000
+#define AR_PHY_RADAR_DC_PWR_THRESH_M	0x007f8000
+#define AR_PHY_RADAR_DC_PWR_THRESH_S	15
+#define AR_PHY_RADAR_LB_DC_CAP_M  	0x7f800000
+#define AR_PHY_RADAR_LB_DC_CAP_S	23
+
+/* Bits for AR_PHY_TX_IQCAL_CONTROL_3. */
+#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN	0x80000000
+
+/* Bits for AR_PHY_RX_IQCAL_CORR_B(0). */
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_M		0x0000007f
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S		0
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_M		0x00003f80
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S		7
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE		0x00004000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_M	0x003f8000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S	15
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_M	0x1fc00000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S	22
+#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN	0x20000000
+
+/* Bits for AR_PHY_PILOT_SPUR_MASK. */
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_M	0x0000001f
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S	0
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_M	0x00000fe0
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S	5
+
+/* Bits for AR_PHY_CHAN_SPUR_MASK. */
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_M		0x0000001f
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S		0
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_M	0x00000fe0
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S	5
+
+/* Bits for AR_PHY_SGI_DELTA. */
+#define AR_PHY_SGI_DSC_EXP_M	0x0000000f
+#define AR_PHY_SGI_DSC_EXP_S	0
+#define AR_PHY_SGI_DSC_MAN_M	0x0007fff0
+#define AR_PHY_SGI_DSC_MAN_S	4
+
+/* Bits for AR_PHY_SETTLING. */
+#define AR_PHY_SETTLING_SWITCH_M	0x00003f80
+#define AR_PHY_SETTLING_SWITCH_S	7
+
+/* Bits for AR_PHY_RXGAIN(i). */
+#define AR_PHY_RXGAIN_TXRX_ATTEN_M	0x0003f000
+#define AR_PHY_RXGAIN_TXRX_ATTEN_S	12
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_M	0x007c0000
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_S	18
+
+/* Bits for AR_PHY_DESIRED_SZ. */
+#define AR_PHY_DESIRED_SZ_ADC_M		0x000000ff
+#define AR_PHY_DESIRED_SZ_ADC_S		0
+#define AR_PHY_DESIRED_SZ_PGA_M		0x0000ff00
+#define AR_PHY_DESIRED_SZ_PGA_S		8
+#define AR_PHY_DESIRED_SZ_TOT_DES_M	0x0ff00000
+#define AR_PHY_DESIRED_SZ_TOT_DES_S	20
+
+/* Bits for AR_PHY_FIND_SIG. */
+#define AR_PHY_FIND_SIG_RELSTEP_M	0x0000001f
+#define AR_PHY_FIND_SIG_RELSTEP_S	0
+#define AR_PHY_FIND_SIG_RELPWR_M	0x000007c0
+#define AR_PHY_FIND_SIG_RELPWR_S	6
+#define AR_PHY_FIND_SIG_FIRSTEP_M	0x0003f000
+#define AR_PHY_FIND_SIG_FIRSTEP_S	12
+#define AR_PHY_FIND_SIG_FIRPWR_M	0x03fc0000
+#define AR_PHY_FIND_SIG_FIRPWR_S	18
+
+/* Bits for AR_PHY_AGC. */
+#define AR_PHY_AGC_COARSE_PWR_CONST_M	0x0000007f
+#define AR_PHY_AGC_COARSE_PWR_CONST_S	0
+#define AR_PHY_AGC_COARSE_LOW_M		0x00007f80
+#define AR_PHY_AGC_COARSE_LOW_S		7
+#define AR_PHY_AGC_COARSE_HIGH_M	0x003f8000
+#define AR_PHY_AGC_COARSE_HIGH_S	15
+
+/* Bits for AR_PHY_EXT_ATTEN_CTL(i). */
+#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_M	0x0000001f
+#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S	0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_M	0x0000003f
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S	0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_M	0x00000fc0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S	6
+#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_M	0x00003c00
+#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S	10
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_M	0x0001f000
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S	12
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_M	0x003e0000
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S	17
+#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_M	0x00fc0000
+#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S	18
+
+/* Bits for AR_PHY_CCA(i). */
+#define AR_PHY_MAXCCA_PWR_M	0x000001ff
+#define AR_PHY_MAXCCA_PWR_S	0
+#define AR_PHY_MINCCA_PWR_M	0x1ff00000
+#define AR_PHY_MINCCA_PWR_S	20
+
+/* Bits for AR_PHY_EXT_CCA(i). */
+#define AR_PHY_EXT_MAXCCA_PWR_M		0x000001ff
+#define AR_PHY_EXT_MAXCCA_PWR_S		0
+#define AR_PHY_EXT_MINCCA_PWR_M		0x01ff0000
+#define AR_PHY_EXT_MINCCA_PWR_S		16
+
+/* Bits for AR_PHY_RESTART. */
+#define AR_PHY_RESTART_ENA	0x00000001
+#define AR_PHY_RESTART_DIV_GC_M	0x001c0000
+#define AR_PHY_RESTART_DIV_GC_S	18
+
+/* Bits for AR_PHY_CCK_DETECT. */
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M		0x0000003f
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S		0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M		0x00001fc0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S		6
+#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x00002000
+
+/* Bits for AR_PHY_DAG_CTRLCCK. */
+#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR	0x00000200
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M	0x0001fc00
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S	10
+
+/* Bits for AR_PHY_CCK_SPUR_MIT. */
+#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT	0x00000001
+#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_M	0x000001fe
+#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S	1
+#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_M	0x1ffffe00
+#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S	9
+#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_M	0x60000000
+#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S  29
+
+/* Bits for AR_PHY_GEN_CTRL. */
+#define AR_PHY_GC_TURBO_MODE		0x00000001
+#define AR_PHY_GC_TURBO_SHORT		0x00000002
+#define AR_PHY_GC_DYN2040_EN		0x00000004
+#define AR_PHY_GC_DYN2040_PRI_ONLY	0x00000008
+#define AR_PHY_GC_DYN2040_PRI_CH	0x00000010
+#define AR_PHY_GC_DYN2040_EXT_CH	0x00000020
+#define AR_PHY_GC_HT_EN			0x00000040
+#define AR_PHY_GC_SHORT_GI_40		0x00000080
+#define AR_PHY_GC_WALSH			0x00000100
+#define AR_PHY_GC_SINGLE_HT_LTF1	0x00000200
+#define AR_PHY_GC_GF_DETECT_EN		0x00000400
+#define AR_PHY_GC_ENABLE_DAC_FIFO	0x00000800
+
+/* Bits for AR_PHY_MODE. */
+#define AR_PHY_MODE_OFDM		0x00000000
+#define AR_PHY_MODE_CCK			0x00000001
+#define AR_PHY_MODE_DYNAMIC		0x00000004
+#define AR_PHY_MODE_HALF		0x00000020
+#define AR_PHY_MODE_QUARTER		0x00000040
+#define AR_PHY_MODE_DYN_CCK_DISABLE	0x00000100
+#define AR_PHY_MODE_SVD_HALF		0x00000200
+
+/* Bits for AR_PHY_ACTIVE. */
+#define AR_PHY_ACTIVE_DIS	0x00000000
+#define AR_PHY_ACTIVE_EN	0x00000001
+
+/* Bits for AR_PHY_SPUR_MASK_A. */
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_M	0x000003ff
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S	0
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_M	0x0001fc00
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S	10
+
+/* Bits for AR_PHY_SPECTRAL_SCAN. */
+#define AR_PHY_SPECTRAL_SCAN_ENABLE		0x00000001
+#define AR_PHY_SPECTRAL_SCAN_ACTIVE		0x00000002
+#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_M	0x000000f0
+#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S	4
+#define AR_PHY_SPECTRAL_SCAN_PERIOD_M		0x0000ff00
+#define AR_PHY_SPECTRAL_SCAN_PERIOD_S		8
+#define AR_PHY_SPECTRAL_SCAN_COUNT_M		0x00ff0000
+#define AR_PHY_SPECTRAL_SCAN_COUNT_S		16
+#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT	0x01000000
+
+/* Bits for AR_PHY_RFBUS_REQ. */
+#define AR_PHY_RFBUS_REQ_EN	0x00000001
+
+/* Bits for AR_PHY_RFBUS_GRANT. */
+#define AR_PHY_RFBUS_GRANT_EN	0x00000001
+
+/* Bits for AR_PHY_RIFS. */
+#define AR_PHY_RIFS_INIT_DELAY	0x3ff0000
+
+/* Bits for AR_PHY_RX_DELAY. */
+#define AR_PHY_RX_DELAY_DELAY_M	0x00003fff
+#define AR_PHY_RX_DELAY_DELAY_S	0
+
+/* Bits for AR_PHY_XPA_TIMING_CTL. */
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_M	0x000000ff
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S	0
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_M	0x0000ff00
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S	8
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_M	0x00ff0000
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S	16
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_M	0xff000000
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S	24
+
+/* Bits for AR_PHY_SWITCH_CHAIN. */
+#define AR_SWITCH_TABLE_ALL_M	0x00000fff
+#define AR_SWITCH_TABLE_ALL_S	0
+
+/* Bits for AR_PHY_SWITCH_COM. */
+#define AR_SWITCH_TABLE_COM_ALL_M	0x0000ffff
+#define AR_SWITCH_TABLE_COM_ALL_S	0
+
+/* Bits for AR_SWITCH_TABLE_COM_2. */
+#define AR_SWITCH_TABLE_COM_2_ALL_M	0x00ffffff
+#define AR_SWITCH_TABLE_COM_2_ALL_S	0
+
+/* Bits for AR_PHY_AGC_CONTROL. */
+#define AR_PHY_AGC_CONTROL_CAL			0x00000001
+#define AR_PHY_AGC_CONTROL_NF			0x00000002
+#define AR_PHY_AGC_CONTROL_YCOK_MAX_M		0x000003c0
+#define AR_PHY_AGC_CONTROL_YCOK_MAX_S		6
+#define AR_PHY_AGC_CONTROL_OFFSET_CAL		0x00000800
+#define AR_PHY_AGC_CONTROL_ENABLE_NF		0x00008000
+#define AR_PHY_AGC_CONTROL_FLTR_CAL		0x00010000
+#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF		0x00020000
+#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS	0x00040000
+#define AR_PHY_AGC_CONTROL_CLC_SUCCESS		0x00080000
+
+/* Bits for AR_PHY_CALMODE. */
+#define AR_PHY_CALMODE_IQ		0x00000000
+#define AR_PHY_CALMODE_ADC_GAIN		0x00000001
+#define AR_PHY_CALMODE_ADC_DC_PER	0x00000002
+#define AR_PHY_CALMODE_ADC_DC_INIT	0x00000003
+
+/* Bits for AR_PHY_FCAL_2_0. */
+#define AR_PHY_FCAL20_CAP_STATUS_0_M	0x01f00000
+#define AR_PHY_FCAL20_CAP_STATUS_0_S	20
+
+/* Bits for AR_PHY_SYNTH_CONTROL. */
+#define AR9380_BMODE	0x20000000
+
+/* Bits for AR_PHY_ANALOG_SWAP. */
+#define AR_PHY_SWAP_ALT_CHAIN	0x00000040
+
+/* Bits for AR_PHY_ADDAC_PARA_CTL. */
+#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC	0x00008000
+
+/* Bits for AR_PHY_TEST. */
+#define AR_PHY_TEST_RFSILENT_BB		0x00002000
+#define AR_PHY_TEST_BBB_OBS_SEL_M	0x00780000
+#define AR_PHY_TEST_BBB_OBS_SEL_S	19
+#define AR_PHY_TEST_RX_OBS_SEL_BIT5	0x00800000
+#define AR_PHY_TEST_CHAIN_SEL_M		0xc0000000
+#define AR_PHY_TEST_CHAIN_SEL_S		30
+
+/* Bits for AR_PHY_TEST_CTL_STATUS. */
+#define AR_PHY_TEST_CTL_TSTDAC_EN		0x00000001
+#define AR_PHY_TEST_CTL_TX_OBS_SEL_M		0x0000001c
+#define AR_PHY_TEST_CTL_TX_OBS_SEL_S		2
+#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_M	0x00000060
+#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S	5
+#define AR_PHY_TEST_CTL_TSTADC_EN		0x00000100
+#define AR_PHY_TEST_CTL_RX_OBS_SEL_M		0x00003c00
+#define AR_PHY_TEST_CTL_RX_OBS_SEL_S		10
+
+/* Bits for AR_PHY_CHAN_INFO_MEMORY. */
+#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK	0x00000001
+#define AR_PHY_CHAN_INFO_TAB_S2_READ		0x00000008
+
+/* Bits for AR_PHY_CHAN_INFO_GAIN_0. */
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK	0x00000fff
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT	320
+
+/* Bits for AR_PHY_CCK_TX_CTRL. */
+#define AR_PHY_CCK_TX_CTRL_JAPAN	0x00000010
+
+/* Bits for AR_PHY_PWRTX_MAX. */
+#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE	0x00000040
+
+/* Bits for AR_PHY_TPCRG5(i). */
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_M		0x0000000f
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S		0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_M	0x000003f0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S	4
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_M	0x0000fc00
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S	10
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_M	0x003f0000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S	16
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_M	0x0fc00000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S	22
+
+/* Bits for AR_PHY_TPC_6_B(i). */
+#define AR_PHY_TPC_6_ERROR_EST_MODE_M	0x03000000
+#define AR_PHY_TPC_6_ERROR_EST_MODE_S	24
+
+/* Bits for AR_PHY_TPC_11_B(i). */
+#define AR_PHY_TPC_OLPC_GAIN_DELTA_M		0x00ff0000
+#define AR_PHY_TPC_OLPC_GAIN_DELTA_S		16
+#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_M	0xff000000
+#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S	24
+
+/* Bits for AR_PHY_TPC_18. */
+#define AR_PHY_TPC_18_THERM_CAL_VALUE_M		0x000000ff
+#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 	0
+
+/* Bits for AR_PHY_TPC_19. */
+#define AR_PHY_TPC_19_ALPHA_THERM_M		0x000000ff
+#define AR_PHY_TPC_19_ALPHA_THERM_S		0
+
+/* Bits for AR_PHY_BB_THERM_ADC_1. */
+#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_M	0x000000ff
+#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S	0
+
+/* Bits for AR_PHY_TX_FORCED_GAIN. */
+#define AR_PHY_TXGAIN_FORCE			0x00000001
+#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_M	0x0000000e
+#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S	1
+#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_M	0x000003c0
+#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S	6
+#define AR_PHY_TXGAIN_FORCED_PADVGNRA_M		0x00003c00
+#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S		10
+#define AR_PHY_TXGAIN_FORCED_PADVGNRB_M		0x0003c000
+#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S		14
+#define AR_PHY_TXGAIN_FORCED_PADVGNRD_M		0x00c00000
+#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S		22
+
+/* Bits for AR_PHY_TX_IQCAL_CONTROL_1. */
+#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_M	0x01fc0000
+#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S	18
+
+/* Bits for AR_PHY_TX_IQCAL_START. */
+#define AR_PHY_TX_IQCAL_START_DO_CAL	0x00000001
+
+/* Bits for AR_PHY_TX_IQCAL_CORR_COEFF_01_B(i). */
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_M	0x00003fff
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S	0
+
+/* Bits for AR_PHY_TX_IQCAL_STATUS_B(i). */
+#define AR_PHY_TX_IQCAL_STATUS_FAILED	0x00000001
+
+/* Bits for AR_PHY_65NM_CH0_SYNTH4. */
+#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT	0x00000002
+
+/* Bits for AR_PHY_65NM_CH0_SYNTH7. */
+#define AR9380_FRACMODE		0x40000000
+#define AR9380_LOAD_SYNTH	0x80000000
+
+/* Bits for AR_PHY_65NM_CH0_RXTX4. */
+#define AR_PHY_65NM_CH0_RXTX4_THERM_ON  0x10000000
+
+/* Bits for AR_PHY_65NM_CH0_TOP. */
+#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_M	0x00000003
+#define AR_PHY_65NM_CH0_TOP_XPABIASLVL_S	0	/* XXX Linux says 8 */
+
+/* Bits for AR_PHY_65NM_CH0_THERM. */
+#define AR_PHY_65NM_CH0_THERM_SPARE_M		0x0000003f
+#define AR_PHY_65NM_CH0_THERM_SPARE_S		0
+#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_M	0x0000ff00
+#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S	8
+#define AR_PHY_65NM_CH0_THERM_START		0x20000000
+#define AR_PHY_65NM_CH0_THERM_LOCAL		0x80000000
+
+
+#define AR9003_RX_LP_QDEPTH	128
+#define AR9003_RX_HP_QDEPTH	16
+
+#define AR9003_NTXSTATUS	64
+
+/* Maximum number of DMA segments per Tx descriptor. */
+#define AR9003_MAX_SCATTER	4
+
+/*
+ * Tx DMA descriptor.
+ */
+struct ar_tx_desc {
+	uint32_t	ds_info;
+	uint32_t	ds_link;
+	struct {
+		uint32_t	ds_data;
+		uint32_t	ds_ctl;
+	} __packed	ds_segs[AR9003_MAX_SCATTER];
+	uint32_t	ds_ctl10;
+	uint32_t	ds_ctl11;
+	uint32_t	ds_ctl12;
+	uint32_t	ds_ctl13;
+	uint32_t	ds_ctl14;
+	uint32_t	ds_ctl15;
+	uint32_t	ds_ctl16;
+	uint32_t	ds_ctl17;
+	uint32_t	ds_ctl18;
+	uint32_t	ds_ctl19;
+	uint32_t	ds_ctl20;
+	uint32_t	ds_ctl21;
+	uint32_t	ds_ctl22;
+	/*
+	 * Padding to make Tx descriptors 128 bytes such that they will
+	 * not cross a 4KB boundary.
+	 */
+	uint32_t	pad[9];
+} __packed;
+
+/* Bits for ds_info. */
+#define AR_TXI_DESC_NDWORDS_M		0x000000ff
+#define AR_TXI_DESC_NDWORDS_S		0
+#define AR_TXI_QCU_NUM_M		0x00000f00
+#define AR_TXI_QCU_NUM_S		8
+#define AR_TXI_CTRL_STAT		0x00004000
+#define AR_TXI_DESC_TX			0x00008000
+#define AR_TXI_DESC_ID_M		0xffff0000
+#define AR_TXI_DESC_ID_S		16
+#define AR_VENDOR_ATHEROS		0x168c	/* NB: PCI_VENDOR_ATHEROS */
+
+/* Bits for ds_ctl. */
+#define AR_TXC_BUF_LEN_M		0x0fff0000
+#define AR_TXC_BUF_LEN_S		16
+
+/* Bits for ds_ctl10. */
+#define AR_TXC10_PTR_CHK_SUM_M		0x0000ffff
+#define AR_TXC10_PTR_CHK_SUM_S		0
+
+/* Bits for ds_ctl11. */
+#define AR_TXC11_FRAME_LEN_M		0x00000fff
+#define AR_TXC11_FRAME_LEN_S		0
+#define AR_TXC11_XMIT_POWER_M		0x003f0000
+#define AR_TXC11_XMIT_POWER_S		16
+#define AR_TXC11_RTS_ENABLE		0x00400000
+#define AR_TXC11_CLR_DEST_MASK		0x01000000
+#define AR_TXC11_DEST_IDX_VALID		0x40000000
+#define AR_TXC11_CTS_ENABLE		0x80000000
+
+/* Bits for ds_ctl12. */
+#define AR_TXC12_DEST_IDX_M		0x000fe000
+#define AR_TXC12_DEST_IDX_S		13
+#define AR_TXC12_FRAME_TYPE_M		0x00f00000
+#define AR_TXC12_FRAME_TYPE_S		20
+#define AR_FRAME_TYPE_NORMAL		0
+#define AR_FRAME_TYPE_ATIM		1
+#define AR_FRAME_TYPE_PSPOLL		2
+#define AR_FRAME_TYPE_BEACON		3
+#define AR_FRAME_TYPE_PROBE_RESP	4
+#define AR_TXC12_NO_ACK			0x01000000
+
+/* Bits for ds_ctl13. */
+#define AR_TXC13_BURST_DUR_M		0x00007fff
+#define AR_TXC13_BURST_DUR_S		0
+#define AR_TXC13_DUR_UPDATE_ENA		0x00008000
+#define AR_TXC13_XMIT_DATA_TRIES0_M	0x000f0000
+#define AR_TXC13_XMIT_DATA_TRIES0_S	16
+#define AR_TXC13_XMIT_DATA_TRIES1_M	0x00f00000
+#define AR_TXC13_XMIT_DATA_TRIES1_S	20
+#define AR_TXC13_XMIT_DATA_TRIES2_M	0x0f000000
+#define AR_TXC13_XMIT_DATA_TRIES2_S	24
+#define AR_TXC13_XMIT_DATA_TRIES3_M	0xf0000000
+#define AR_TXC13_XMIT_DATA_TRIES3_S	28
+
+/* Bits for ds_ctl14. */
+#define AR_TXC14_XMIT_RATE0_M		0x000000ff
+#define AR_TXC14_XMIT_RATE0_S		0
+#define AR_TXC14_XMIT_RATE1_M		0x0000ff00
+#define AR_TXC14_XMIT_RATE1_S		8
+#define AR_TXC14_XMIT_RATE2_M		0x00ff0000
+#define AR_TXC14_XMIT_RATE2_S		16
+#define AR_TXC14_XMIT_RATE3_M		0xff000000
+#define AR_TXC14_XMIT_RATE3_S		24
+
+/* Bits for ds_ctl15. */
+#define AR_TXC15_PACKET_DUR0_M		0x00007fff
+#define AR_TXC15_PACKET_DUR0_S		0
+#define AR_TXC15_RTSCTS_QUAL0		0x00008000
+#define AR_TXC15_PACKET_DUR1_M		0x7fff0000
+#define AR_TXC15_PACKET_DUR1_S		16
+#define AR_TXC15_RTSCTS_QUAL1		0x80000000
+/* Shortcut. */
+#define AR_TXC15_RTSCTS_QUAL01	\
+	(AR_TXC15_RTSCTS_QUAL0 | AR_TXC15_RTSCTS_QUAL1)
+
+/* Bits for ds_ctl16. */
+#define AR_TXC16_PACKET_DUR2_M		0x00007fff
+#define AR_TXC16_PACKET_DUR2_S		0
+#define AR_TXC16_RTSCTS_QUAL2		0x00008000
+#define AR_TXC16_PACKET_DUR3_M		0x7fff0000
+#define AR_TXC16_PACKET_DUR3_S		16
+#define AR_TXC16_RTSCTS_QUAL3		0x80000000
+/* Shortcut. */
+#define AR_TXC16_RTSCTS_QUAL23	\
+	(AR_TXC16_RTSCTS_QUAL2 | AR_TXC16_RTSCTS_QUAL3)
+
+/* Bits for ds_ctl17. */
+#define AR_TXC17_ENCR_TYPE_M		0x0c000000
+#define AR_TXC17_ENCR_TYPE_S		26
+#define AR_ENCR_TYPE_CLEAR		0
+#define AR_ENCR_TYPE_WEP		1
+#define AR_ENCR_TYPE_AES		2
+#define AR_ENCR_TYPE_TKIP		3
+
+/* Bits for ds_ctl18. */
+#define AR_TXC18_2040_0			0x00000001
+#define AR_TXC18_GI0			0x00000002
+#define AR_TXC18_CHAIN_SEL0_M		0x0000001c
+#define AR_TXC18_CHAIN_SEL0_S		2
+#define AR_TXC18_2040_1			0x00000020
+#define AR_TXC18_GI1			0x00000040
+#define AR_TXC18_CHAIN_SEL1_M		0x00000380
+#define AR_TXC18_CHAIN_SEL1_S		7
+#define AR_TXC18_2040_2			0x00000400
+#define AR_TXC18_GI2			0x00000800
+#define AR_TXC18_CHAIN_SEL2_M		0x00007000
+#define AR_TXC18_CHAIN_SEL2_S		12
+#define AR_TXC18_2040_3			0x00008000
+#define AR_TXC18_GI3			0x00010000
+#define AR_TXC18_CHAIN_SEL3_M		0x000e0000
+#define AR_TXC18_CHAIN_SEL3_S		17
+#define AR_TXC18_RTSCTS_RATE_M		0x0ff00000
+#define AR_TXC18_RTSCTS_RATE_S		20
+/* Shortcuts. */
+#define AR_TXC18_2040_0123	\
+	(AR_TXC18_2040_0 | AR_TXC18_2040_1 | AR_TXC18_2040_2 | AR_TXC18_2040_3)
+#define AR_TXC18_GI0123		\
+	(AR_TXC18_GI0 | AR_TXC18_GI1 | AR_TXC18_GI2 | AR_TXC18_GI3)
+
+/* Bits for ds_ctl19. */
+#define AR_TXC19_NOT_SOUNDING		0x20000000
+
+
+/*
+ * Tx status DMA descriptor.
+ */
+struct ar_tx_status {
+	uint32_t	ds_info;
+	uint32_t	ds_status1;
+	uint32_t	ds_status2;
+	uint32_t	ds_status3;
+	uint32_t	ds_status4;
+	uint32_t	ds_status5;
+	uint32_t	ds_status6;
+	uint32_t	ds_status7;
+	uint32_t	ds_status8;
+} __packed;
+
+/* Bits for ds_status3. */
+#define AR_TXS3_EXCESSIVE_RETRIES	0x00000002
+#define AR_TXS3_FIFO_UNDERRUN		0x00000004
+#define AR_TXS3_RTS_FAIL_CNT_M		0x000000f0
+#define AR_TXS3_RTS_FAIL_CNT_S		4
+#define AR_TXS3_DATA_FAIL_CNT_M		0x00000f00
+#define AR_TXS3_DATA_FAIL_CNT_S		8
+#define AR_TXS3_TX_DELIM_UNDERRUN	0x00010000
+#define AR_TXS3_TX_DATA_UNDERRUN	0x00020000
+/* Shortcut. */
+#define AR_TXS3_UNDERRUN		\
+	(AR_TXS3_FIFO_UNDERRUN |	\
+	 AR_TXS3_TX_DELIM_UNDERRUN |	\
+	 AR_TXS3_TX_DATA_UNDERRUN)
+
+/* Bits for ds_status8. */
+#define AR_TXS8_DONE			0x00000001
+#define AR_TXS8_FINAL_IDX_M		0x00600000
+#define AR_TXS8_FINAL_IDX_S		21
+
+/*
+ * Rx status DMA descriptor.
+ */
+struct ar_rx_status {
+	uint32_t	ds_info;
+	uint32_t	ds_status1;
+	uint32_t	ds_status2;
+	uint32_t	ds_status3;
+	uint32_t	ds_status4;
+	uint32_t	ds_status5;
+	uint32_t	ds_status6;
+	uint32_t	ds_status7;
+	uint32_t	ds_status8;
+	uint32_t	ds_status9;
+	uint32_t	ds_status10;
+	uint32_t	ds_status11;
+} __packed;
+
+/* Bits for ds_info. */
+#define AR_RXI_CTRL_STAT		0x00004000
+#define AR_RXI_DESC_TX			0x00008000
+#define AR_RXI_DESC_ID_M		0xffff0000
+#define AR_RXI_DESC_ID_S		16
+
+/* Bits for ds_status1. */
+#define AR_RXS1_DONE			0x00000001
+#define AR_RXS1_RATE_M			0x000003fc
+#define AR_RXS1_RATE_S			2
+
+/* Bits for ds_status2. */
+#define AR_RXS2_DATA_LEN_M		0x00000fff
+#define AR_RXS2_DATA_LEN_S		0
+
+/* Bits for ds_status4. */
+#define AR_RXS4_GI			0x00000001
+#define AR_RXS4_ANTENNA_M		0xffffff00
+#define AR_RXS4_ANTENNA_S		8
+
+/* Bits for ds_status5. */
+#define AR_RXS5_RSSI_COMBINED_M		0xff000000
+#define AR_RXS5_RSSI_COMBINED_S		24
+
+/* Bits for ds_status11. */
+#define AR_RXS11_FRAME_OK		0x00000002
+#define AR_RXS11_CRC_ERR		0x00000004
+#define AR_RXS11_DECRYPT_CRC_ERR	0x00000008
+#define AR_RXS11_PHY_ERR		0x00000010
+#define AR_RXS11_PHY_ERR_CODE_M		0x0000ff00
+#define AR_RXS11_PHY_ERR_CODE_S		8
+#define AR_RXS11_MICHAEL_ERR		0x00000020
+
+/*
+ * AR9003 family common ROM structures.
+ */
+#define AR_EEP_COMPRESS_NONE	0
+#define AR_EEP_COMPRESS_LZMA	1
+#define AR_EEP_COMPRESS_PAIRS	2
+#define AR_EEP_COMPRESS_BLOCK	3
+
+struct ar_cal_target_power_leg {
+	uint8_t	tPow2x[4];
+} __packed;
+
+struct ar_cal_target_power_ht {
+	uint8_t	tPow2x[14];
+} __packed;
diff --git a/sys/dev/ic/ar9280.c b/sys/dev/ic/ar9280.c
index 138ad789e72..bca481545a5 100644
--- a/sys/dev/ic/ar9280.c
+++ b/sys/dev/ic/ar9280.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9280.c,v 1.4 2010/04/20 22:05:41 tedu Exp $	*/
+/*	$OpenBSD: ar9280.c,v 1.5 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -62,23 +62,42 @@
 #include <dev/ic/athnreg.h>
 #include <dev/ic/athnvar.h>
 
+#include <dev/ic/ar5008reg.h>
 #include <dev/ic/ar5416reg.h>	/* We share the ROM layout. */
 #include <dev/ic/ar9280reg.h>
 
 int	ar9280_attach(struct athn_softc *);
 void	ar9280_setup(struct athn_softc *);
+int	ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
 void	ar9280_init_from_rom(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
+void	ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9280_2_0_olpc_get_pdadcs(struct athn_softc *,
+	    struct ieee80211_channel *, int, uint8_t *, uint8_t *, uint8_t *);
 void	ar9280_reset_rx_gain(struct athn_softc *, struct ieee80211_channel *);
 void	ar9280_reset_tx_gain(struct athn_softc *, struct ieee80211_channel *);
 void	ar9280_2_0_olpc_init(struct athn_softc *);
 void	ar9280_2_0_olpc_temp_compensation(struct athn_softc *);
 
+/* Extern functions. */
+uint8_t	athn_chan2fbin(struct ieee80211_channel *);
+void	athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
+int	ar5008_attach(struct athn_softc *);
+void	ar5008_set_viterbi_mask(struct athn_softc *, int);
+void	ar5416_swap_rom(struct athn_softc *);
+void	ar5416_set_txpower(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+const struct ar_spur_chan *
+	ar5416_get_spur_chans(struct athn_softc *, int);
+
+
 int
 ar9280_attach(struct athn_softc *sc)
 {
 	sc->eep_base = AR5416_EEP_START_LOC;
-	sc->eep_size = sizeof (struct ar5416_eeprom);
+	sc->eep_size = sizeof(struct ar5416_eeprom);
 	sc->def_nf = AR9280_PHY_CCA_MAX_GOOD_VALUE;
 	sc->ngpiopins = 10;
 	sc->led_pin = 1;
@@ -99,7 +118,8 @@ ar9280_attach(struct athn_softc *sc)
 		sc->serdes = ar9280_2_0_serdes;
 	else
 		sc->serdes = ar9280_1_0_serdes;
-	return (0);
+
+	return (ar5008_attach(sc));
 }
 
 void
@@ -114,6 +134,12 @@ ar9280_setup(struct athn_softc *sc)
 	    eep->baseEepHeader.openLoopPwrCntl)
 		sc->flags |= ATHN_FLAG_OLPC;
 
+	/* Determine if fast PLL clock is supported. */
+	if (AR_SREV_9280_20(sc) &&
+	    (sc->eep_rev <= AR_EEP_MINOR_VER_16 ||
+	     eep->baseEepHeader.fastClk5g))
+		sc->flags |= ATHN_FLAG_FAST_PLL_CLOCK;
+
 	if (AR_SREV_9280_20(sc)) {
 		/* Check if we have a valid rxGainType field in ROM. */
 		if (sc->eep_rev >= AR_EEP_MINOR_VER_17) {
@@ -157,7 +183,7 @@ ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
 		phy |= AR9280_BMODE | AR9280_FRACMODE;
 
 		if (AR_SREV_9287_11_OR_LATER(sc)) {
-			/* XXX Magic from the Linux driver. */
+			/* NB: Magic values from the Linux driver. */
 			if (freq == 2484) {	/* Channel 14. */
 				/* Japanese regulatory requirements. */
 				AR_WRITE(sc, AR_PHY(637), 0x00000000);
@@ -429,12 +455,12 @@ ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 {
 	const struct ar_spur_chan *spurchans;
 	int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
-	int spur_off, bound, i;
+	int spur_off, range, i;
 
 	/* NB: Always clear. */
 	AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
 
-	bound = (extc != NULL) ? 19 : 10;
+	range = (extc != NULL) ? 19 : 10;
 
 	spurchans = sc->ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
 	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
@@ -448,7 +474,7 @@ ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 		else
 			spur += AR_BASE_FREQ_5GHZ;
 		spur -= c->ic_freq;
-		if (abs(spur) < bound)
+		if (abs(spur) < range)
 			break;
 	}
 	if (i == AR_EEPROM_MODAL_SPURS)
@@ -496,7 +522,7 @@ ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
 	    SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
 
 	bin = spur * 320;
-	athn_set_viterbi_mask(sc, bin);
+	ar5008_set_viterbi_mask(sc, bin);
 }
 
 void
diff --git a/sys/dev/ic/ar9285.c b/sys/dev/ic/ar9285.c
index f9442fa8bac..9c52217f513 100644
--- a/sys/dev/ic/ar9285.c
+++ b/sys/dev/ic/ar9285.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9285.c,v 1.7 2010/04/20 22:05:43 tedu Exp $	*/
+/*	$OpenBSD: ar9285.c,v 1.8 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009-2010 Damien Bergamini <damien.bergamini@free.fr>
@@ -62,6 +62,7 @@
 #include <dev/ic/athnreg.h>
 #include <dev/ic/athnvar.h>
 
+#include <dev/ic/ar5008reg.h>
 #include <dev/ic/ar9280reg.h>
 #include <dev/ic/ar9285reg.h>
 
@@ -74,6 +75,8 @@ void	ar9285_init_from_rom(struct athn_softc *, struct ieee80211_channel *,
 void	ar9285_pa_calib(struct athn_softc *);
 int	ar9285_1_2_cl_cal(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
+int	ar9285_1_2_init_calib(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
 void	ar9285_get_pdadcs(struct athn_softc *, struct ieee80211_channel *,
 	    int, uint8_t, uint8_t *, uint8_t *);
 void	ar9285_set_power_calib(struct athn_softc *,
@@ -81,11 +84,28 @@ void	ar9285_set_power_calib(struct athn_softc *,
 void	ar9285_set_txpower(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
 
+/* Extern functions. */
+uint8_t	athn_chan2fbin(struct ieee80211_channel *);
+void	athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
+int	ar5008_attach(struct athn_softc *);
+void	ar5008_write_txpower(struct athn_softc *, int16_t power[]);
+void	ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *,
+	    struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *);
+void	ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]);
+void	ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]);
+int	ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+
+
 int
 ar9285_attach(struct athn_softc *sc)
 {
 	sc->eep_base = AR9285_EEP_START_LOC;
-	sc->eep_size = sizeof (struct ar9285_eeprom);
+	sc->eep_size = sizeof(struct ar9285_eeprom);
 	sc->def_nf = AR9285_PHY_CCA_MAX_GOOD_VALUE;
 	sc->ngpiopins = 12;
 	sc->led_pin = 1;
@@ -103,7 +123,8 @@ ar9285_attach(struct athn_softc *sc)
 	else
 		sc->ini = &ar9285_1_0_ini;
 	sc->serdes = ar9280_2_0_serdes;
-	return (0);
+
+	return (ar5008_attach(sc));
 }
 
 void
@@ -153,7 +174,7 @@ ar9285_get_spur_chans(struct athn_softc *sc, int is2ghz)
 	const struct ar9285_eeprom *eep = sc->eep;
 
 	KASSERT(is2ghz);
-	return eep->modalHeader.spurChans;
+	return (eep->modalHeader.spurChans);
 }
 
 void
@@ -214,7 +235,7 @@ ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
 	AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
 
 	if (AR_SREV_9285_11(sc))
-		AR_WRITE(sc, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT | 0x14);
+		AR_WRITE(sc, AR9285_AN_TOP4, AR9285_AN_TOP4_UNLOCKED);
 
 	if (modal->version >= 3) {
 		/* Setup antenna diversity from ROM. */
@@ -378,8 +399,7 @@ ar9285_pa_calib(struct athn_softc *sc)
 		return;
 
 	if (AR_SREV_9285_11(sc)) {
-		/* XXX magic 0x14. */
-		AR_WRITE(sc, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT | 0x14);
+		AR_WRITE(sc, AR9285_AN_TOP4, AR9285_AN_TOP4_UNLOCKED);
 		DELAY(10);
 	}
 
@@ -585,7 +605,7 @@ ar9285_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
 		hipier.pwr[i] = pierdata[lo].pwrPdg[i];
 		hipier.vpd[i] = pierdata[lo].vpdPdg[i];
 	}
-	athn_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
+	ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
 	    AR9285_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
 }
 
@@ -607,7 +627,7 @@ ar9285_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
 		overlap = eep->modalHeader.pdGainOverlap;
 
 	nxpdgains = 0;
-	memset(xpdgains, 0, sizeof xpdgains);
+	memset(xpdgains, 0, sizeof(xpdgains));
 	for (i = AR9285_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
 		if (nxpdgains >= AR9285_NUM_PD_GAINS)
 			break;
@@ -663,36 +683,37 @@ ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	/* XXX */
 
 	/* Get CCK target powers. */
-	athn_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
+	ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
 	    AR9285_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
 
 	/* Get OFDM target powers. */
-	athn_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
+	ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
 	    AR9285_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
 
 #ifndef IEEE80211_NO_HT
 	/* Get HT-20 target powers. */
-	athn_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
+	ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
 	    AR9285_NUM_2G_20_TARGET_POWERS, tpow_ht20);
 
 	if (extc != NULL) {
 		/* Get HT-40 target powers. */
-		athn_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+		ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
 		    eep->calTargetPower2GHT40, AR9285_NUM_2G_40_TARGET_POWERS,
 		    tpow_ht40);
 
 		/* Get secondary channel CCK target powers. */
-		athn_get_lg_tpow(sc, extc, AR_CTL_11B, eep->calTargetPowerCck,
-		    AR9285_NUM_2G_CCK_TARGET_POWERS, tpow_cck_ext);
+		ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
+		    eep->calTargetPowerCck, AR9285_NUM_2G_CCK_TARGET_POWERS,
+		    tpow_cck_ext);
 
 		/* Get secondary channel OFDM target powers. */
-		athn_get_lg_tpow(sc, extc, AR_CTL_11G,
+		ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
 		    eep->calTargetPower2G, AR9285_NUM_2G_20_TARGET_POWERS,
 		    tpow_ofdm_ext);
 	}
 #endif
 
-	memset(power, 0, sizeof power);
+	memset(power, 0, sizeof(power));
 	/* Shuffle target powers accross transmit rates. */
 	power[ATHN_POWER_OFDM6   ] =
 	power[ATHN_POWER_OFDM9   ] =
@@ -735,5 +756,5 @@ ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 
 	/* Commit transmit power values to hardware. */
-	athn_write_txpower(sc, power);
+	ar5008_write_txpower(sc, power);
 }
diff --git a/sys/dev/ic/ar9285reg.h b/sys/dev/ic/ar9285reg.h
index 3eac738bc58..bfbd9052eec 100644
--- a/sys/dev/ic/ar9285reg.h
+++ b/sys/dev/ic/ar9285reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9285reg.h,v 1.2 2010/04/07 16:19:33 damien Exp $	*/
+/*	$OpenBSD: ar9285reg.h,v 1.3 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -42,47 +42,47 @@
 
 /* Bits for AR9285_AN_RF2G1. */
 #define AR9285_AN_RF2G1_ENPACAL		0x00000800
-#define AR9285_AN_RF2G1_PDPADRV1	0x02000000
-#define AR9285_AN_RF2G1_PDPADRV2	0x01000000
 #define AR9285_AN_RF2G1_PDPAOUT		0x00800000
+#define AR9285_AN_RF2G1_PDPADRV2	0x01000000
+#define AR9285_AN_RF2G1_PDPADRV1	0x02000000
 
 /* Bits for AR9285_AN_RF2G2. */
 #define AR9285_AN_RF2G2_OFFCAL	0x00001000
 
 /* Bits for AR9285_AN_RF2G3. */
-#define AR9285_AN_RF2G3_PDVCCOMP	0x02000000
-#define AR9285_AN_RF2G3_OB_0_M		0x00e00000
-#define AR9285_AN_RF2G3_OB_0_S		21
-#define AR9285_AN_RF2G3_OB_1_M		0x001c0000
-#define AR9285_AN_RF2G3_OB_1_S		18
-#define AR9285_AN_RF2G3_OB_2_M		0x00038000
-#define AR9285_AN_RF2G3_OB_2_S		15
-#define AR9285_AN_RF2G3_OB_3_M		0x00007000
-#define AR9285_AN_RF2G3_OB_3_S		12
-#define AR9285_AN_RF2G3_OB_4_M		0x00000e00
-#define AR9285_AN_RF2G3_OB_4_S		9
-#define AR9285_AN_RF2G3_DB1_0_M		0x000001c0
-#define AR9285_AN_RF2G3_DB1_0_S		6
-#define AR9285_AN_RF2G3_DB1_1_M		0x00000038
-#define AR9285_AN_RF2G3_DB1_1_S		3
 #define AR9285_AN_RF2G3_DB1_2_M		0x00000007
 #define AR9285_AN_RF2G3_DB1_2_S		0
+#define AR9285_AN_RF2G3_DB1_1_M		0x00000038
+#define AR9285_AN_RF2G3_DB1_1_S		3
+#define AR9285_AN_RF2G3_DB1_0_M		0x000001c0
+#define AR9285_AN_RF2G3_DB1_0_S		6
+#define AR9285_AN_RF2G3_OB_4_M		0x00000e00
+#define AR9285_AN_RF2G3_OB_4_S		9
+#define AR9285_AN_RF2G3_OB_3_M		0x00007000
+#define AR9285_AN_RF2G3_OB_3_S		12
+#define AR9285_AN_RF2G3_OB_2_M		0x00038000
+#define AR9285_AN_RF2G3_OB_2_S		15
+#define AR9285_AN_RF2G3_OB_1_M		0x001c0000
+#define AR9285_AN_RF2G3_OB_1_S		18
+#define AR9285_AN_RF2G3_OB_0_M		0x00e00000
+#define AR9285_AN_RF2G3_OB_0_S		21
+#define AR9285_AN_RF2G3_PDVCCOMP	0x02000000
 
 /* Bits for AR9285_AN_RF2G4. */
-#define AR9285_AN_RF2G4_DB1_3_M		0xe0000000
-#define AR9285_AN_RF2G4_DB1_3_S		29
-#define AR9285_AN_RF2G4_DB1_4_M		0x1c000000
-#define AR9285_AN_RF2G4_DB1_4_S		26
-#define AR9285_AN_RF2G4_DB2_0_M		0x03800000
-#define AR9285_AN_RF2G4_DB2_0_S		23
-#define AR9285_AN_RF2G4_DB2_1_M		0x00700000
-#define AR9285_AN_RF2G4_DB2_1_S		20
-#define AR9285_AN_RF2G4_DB2_2_M		0x000e0000
-#define AR9285_AN_RF2G4_DB2_2_S		17
-#define AR9285_AN_RF2G4_DB2_3_M		0x0001c000
-#define AR9285_AN_RF2G4_DB2_3_S		14
 #define AR9285_AN_RF2G4_DB2_4_M		0x00003800
 #define AR9285_AN_RF2G4_DB2_4_S		11
+#define AR9285_AN_RF2G4_DB2_3_M		0x0001c000
+#define AR9285_AN_RF2G4_DB2_3_S		14
+#define AR9285_AN_RF2G4_DB2_2_M		0x000e0000
+#define AR9285_AN_RF2G4_DB2_2_S		17
+#define AR9285_AN_RF2G4_DB2_1_M		0x00700000
+#define AR9285_AN_RF2G4_DB2_1_S		20
+#define AR9285_AN_RF2G4_DB2_0_M		0x03800000
+#define AR9285_AN_RF2G4_DB2_0_S		23
+#define AR9285_AN_RF2G4_DB1_4_M		0x1c000000
+#define AR9285_AN_RF2G4_DB1_4_S		26
+#define AR9285_AN_RF2G4_DB1_3_M		0xe0000000
+#define AR9285_AN_RF2G4_DB1_3_S		29
 
 /* Bits for AR9285_AN_RF2G5. */
 #define AR9285_AN_RF2G5_IC50TX_M	0x00000700
@@ -118,7 +118,8 @@
 #define AR9285_AN_TOP3_PWDDAC		0x00800000
 
 /* Bits for AR9285_AN_TOP4. */
-#define AR9285_AN_TOP4_DEFAULT		0x10142c00
+#define AR9285_AN_TOP4_DEFAULT		0x10142c00	/* XXX magic */
+#define AR9285_AN_TOP4_UNLOCKED		0x10142c14	/* XXX magic */
 
 /* Bits for AR_PHY_MULTICHAIN_GAIN_CTL. */
 #define AR9285_PHY_ANT_DIV_CTL_ALL_M		0x7f000000
@@ -127,18 +128,12 @@
 #define AR9285_PHY_ANT_DIV_CTL_S		24
 #define AR9285_PHY_ANT_DIV_ALT_LNACONF_M	0x06000000
 #define AR9285_PHY_ANT_DIV_ALT_LNACONF_S	25
-#define AR9285_PHY_ANT_DIV_LNA1			2
-#define AR9285_PHY_ANT_DIV_LNA2			1
 #define AR9285_PHY_ANT_DIV_MAIN_LNACONF_M	0x18000000
 #define AR9285_PHY_ANT_DIV_MAIN_LNACONF_S	27
-#define AR9285_PHY_ANT_DIV_ALT_GAINTB_M	0x20000000
+#define AR9285_PHY_ANT_DIV_ALT_GAINTB_M		0x20000000
 #define AR9285_PHY_ANT_DIV_ALT_GAINTB_S		29
-#define AR9285_PHY_ANT_DIV_GAINTB_0		0
-#define AR9285_PHY_ANT_DIV_GAINTB_1		1
 #define AR9285_PHY_ANT_DIV_MAIN_GAINTB_M	0x40000000
 #define AR9285_PHY_ANT_DIV_MAIN_GAINTB_S	30
-#define AR9285_PHY_ANT_DIV_LNA1_PLUS_LNA2	3
-#define AR9285_PHY_ANT_DIV_LNA1_MINUS_LNA2	0
 
 /*
  * ROM layout used by AR9285 (single-stream, 2GHz only).
diff --git a/sys/dev/ic/ar9287.c b/sys/dev/ic/ar9287.c
index 86943b898e9..21a6adfe315 100644
--- a/sys/dev/ic/ar9287.c
+++ b/sys/dev/ic/ar9287.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9287.c,v 1.9 2010/04/23 16:05:39 damien Exp $	*/
+/*	$OpenBSD: ar9287.c,v 1.10 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -62,6 +62,7 @@
 #include <dev/ic/athnreg.h>
 #include <dev/ic/athnvar.h>
 
+#include <dev/ic/ar5008reg.h>
 #include <dev/ic/ar9280reg.h>
 #include <dev/ic/ar9287reg.h>
 
@@ -81,12 +82,31 @@ void	ar9287_set_txpower(struct athn_softc *, struct ieee80211_channel *,
 	    struct ieee80211_channel *);
 void	ar9287_olpc_init(struct athn_softc *);
 void	ar9287_olpc_temp_compensation(struct athn_softc *);
+void	ar9287_1_2_enable_async_fifo(struct athn_softc *);
+void	ar9287_1_2_setup_async_fifo(struct athn_softc *);
+
+/* Extern functions. */
+uint8_t	athn_chan2fbin(struct ieee80211_channel *);
+void	athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
+int	ar5008_attach(struct athn_softc *);
+void	ar5008_write_txpower(struct athn_softc *, int16_t power[]);
+void	ar5008_get_pdadcs(struct athn_softc *, uint8_t, struct athn_pier *,
+	    struct athn_pier *, int, int, uint8_t, uint8_t *, uint8_t *);
+void	ar5008_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_leg *, int, uint8_t[]);
+void	ar5008_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const struct ar_cal_target_power_ht *, int, uint8_t[]);
+int	ar9280_set_synth(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9280_spur_mitigate(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+
 
 int
 ar9287_attach(struct athn_softc *sc)
 {
 	sc->eep_base = AR9287_EEP_START_LOC;
-	sc->eep_size = sizeof (struct ar9287_eeprom);
+	sc->eep_size = sizeof(struct ar9287_eeprom);
 	sc->def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE;
 	sc->ngpiopins = 11;
 	sc->led_pin = 8;
@@ -104,7 +124,8 @@ ar9287_attach(struct athn_softc *sc)
 	else
 		sc->ini = &ar9287_1_0_ini;
 	sc->serdes = ar9280_2_0_serdes;
-	return (0);
+
+	return (ar5008_attach(sc));
 }
 
 void
@@ -150,7 +171,7 @@ ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz)
 	const struct ar9287_eeprom *eep = sc->eep;
 
 	KASSERT(is2ghz);
-	return eep->modalHeader.spurChans;
+	return (eep->modalHeader.spurChans);
 }
 
 void
@@ -284,7 +305,7 @@ ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
 		hipier.pwr[i] = pierdata[lo].pwrPdg[i];
 		hipier.vpd[i] = pierdata[lo].vpdPdg[i];
 	}
-	athn_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
+	ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
 	    AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
 
 	delta = (eep->baseEepHeader.pwrTableOffset -
@@ -352,7 +373,7 @@ ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
 	}
 
 	nxpdgains = 0;
-	memset(xpdgains, 0, sizeof xpdgains);
+	memset(xpdgains, 0, sizeof(xpdgains));
 	for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
 		if (nxpdgains >= AR9287_NUM_PD_GAINS)
 			break;		/* Can't happen. */
@@ -450,35 +471,37 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 		pwr = 0;
 
 	/* Get CCK target powers. */
-	athn_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
+	ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
 	    AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
 
 	/* Get OFDM target powers. */
-	athn_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
+	ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
 	    AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
 
 #ifndef IEEE80211_NO_HT
 	/* Get HT-20 target powers. */
-	athn_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
+	ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
 	    AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20);
 
 	if (extc != NULL) {
 		/* Get HT-40 target powers. */
-		athn_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+		ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
 		    eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS,
 		    tpow_ht40);
 
 		/* Get secondary channel CCK target powers. */
-		athn_get_lg_tpow(sc, extc, AR_CTL_11B, eep->calTargetPowerCck,
-		    AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck_ext);
+		ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
+		    eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS,
+		    tpow_cck_ext);
 
 		/* Get secondary channel OFDM target powers. */
-		athn_get_lg_tpow(sc, extc, AR_CTL_11G, eep->calTargetPower2G,
-		    AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm_ext);
+		ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
+		    eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS,
+		    tpow_ofdm_ext);
 	}
 #endif
 
-	memset(power, 0, sizeof power);
+	memset(power, 0, sizeof(power));
 	/* Shuffle target powers accross transmit rates. */
 	power[ATHN_POWER_OFDM6   ] =
 	power[ATHN_POWER_OFDM9   ] =
@@ -521,7 +544,7 @@ ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
 			power[i] = AR_MAX_RATE_POWER;
 	}
 	/* Commit transmit power values to hardware. */
-	athn_write_txpower(sc, power);
+	ar5008_write_txpower(sc, power);
 }
 
 void
diff --git a/sys/dev/ic/ar9287reg.h b/sys/dev/ic/ar9287reg.h
index 19d1b8df617..6ff387e1cfb 100644
--- a/sys/dev/ic/ar9287reg.h
+++ b/sys/dev/ic/ar9287reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar9287reg.h,v 1.1 2009/11/14 16:55:11 damien Exp $	*/
+/*	$OpenBSD: ar9287reg.h,v 1.2 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -30,18 +30,18 @@
 #define AR9287_AN_TOP2			0x78b4
 
 /* Bits for AR9287_AN_RF2G3_CH[01]. */
-#define AR9287_AN_RF2G3_DB1_M		0xe0000000
-#define AR9287_AN_RF2G3_DB1_S		29
-#define AR9287_AN_RF2G3_DB2_M		0x1c000000
-#define AR9287_AN_RF2G3_DB2_S		26
-#define AR9287_AN_RF2G3_OB_CCK_M	0x03800000
-#define AR9287_AN_RF2G3_OB_CCK_S	23
-#define AR9287_AN_RF2G3_OB_PSK_M	0x00700000
-#define AR9287_AN_RF2G3_OB_PSK_S	20
-#define AR9287_AN_RF2G3_OB_QAM_M	0x000e0000
-#define AR9287_AN_RF2G3_OB_QAM_S	17
 #define AR9287_AN_RF2G3_OB_PAL_OFF_M	0x0001c000
 #define AR9287_AN_RF2G3_OB_PAL_OFF_S	14
+#define AR9287_AN_RF2G3_OB_QAM_M	0x000e0000
+#define AR9287_AN_RF2G3_OB_QAM_S	17
+#define AR9287_AN_RF2G3_OB_PSK_M	0x00700000
+#define AR9287_AN_RF2G3_OB_PSK_S	20
+#define AR9287_AN_RF2G3_OB_CCK_M	0x03800000
+#define AR9287_AN_RF2G3_OB_CCK_S	23
+#define AR9287_AN_RF2G3_DB2_M		0x1c000000
+#define AR9287_AN_RF2G3_DB2_S		26
+#define AR9287_AN_RF2G3_DB1_M		0xe0000000
+#define AR9287_AN_RF2G3_DB1_S		29
 
 /* Bits for AR9287_AN_TXPC0. */
 #define AR9287_AN_TXPC0_TXPCMODE_M		0x0000c000
diff --git a/sys/dev/ic/ar9380.c b/sys/dev/ic/ar9380.c
new file mode 100644
index 00000000000..d1f7f293187
--- /dev/null
+++ b/sys/dev/ic/ar9380.c
@@ -0,0 +1,667 @@
+/*	$OpenBSD: ar9380.c,v 1.1 2010/05/10 17:44:21 damien Exp $	*/
+
+/*-
+ * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for Atheros 802.11a/g/n chipsets.
+ * Routines for AR9380 and AR9381 chipsets.
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/endian.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/in_var.h>
+#include <netinet/if_ether.h>
+
+#include <net80211/ieee80211_var.h>
+#include <net80211/ieee80211_amrr.h>
+#include <net80211/ieee80211_radiotap.h>
+
+#include <dev/ic/athnreg.h>
+#include <dev/ic/athnvar.h>
+
+#include <dev/ic/ar9003reg.h>
+#include <dev/ic/ar9380reg.h>
+
+int	ar9380_attach(struct athn_softc *);
+void	ar9380_setup(struct athn_softc *);
+void	ar9380_swap_rom(struct athn_softc *);
+int	ar9380_set_synth(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9380_init_from_rom(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9380_spur_mitigate_cck(struct athn_softc *,
+	    struct ieee80211_channel *, struct ieee80211_channel *);
+void	ar9380_spur_mitigate_ofdm(struct athn_softc *,
+	    struct ieee80211_channel *, struct ieee80211_channel *);
+void	ar9380_spur_mitigate(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9380_set_txpower(struct athn_softc *, struct ieee80211_channel *,
+	    struct ieee80211_channel *);
+void	ar9380_get_correction(struct athn_softc *, struct ieee80211_channel *,
+	    int, int *, int *);
+void	ar9380_set_correction(struct athn_softc *, struct ieee80211_channel *);
+
+/* Extern functions. */
+int	athn_interpolate(int, int, int, int, int);
+uint8_t	athn_chan2fbin(struct ieee80211_channel *);
+void	athn_get_pier_ival(uint8_t, const uint8_t *, int, int *, int *);
+int	ar9003_attach(struct athn_softc *);
+void	ar9003_write_txpower(struct athn_softc *, int16_t power[]);
+void	ar9003_get_lg_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const uint8_t *, const struct ar_cal_target_power_leg *,
+	    int, uint8_t[]);
+void	ar9003_get_ht_tpow(struct athn_softc *, struct ieee80211_channel *,
+	    uint8_t, const uint8_t *, const struct ar_cal_target_power_ht *,
+	    int, uint8_t[]);
+
+
+int
+ar9380_attach(struct athn_softc *sc)
+{
+	sc->eep_base = AR9380_EEP_START_LOC;
+	sc->eep_size = sizeof(struct ar9380_eeprom);
+	sc->eep_def = ar9380_def_rom;
+	sc->ngpiopins = 17;
+	sc->ops.setup = ar9380_setup;
+	sc->ops.swap_rom = ar9380_swap_rom;
+	sc->ops.init_from_rom = ar9380_init_from_rom;
+	sc->ops.set_txpower = ar9380_set_txpower;
+	sc->ops.set_synth = ar9380_set_synth;
+	sc->ops.spur_mitigate = ar9380_spur_mitigate;
+	sc->cca_min_2g = AR9380_PHY_CCA_MIN_GOOD_VAL_2GHZ;
+	sc->cca_max_2g = AR9380_PHY_CCA_MAX_GOOD_VAL_2GHZ;
+	sc->cca_min_5g = AR9380_PHY_CCA_MIN_GOOD_VAL_5GHZ;
+	sc->cca_max_5g = AR9380_PHY_CCA_MAX_GOOD_VAL_5GHZ;
+	sc->ini = &ar9380_2_0_ini;
+
+	return (ar9003_attach(sc));
+}
+
+void
+ar9380_setup(struct athn_softc *sc)
+{
+	struct ieee80211com *ic = &sc->sc_ic;
+	struct ar9380_eeprom *eep = sc->eep;
+	struct ar9380_base_eep_hdr *base = &eep->baseEepHeader;
+	uint8_t kc_entries_log, type;
+
+	if (base->opFlags & AR_OPFLAGS_11A)
+		sc->flags |= ATHN_FLAG_11A;
+	if (base->opFlags & AR_OPFLAGS_11G)
+		sc->flags |= ATHN_FLAG_11G;
+	if (base->opFlags & AR_OPFLAGS_11N)
+		sc->flags |= ATHN_FLAG_11N;
+
+	IEEE80211_ADDR_COPY(ic->ic_myaddr, eep->macAddr);
+	sc->led_pin = base->wlanLedGpio;
+
+	/* Check if we have a hardware radio switch. */
+	if (base->rfSilent & AR_EEP_RFSILENT_ENABLED) {
+		sc->flags |= ATHN_FLAG_RFSILENT;
+		/* Get GPIO pin used by hardware radio switch. */
+		sc->rfsilent_pin = base->wlanDisableGpio;
+	}
+
+	/* Get the number of HW key cache entries. */
+	kc_entries_log = MS(base->deviceCap, AR_EEP_DEVCAP_KC_ENTRIES);
+	sc->kc_entries = (kc_entries_log != 0) ?
+	    1 << kc_entries_log : AR_KEYTABLE_SIZE;
+
+	sc->txchainmask = MS(base->txrxMask, AR_EEP_TX_MASK);
+	sc->rxchainmask = MS(base->txrxMask, AR_EEP_RX_MASK);
+
+	/* Select initialization values based on ROM. */
+	type = MS(eep->baseEepHeader.txrxgain, AR_EEP_RX_GAIN);
+	if (type == AR_EEP_RX_GAIN_WO_XLNA)
+		sc->rx_gain = &ar9380_2_0_rx_gain_wo_xlna;
+	else
+		sc->rx_gain = &ar9380_2_0_rx_gain;
+
+	/* Select initialization values based on ROM. */
+	type = MS(eep->baseEepHeader.txrxgain, AR_EEP_TX_GAIN);
+	if (type == AR_EEP_TX_GAIN_HIGH_OB_DB)
+		sc->tx_gain = &ar9380_2_0_tx_gain_high_ob_db;
+	else if (type == AR_EEP_TX_GAIN_LOW_OB_DB)
+		sc->tx_gain = &ar9380_2_0_tx_gain_low_ob_db;
+	else
+		sc->tx_gain = &ar9380_2_0_tx_gain;
+}
+
+void
+ar9380_swap_rom(struct athn_softc *sc)
+{
+#if BYTE_ORDER == BIG_ENDIAN
+	struct ar9380_eeprom *eep = sc->eep;
+	struct ar9380_base_eep_hdr *base = &eep->baseEepHeader;
+	struct ar9380_modal_eep_header *modal;
+	int i;
+
+	base->regDmn[0] = swap16(base->regDmn[0]);
+	base->regDmn[1] = swap16(base->regDmn[1]);
+	base->swreg = swap32(base->swreg);
+
+	modal = &eep->modalHeader2G;
+	modal->antCtrlCommon = swap32(modal->antCtrlCommon);
+	modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2);
+	for (i = 0; i < AR9380_MAX_CHAINS; i++)
+		modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]);
+
+	modal = &eep->modalHeader5G;
+	modal->antCtrlCommon = swap32(modal->antCtrlCommon);
+	modal->antCtrlCommon2 = swap32(modal->antCtrlCommon2);
+	for (i = 0; i < AR9380_MAX_CHAINS; i++)
+		modal->antCtrlChain[i] = swap16(modal->antCtrlChain[i]);
+#endif
+}
+
+int
+ar9380_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	uint32_t freq = c->ic_freq;
+	uint32_t chansel, phy;
+
+	if (IEEE80211_IS_CHAN_2GHZ(c)) {
+		chansel = (freq << 16) / 15;
+		AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE);
+	} else {
+		chansel = (freq << 15) / 15;
+		chansel >>= 1;
+		AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, 0);
+	}
+
+	/* Enable Long Shift Select for synthesizer. */
+	AR_SETBITS(sc, AR_PHY_65NM_CH0_SYNTH4,
+	    AR_PHY_SYNTH4_LONG_SHIFT_SELECT);
+
+	/* Program synthesizer. */
+	phy = (chansel << 2) | AR9380_FRACMODE;
+	DPRINTFN(4, ("AR_PHY_65NM_CH0_SYNTH7=0x%08x\n", phy));
+	AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);
+	/* Toggle Load Synth Channel bit. */
+	AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);
+	return (0);
+}
+
+void
+ar9380_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	const struct ar9380_eeprom *eep = sc->eep;
+	const struct ar9380_modal_eep_header *modal;
+	uint32_t reg;
+	int i;
+
+	if (IEEE80211_IS_CHAN_2GHZ(c))
+		modal = &eep->modalHeader2G;
+	else
+		modal = &eep->modalHeader5G;
+
+	/* Apply XPA bias level. */
+	reg = AR_READ(sc, AR_PHY_65NM_CH0_TOP);
+	reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,
+	    MS(modal->xpaBiasLvl, AR_EEP_XPABIASLVL));
+	AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg);
+	reg = AR_READ(sc, AR_PHY_65NM_CH0_THERM);
+	reg = RW(reg, AR_PHY_65NM_CH0_THERM_SPARE,
+	    MS(modal->xpaBiasLvl, AR_EEP_THERM_SPARE));
+	AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg);
+
+	/* Apply antenna control. */
+	reg = AR_READ(sc, AR_PHY_SWITCH_COM);
+	reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);
+	AR_WRITE(sc, AR_PHY_SWITCH_COM, reg);
+	reg = AR_READ(sc, AR_PHY_SWITCH_COM_2);
+	reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);
+	AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg);
+
+	for (i = 0; i < AR9380_MAX_CHAINS; i++) {
+		reg = AR_READ(sc, AR_PHY_SWITCH_CHAIN(i));
+		reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);
+		AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg);
+	}
+
+	if (eep->baseEepHeader.miscConfiguration & AR_EEP_DRIVE_STRENGTH) {
+		/* Apply drive strength. */
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS1);
+		reg = (reg & ~0x00ffffc0) | 0x00b6db40;
+		AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS1, reg);
+
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS2);
+		reg = (reg & ~0xffffffe0) | 0xb6db6da0;
+		AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS2, reg);
+
+		reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS4);
+		reg = (reg & ~0xff800000) | 0xb6800000;
+		AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS4, reg);
+	}
+
+	if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) {
+		/* Internal regulator is ON. */
+		AR_CLRBITS(sc, AR_RTC_REG_CONTROL1,
+		    AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+		AR_WRITE(sc, AR_RTC_REG_CONTROL0, eep->baseEepHeader.swreg);
+		AR_SETBITS(sc, AR_RTC_REG_CONTROL1,
+		    AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+	} else
+		AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD);
+}
+
+void
+ar9380_spur_mitigate_cck(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	/* NB: It is safe to call this function for 5GHz channels. */
+	static const int16_t freqs[] = { 2420, 2440, 2464, 2480 };
+	int i, spur, freq;
+	uint32_t reg;
+
+	for (i = 0; i < nitems(freqs); i++) {
+		spur = freqs[i] - c->ic_freq;
+		if (abs(spur) < 10)	/* +/- 10MHz range. */
+			break;
+	}
+	if (i == nitems(freqs)) {
+		/* Disable CCK spur mitigation. */
+		reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
+		reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
+		AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
+		reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
+		reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);
+		reg &= ~AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
+		AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
+		return;
+	}
+	freq = (spur * 524288) / 11;
+
+	reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
+	reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
+	AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
+
+	reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
+	reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq);
+	reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
+	reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
+	reg |= AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
+	AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
+}
+
+void
+ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	const struct ar9380_eeprom *eep;
+	const uint8_t *spurchans;
+	uint32_t reg;
+	int idx, spur_delta_phase, spur_off, range, i;
+	int freq, spur, spur_freq_sd, spur_subchannel_sd;
+
+	if (IEEE80211_IS_CHAN_2GHZ(c))
+		spurchans = eep->modalHeader2G.spurChans;
+	else
+		spurchans = eep->modalHeader5G.spurChans;
+	if (spurchans[0] == 0)
+		return;
+
+	/* Disable OFDM spur mitigation. */
+	AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
+
+	reg = AR_READ(sc, AR_PHY_TIMING11);
+	reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
+	reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
+	reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
+	reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
+	AR_WRITE(sc, AR_PHY_TIMING11, reg);
+
+	AR_CLRBITS(sc, AR_PHY_SFCORR_EXT,
+	    AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD);
+
+	AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
+
+	reg = AR_READ(sc, AR_PHY_SPUR_REG);
+	reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
+	reg &= ~AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
+	reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
+	reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
+	AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
+
+	freq = c->ic_freq;
+#ifndef IEEE80211_NO_HT
+	if (extc != NULL) {
+		range = 19;	/* +/- 19MHz range. */
+		if (AR_READ(sc, AR_PHY_GEN_CTRL) & AR_PHY_GC_DYN2040_PRI_CH)
+			freq += 10;
+		else
+			freq -= 10;
+	} else
+#endif
+		range = 10;	/* +/- 10MHz range. */
+	for (i = 0; i < AR9380_EEPROM_MODAL_SPURS; i++) {
+		spur = spurchans[i];
+		if (spur == 0)
+			return;
+		/* Convert to frequency. */
+		if (IEEE80211_IS_CHAN_2GHZ(c))
+			spur = 2300 + spur;
+		else
+			spur = 4900 + (spur * 5);
+		spur -= freq;
+		if (abs(spur) < range)
+			break;
+	}
+	if (i == AR9380_EEPROM_MODAL_SPURS)
+		return;
+
+	/* Enable OFDM spur mitigation. */
+#ifndef IEEE80211_NO_HT
+	if (extc != NULL) {
+		spur_delta_phase = (spur * 131072) / 5;
+		reg = AR_READ(sc, AR_PHY_GEN_CTRL);
+		if (spur < 0) {
+			spur_subchannel_sd =
+			    (reg & AR_PHY_GC_DYN2040_PRI_CH) == 0;
+			spur_off = spur + 10;
+		} else {
+			spur_subchannel_sd =
+			    (reg & AR_PHY_GC_DYN2040_PRI_CH) != 0;
+			spur_off = spur - 10;
+		}
+	} else
+#endif
+	{
+		spur_delta_phase = (spur * 262144) / 5;
+		spur_subchannel_sd = 0;
+		spur_off = spur;
+	}
+	spur_freq_sd = (spur_off * 512) / 11;
+
+	AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
+
+	reg = AR_READ(sc, AR_PHY_TIMING11);
+	reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
+	reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
+	reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
+	reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
+	AR_WRITE(sc, AR_PHY_TIMING11, reg);
+
+	reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
+	if (spur_subchannel_sd)
+		reg |= AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
+	else
+		reg &= ~AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
+	AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
+
+	AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
+
+	reg = AR_READ(sc, AR_PHY_SPUR_REG);
+	reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
+	reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
+	reg |= AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
+	if (AR_READ(sc, AR_PHY_MODE) & AR_PHY_MODE_DYNAMIC)
+		reg |= AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
+	reg |= AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
+	AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
+
+	idx = (spur * 16) / 5;
+	if (idx < 0)
+		idx--;
+
+	/* Write pilot mask. */
+	AR_SETBITS(sc, AR_PHY_TIMING4,
+	    AR_PHY_TIMING4_ENABLE_PILOT_MASK |
+	    AR_PHY_TIMING4_ENABLE_CHAN_MASK);
+
+	reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK);
+	reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);
+	reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);
+	AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg);
+
+	reg = AR_READ(sc, AR_PHY_SPUR_MASK_A);
+	reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);
+	reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
+	AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg);
+
+	reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK);
+	reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);
+	reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);
+	AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);
+}
+
+void
+ar9380_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	/* NB: We call spur_mitigate_cck for 5GHz too, just to disable it. */
+	ar9380_spur_mitigate_cck(sc, c, extc);
+	ar9380_spur_mitigate_ofdm(sc, c, extc);
+}
+
+void
+ar9380_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
+    struct ieee80211_channel *extc)
+{
+	const struct ar9380_eeprom *eep = sc->eep;
+	uint8_t tpow_cck[4], tpow_ofdm[4];
+#ifndef IEEE80211_NO_HT
+	uint8_t tpow_ht20[14], tpow_ht40[14];
+#endif
+	int16_t power[ATHN_POWER_COUNT];
+
+	if (IEEE80211_IS_CHAN_2GHZ(c)) {
+		/* Get CCK target powers. */
+		ar9003_get_lg_tpow(sc, c, AR_CTL_11B,
+		    eep->calTargetFbinCck, eep->calTargetPowerCck,
+		    AR9380_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
+
+		/* Get OFDM target powers. */
+		ar9003_get_lg_tpow(sc, c, AR_CTL_11G,
+		    eep->calTargetFbin2G, eep->calTargetPower2G,
+		    AR9380_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
+
+#ifndef IEEE80211_NO_HT
+		/* Get HT-20 target powers. */
+		ar9003_get_ht_tpow(sc, c, AR_CTL_2GHT20,
+		    eep->calTargetFbin2GHT20, eep->calTargetPower2GHT20,
+		    AR9380_NUM_2G_20_TARGET_POWERS, tpow_ht20);
+
+		if (extc != NULL) {
+			/* Get HT-40 target powers. */
+			ar9003_get_ht_tpow(sc, c, AR_CTL_2GHT40,
+			    eep->calTargetFbin2GHT40,
+			    eep->calTargetPower2GHT40,
+			    AR9380_NUM_2G_40_TARGET_POWERS, tpow_ht40);
+		}
+#endif
+	} else {
+		/* Get OFDM target powers. */
+		ar9003_get_lg_tpow(sc, c, AR_CTL_11A,
+		    eep->calTargetFbin2G, eep->calTargetPower5G,
+		    AR9380_NUM_5G_20_TARGET_POWERS, tpow_ofdm);
+
+#ifndef IEEE80211_NO_HT
+		/* Get HT-20 target powers. */
+		ar9003_get_ht_tpow(sc, c, AR_CTL_5GHT20,
+		    eep->calTargetFbin5GHT20, eep->calTargetPower5GHT20,
+		    AR9380_NUM_5G_20_TARGET_POWERS, tpow_ht20);
+
+		if (extc != NULL) {
+			/* Get HT-40 target powers. */
+			ar9003_get_ht_tpow(sc, c, AR_CTL_5GHT40,
+			    eep->calTargetFbin5GHT40,
+			    eep->calTargetPower5GHT40,
+			    AR9380_NUM_5G_40_TARGET_POWERS, tpow_ht40);
+		}
+#endif
+	}
+
+	memset(power, 0, sizeof(power));
+	/* Shuffle target powers accross transmit rates. */
+	power[ATHN_POWER_OFDM6 ] =
+	power[ATHN_POWER_OFDM9 ] =
+	power[ATHN_POWER_OFDM12] =
+	power[ATHN_POWER_OFDM18] =
+	power[ATHN_POWER_OFDM24] = tpow_ofdm[0];
+	power[ATHN_POWER_OFDM36] = tpow_ofdm[1];
+	power[ATHN_POWER_OFDM48] = tpow_ofdm[2];
+	power[ATHN_POWER_OFDM54] = tpow_ofdm[3];
+	if (IEEE80211_IS_CHAN_2GHZ(c)) {
+		power[ATHN_POWER_CCK1_LP ] =
+		power[ATHN_POWER_CCK2_LP ] =
+		power[ATHN_POWER_CCK2_SP ] =
+		power[ATHN_POWER_CCK55_LP] = tpow_cck[0];
+		power[ATHN_POWER_CCK55_SP] = tpow_cck[1];
+		power[ATHN_POWER_CCK11_LP] = tpow_cck[2];
+		power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
+	}
+#ifndef IEEE80211_NO_HT
+	/* Next entry covers MCS0, MCS8 and MCS16. */
+	power[ATHN_POWER_HT20( 0)] = tpow_ht20[ 0];
+	/* Next entry covers MCS1-3, MCS9-11 and MCS17-19. */
+	power[ATHN_POWER_HT20( 1)] = tpow_ht20[ 1];
+	power[ATHN_POWER_HT20( 4)] = tpow_ht20[ 2];
+	power[ATHN_POWER_HT20( 5)] = tpow_ht20[ 3];
+	power[ATHN_POWER_HT20( 6)] = tpow_ht20[ 4];
+	power[ATHN_POWER_HT20( 7)] = tpow_ht20[ 5];
+	power[ATHN_POWER_HT20(12)] = tpow_ht20[ 6];
+	power[ATHN_POWER_HT20(13)] = tpow_ht20[ 7];
+	power[ATHN_POWER_HT20(14)] = tpow_ht20[ 8];
+	power[ATHN_POWER_HT20(15)] = tpow_ht20[ 9];
+	power[ATHN_POWER_HT20(20)] = tpow_ht20[10];
+	power[ATHN_POWER_HT20(21)] = tpow_ht20[11];
+	power[ATHN_POWER_HT20(22)] = tpow_ht20[12];
+	power[ATHN_POWER_HT20(23)] = tpow_ht20[13];
+	if (extc != NULL) {
+		/* Next entry covers MCS0, MCS8 and MCS16. */
+		power[ATHN_POWER_HT40( 0)] = tpow_ht40[ 0];
+		/* Next entry covers MCS1-3, MCS9-11 and MCS17-19. */
+		power[ATHN_POWER_HT40( 1)] = tpow_ht40[ 1];
+		power[ATHN_POWER_HT40( 4)] = tpow_ht40[ 2];
+		power[ATHN_POWER_HT40( 5)] = tpow_ht40[ 3];
+		power[ATHN_POWER_HT40( 6)] = tpow_ht40[ 4];
+		power[ATHN_POWER_HT40( 7)] = tpow_ht40[ 5];
+		power[ATHN_POWER_HT40(12)] = tpow_ht40[ 6];
+		power[ATHN_POWER_HT40(13)] = tpow_ht40[ 7];
+		power[ATHN_POWER_HT40(14)] = tpow_ht40[ 8];
+		power[ATHN_POWER_HT40(15)] = tpow_ht40[ 9];
+		power[ATHN_POWER_HT40(20)] = tpow_ht40[10];
+		power[ATHN_POWER_HT40(21)] = tpow_ht40[11];
+		power[ATHN_POWER_HT40(22)] = tpow_ht40[12];
+		power[ATHN_POWER_HT40(23)] = tpow_ht40[13];
+	}
+#endif
+
+	/* Write transmit power values to hardware. */
+	ar9003_write_txpower(sc, power);
+
+	/* Apply transmit power correction. */
+	ar9380_set_correction(sc, c);
+}
+
+void
+ar9380_get_correction(struct athn_softc *sc, struct ieee80211_channel *c,
+    int chain, int *corr, int *temp)
+{
+	const struct ar9380_eeprom *eep = sc->eep;
+	const struct ar9380_cal_data_per_freq_op_loop *pierdata;
+	const uint8_t *pierfreq;
+	uint8_t fbin;
+	int lo, hi, npiers;
+
+	if (IEEE80211_IS_CHAN_2GHZ(c)) {
+		pierfreq = eep->calFreqPier2G;
+		pierdata = eep->calPierData2G[chain];
+		npiers = AR9380_NUM_2G_CAL_PIERS;
+	} else {
+		pierfreq = eep->calFreqPier5G;
+		pierdata = eep->calPierData5G[chain];
+		npiers = AR9380_NUM_5G_CAL_PIERS;
+	}
+	/* Find channel in ROM pier table. */
+	fbin = athn_chan2fbin(c);
+	athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
+
+	*corr = athn_interpolate(fbin,
+	    pierfreq[lo], pierdata[lo].refPower,
+	    pierfreq[hi], pierdata[hi].refPower);
+	*temp = athn_interpolate(fbin,
+	    pierfreq[lo], pierdata[lo].tempMeas,
+	    pierfreq[hi], pierdata[hi].tempMeas);
+}
+
+void
+ar9380_set_correction(struct athn_softc *sc, struct ieee80211_channel *c)
+{
+	const struct ar9380_eeprom *eep = sc->eep;
+	uint32_t reg;
+	int8_t slope;
+	int i, corr, temp, temp0;
+
+	for (i = 0; i < AR9380_MAX_CHAINS; i++) {
+		ar9380_get_correction(sc, c, i, &corr, &temp);
+		if (i == 0)
+			temp0 = temp;
+
+		reg = AR_READ(sc, AR_PHY_TPC_11_B(i));
+		reg = RW(reg, AR_PHY_TPC_OLPC_GAIN_DELTA, corr);
+		AR_WRITE(sc, AR_PHY_TPC_11_B(i), reg);
+
+		/* Enable open loop power control. */
+		reg = AR_READ(sc, AR_PHY_TPC_6_B(i));
+		reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3);
+		AR_WRITE(sc, AR_PHY_TPC_6_B(i), reg);
+	}
+
+	/* Enable temperature compensation. */
+	if (IEEE80211_IS_CHAN_2GHZ(c))
+		slope = eep->modalHeader2G.tempSlope;
+	else
+		slope = eep->modalHeader5G.tempSlope;
+
+	reg = AR_READ(sc, AR_PHY_TPC_19);
+	reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope);
+	AR_WRITE(sc, AR_PHY_TPC_19, reg);
+
+	reg = AR_READ(sc, AR_PHY_TPC_18);
+	reg = RW(reg, AR_PHY_TPC_18_THERM_CAL_VALUE, temp0);
+	AR_WRITE(sc, AR_PHY_TPC_18, reg);
+}
diff --git a/sys/dev/ic/ar9380reg.h b/sys/dev/ic/ar9380reg.h
new file mode 100644
index 00000000000..1c8aa80dead
--- /dev/null
+++ b/sys/dev/ic/ar9380reg.h
@@ -0,0 +1,970 @@
+/*	$OpenBSD: ar9380reg.h,v 1.1 2010/05/10 17:44:21 damien Exp $	*/
+
+/*-
+ * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define AR9380_MAX_CHAINS	3
+
+#define AR9380_PHY_CCA_NOM_VAL_2GHZ		(-110)
+#define AR9380_PHY_CCA_NOM_VAL_5GHZ		(-115)
+#define AR9380_PHY_CCA_MIN_GOOD_VAL_2GHZ	(-125)
+#define AR9380_PHY_CCA_MIN_GOOD_VAL_5GHZ	(-125)
+#define AR9380_PHY_CCA_MAX_GOOD_VAL_2GHZ	( -95)
+#define AR9380_PHY_CCA_MAX_GOOD_VAL_5GHZ	(-100)
+
+/*
+ * ROM layout used by AR9380.
+ */
+#define AR9380_EEP_START_LOC		0x3ff
+#define AR9380_NUM_5G_CAL_PIERS		8
+#define AR9380_NUM_2G_CAL_PIERS		3
+#define AR9380_NUM_5G_20_TARGET_POWERS	8
+#define AR9380_NUM_5G_40_TARGET_POWERS	8
+#define AR9380_NUM_2G_CCK_TARGET_POWERS	2
+#define AR9380_NUM_2G_20_TARGET_POWERS	3
+#define AR9380_NUM_2G_40_TARGET_POWERS	3
+#define AR9380_NUM_CTLS_5G		9
+#define AR9380_NUM_CTLS_2G		12
+#define AR9380_NUM_BAND_EDGES_5G	8
+#define AR9380_NUM_BAND_EDGES_2G	4
+#define AR9380_NUM_PD_GAINS		4
+#define AR9380_PD_GAINS_IN_MASK		4
+#define AR9380_PD_GAIN_ICEPTS		5
+#define AR9380_EEPROM_MODAL_SPURS	5
+#define AR9380_CUSTOMER_DATA_SIZE	20
+
+struct ar9380_cal_ctl_data_2g {
+	uint8_t	ctlEdges[AR9380_NUM_BAND_EDGES_2G];
+} __packed;
+
+struct ar9380_cal_ctl_data_5g {
+	uint8_t	ctlEdges[AR9380_NUM_BAND_EDGES_5G];
+} __packed;
+
+struct ar9380_base_eep_hdr {
+	uint16_t	regDmn[2];
+	uint8_t		txrxMask;
+#define AR_EEP_TX_MASK_M	0xf0
+#define AR_EEP_TX_MASK_S	4
+#define AR_EEP_RX_MASK_M	0x0f
+#define AR_EEP_RX_MASK_S	0
+
+	uint8_t		opFlags;
+#define AR_OPFLAGS_11A			0x01
+#define AR_OPFLAGS_11G			0x02
+#define AR_OPFLAGS_11N_5G40		0x04
+#define AR_OPFLAGS_11N_2G40		0x08
+#define AR_OPFLAGS_11N_5G20		0x10
+#define AR_OPFLAGS_11N_2G20		0x20
+/* Shortcut. */
+#define AR_OPFLAGS_11N			0x3c
+
+	uint8_t		eepMisc;
+	uint8_t		rfSilent;
+#define AR_EEP_RFSILENT_ENABLED		0x0001
+#define AR_EEP_RFSILENT_POLARITY	0x0002
+
+	uint8_t		blueToothOptions;
+	uint8_t		deviceCap;
+#define AR_EEP_DEVCAP_KC_ENTRIES_M	0xf000
+#define AR_EEP_DEVCAP_KC_ENTRIES_S	12
+
+	uint8_t		deviceType;
+	int8_t		pwrTableOffset;
+	uint8_t		params_for_tuning_caps[2];
+	uint8_t		featureEnable;
+#define AR_EEP_TX_TEMP_COMP_EN		0x01
+#define AR_EEP_TX_VOLT_COMP_EN		0x02
+#define AR_EEP_FAST_CLOCK_EN		0x04
+#define AR_EEP_DOUBLING_EN		0x08
+#define AR_EEP_INTERNAL_REGULATOR	0x10
+
+	uint8_t		miscConfiguration;
+#define AR_EEP_DRIVE_STRENGTH		0x01
+
+	uint8_t		eepromWriteEnableGpio;
+	uint8_t		wlanDisableGpio;
+	uint8_t		wlanLedGpio;
+	uint8_t		rxBandSelectGpio;
+	uint8_t		txrxgain;
+#define AR_EEP_TX_GAIN_M		0xf0
+#define AR_EEP_TX_GAIN_S		4
+#define AR_EEP_TX_GAIN_HIGH_OB_DB	1
+#define AR_EEP_TX_GAIN_LOW_OB_DB	2
+#define AR_EEP_RX_GAIN_M		0x0f
+#define AR_EEP_RX_GAIN_S		0
+#define AR_EEP_RX_GAIN_WO_XLNA		1
+
+	uint32_t	swreg;
+} __packed;
+
+struct ar9380_modal_eep_header {
+	uint32_t	antCtrlCommon;
+	uint32_t	antCtrlCommon2;
+	uint16_t	antCtrlChain[AR9380_MAX_CHAINS];
+	uint8_t		xatten1DB[AR9380_MAX_CHAINS];
+	uint8_t		xatten1Margin[AR9380_MAX_CHAINS];
+	int8_t		tempSlope;
+	int8_t		voltSlope;
+	uint8_t		spurChans[AR9380_EEPROM_MODAL_SPURS];
+	int8_t		noiseFloorThreshCh[AR9380_MAX_CHAINS];
+	uint8_t		ob[AR9380_MAX_CHAINS];
+	uint8_t		db_stage2[AR9380_MAX_CHAINS];
+	uint8_t		db_stage3[AR9380_MAX_CHAINS];
+	uint8_t		db_stage4[AR9380_MAX_CHAINS];
+	uint8_t		xpaBiasLvl;
+#define AR_EEP_XPABIASLVL_M	0x03
+#define AR_EEP_XPABIASLVL_S	0
+#define AR_EEP_THERM_SPARE_M	0x0c
+#define AR_EEP_THERM_SPARE_S	2
+
+	uint8_t		txFrameToDataStart;
+	uint8_t		txFrameToPaOn;
+	uint8_t		txClip;
+	int8_t		antennaGain;
+	uint8_t		switchSettling;
+	int8_t		adcDesiredSize;
+	uint8_t		txEndToXpaOff;
+	uint8_t		txEndToRxOn;
+	uint8_t		txFrameToXpaOn;
+	uint8_t		thresh62;
+	uint8_t		futureModal[32];
+} __packed;
+
+struct ar9380_cal_data_per_freq_op_loop {
+	int8_t	refPower;
+	uint8_t	voltMeas;
+	uint8_t	tempMeas;
+	int8_t	rxNoisefloorCal;
+	int8_t	rxNoisefloorPower;
+	uint8_t	rxTempMeas;
+} __packed;
+
+struct ar9380_eeprom {
+	uint8_t	eepromVersion;
+	uint8_t	templateVersion;
+	uint8_t	macAddr[6];
+	uint8_t	custData[AR9380_CUSTOMER_DATA_SIZE];
+	struct	ar9380_base_eep_hdr baseEepHeader;
+	struct	ar9380_modal_eep_header modalHeader2G;
+	uint8_t	calFreqPier2G[AR9380_NUM_2G_CAL_PIERS];
+	struct	ar9380_cal_data_per_freq_op_loop
+	    calPierData2G[AR9380_MAX_CHAINS][AR9380_NUM_2G_CAL_PIERS];
+	uint8_t	calTargetFbinCck[AR9380_NUM_2G_CCK_TARGET_POWERS];
+	uint8_t	calTargetFbin2G[AR9380_NUM_2G_20_TARGET_POWERS];
+	uint8_t	calTargetFbin2GHT20[AR9380_NUM_2G_20_TARGET_POWERS];
+	uint8_t	calTargetFbin2GHT40[AR9380_NUM_2G_40_TARGET_POWERS];
+	struct	ar_cal_target_power_leg
+	    calTargetPowerCck[AR9380_NUM_2G_CCK_TARGET_POWERS];
+	struct	ar_cal_target_power_leg
+	    calTargetPower2G[AR9380_NUM_2G_20_TARGET_POWERS];
+	struct	ar_cal_target_power_ht
+	    calTargetPower2GHT20[AR9380_NUM_2G_20_TARGET_POWERS];
+	struct	ar_cal_target_power_ht
+	    calTargetPower2GHT40[AR9380_NUM_2G_40_TARGET_POWERS];
+	uint8_t	ctlIndex_2G[AR9380_NUM_CTLS_2G];
+	uint8_t	ctl_freqbin_2G[AR9380_NUM_CTLS_2G][AR9380_NUM_BAND_EDGES_2G];
+	struct	ar9380_cal_ctl_data_2g ctlPowerData_2G[AR9380_NUM_CTLS_2G];
+	struct	ar9380_modal_eep_header modalHeader5G;
+	uint8_t	calFreqPier5G[AR9380_NUM_5G_CAL_PIERS];
+	struct	ar9380_cal_data_per_freq_op_loop
+	    calPierData5G[AR9380_MAX_CHAINS][AR9380_NUM_5G_CAL_PIERS];
+	uint8_t	calTargetFbin5G[AR9380_NUM_5G_20_TARGET_POWERS];
+	uint8_t	calTargetFbin5GHT20[AR9380_NUM_5G_20_TARGET_POWERS];
+	uint8_t	calTargetFbin5GHT40[AR9380_NUM_5G_40_TARGET_POWERS];
+	struct	ar_cal_target_power_leg
+	    calTargetPower5G[AR9380_NUM_5G_20_TARGET_POWERS];
+	struct	ar_cal_target_power_ht
+	    calTargetPower5GHT20[AR9380_NUM_5G_20_TARGET_POWERS];
+	struct	ar_cal_target_power_ht
+	    calTargetPower5GHT40[AR9380_NUM_5G_40_TARGET_POWERS];
+	uint8_t	ctlIndex_5G[AR9380_NUM_CTLS_5G];
+	uint8_t	ctl_freqbin_5G[AR9380_NUM_CTLS_5G][AR9380_NUM_BAND_EDGES_5G];
+	struct	ar9380_cal_ctl_data_5g ctlPowerData_5G[AR9380_NUM_CTLS_5G];
+} __packed;
+
+/*
+ * Default ROM content (little endian).
+ */
+static const uint8_t ar9380_def_rom[] = {
+	0x02, 0x02, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x77, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00,
+	0x00, 0x00, 0x0c, 0x00, 0x03, 0x00, 0x08, 0xff, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x22, 0x22, 0x02,
+	0x00, 0x50, 0x01, 0x50, 0x01, 0x50, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xff, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x0e, 0x03, 0x00,
+	0x2c, 0xe2, 0x00, 0x02, 0x0e, 0x1c, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x89,
+	0xac, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xb8, 0x70, 0x89, 0xac,
+	0x70, 0x89, 0xac, 0x70, 0x89, 0xac, 0x24, 0x24, 0x24, 0x24,
+	0x24, 0x24, 0x24, 0x24, 0x20, 0x20, 0x1c, 0x18, 0x20, 0x20,
+	0x1c, 0x18, 0x20, 0x20, 0x1c, 0x18, 0x20, 0x20, 0x20, 0x20,
+	0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14,
+	0x20, 0x20, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14,
+	0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x14,
+	0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20,
+	0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20,
+	0x1c, 0x14, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20,
+	0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x20, 0x20,
+	0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14, 0x20, 0x20, 0x1c, 0x14,
+	0x11, 0x12, 0x15, 0x17, 0x41, 0x42, 0x45, 0x47, 0x31, 0x32,
+	0x35, 0x37, 0x70, 0x75, 0x9d, 0xa2, 0x70, 0x75, 0xa2, 0xff,
+	0x70, 0x75, 0xa2, 0xff, 0x7a, 0x7f, 0x93, 0x98, 0x70, 0x75,
+	0xac, 0xb8, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75, 0xac, 0x00,
+	0x7a, 0x7f, 0x93, 0xa2, 0x70, 0x75, 0xac, 0x00, 0x70, 0x75,
+	0xac, 0x00, 0x70, 0x75, 0xac, 0x00, 0x7a, 0x7f, 0x93, 0xa2,
+	0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x7c, 0x3c,
+	0x3c, 0x7c, 0x7c, 0x3c, 0x00, 0x00, 0x3c, 0x7c, 0x3c, 0x3c,
+	0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x3c, 0x3c, 0x7c,
+	0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x3c, 0x3c,
+	0x3c, 0x7c, 0x7c, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01,
+	0x00, 0x00, 0x22, 0x22, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x03, 0x03,
+	0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+	0x00, 0x0e, 0x0e, 0x03, 0x00, 0x2d, 0xe2, 0x00, 0x02, 0x0e,
+	0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c, 0xa0, 0xb9,
+	0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x4c, 0x54, 0x68, 0x78, 0x8c,
+	0xa0, 0xb9, 0xcd, 0x4c, 0x58, 0x68, 0x8c, 0xb4, 0xbd, 0xb9,
+	0xcd, 0x4c, 0x58, 0x68, 0x8c, 0xb4, 0xbd, 0xb9, 0xcd, 0x14,
+	0x14, 0x14, 0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14,
+	0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14,
+	0x14, 0x14, 0x0a, 0x14, 0x14, 0x14, 0x0a, 0x14, 0x14, 0x14,
+	0x0a, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+	0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00,
+	0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14,
+	0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+	0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+	0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a,
+	0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+	0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+	0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00,
+	0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14,
+	0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+	0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+	0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a,
+	0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+	0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+	0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00,
+	0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14,
+	0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+	0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a,
+	0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x14, 0x14, 0x0a,
+	0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+	0x00, 0x14, 0x14, 0x0a, 0x0a, 0x00, 0x00, 0x0a, 0x0a, 0x00,
+	0x00, 0x0a, 0x0a, 0x00, 0x00, 0x10, 0x16, 0x18, 0x40, 0x46,
+	0x48, 0x30, 0x36, 0x38, 0x4c, 0x5c, 0x60, 0x8c, 0xa0, 0xb4,
+	0xbd, 0xcd, 0x4c, 0x5c, 0x60, 0x8c, 0x90, 0xb4, 0xbd, 0xcd,
+	0x4e, 0x56, 0x5e, 0x66, 0x8e, 0x96, 0xae, 0xbf, 0x4c, 0x50,
+	0x5c, 0x68, 0x8c, 0xb4, 0xff, 0xff, 0x4c, 0x5c, 0x8c, 0xb4,
+	0xff, 0xff, 0xff, 0xff, 0x4e, 0x5e, 0x66, 0x8e, 0x9e, 0xae,
+	0xff, 0xff, 0x4c, 0x50, 0x54, 0x5c, 0x8c, 0xa0, 0xb4, 0xbd,
+	0x4c, 0x5c, 0x68, 0x8c, 0x98, 0xb4, 0xbd, 0xcd, 0x4e, 0x56,
+	0x5e, 0x8e, 0x96, 0xae, 0xbf, 0xc7, 0x7c, 0x7c, 0x7c, 0x7c,
+	0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+	0x7c, 0x3c, 0x3c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+	0x3c, 0x7c, 0x7c, 0x3c, 0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c,
+	0x7c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c,
+	0x7c, 0x3c, 0x3c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
+	0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c,
+	0x7c, 0x3c, 0x7c, 0x7c, 0x7c, 0x7c, 0x3c, 0x7c
+};
+
+/* Macro to "pack" registers to 16-bit to save some .rodata space. */
+#define P(x)	((x) >> 2)
+
+/*
+ * AR9380 2.0 programming.
+ */
+static const uint16_t ar9380_2_0_regs[] = {
+	P(0x07010), P(0x01030), P(0x01070), P(0x010b0), P(0x08014),
+	P(0x0801c), P(0x08120), P(0x081d0), P(0x08318), P(0x1609c),
+	P(0x160ac), P(0x160b0), P(0x1610c), P(0x1650c), P(0x1690c),
+	P(0x09810), P(0x09820), P(0x09824), P(0x09828), P(0x0982c),
+	P(0x09830), P(0x09c00), P(0x09e00), P(0x09e04), P(0x09e0c),
+	P(0x09e10), P(0x09e14), P(0x09e18), P(0x09e1c), P(0x09e20),
+	P(0x09e2c), P(0x09e44), P(0x09e48), P(0x09fc8), P(0x0a204),
+	P(0x0a208), P(0x0a230), P(0x0a238), P(0x0a250), P(0x0a254),
+	P(0x0a258), P(0x0a25c), P(0x0a260), P(0x0a264), P(0x0a280),
+	P(0x0a284), P(0x0a288), P(0x0a28c), P(0x0a2c4), P(0x0a2d0),
+	P(0x0a2d8), P(0x0a358), P(0x0a830), P(0x0ae04), P(0x0ae18),
+	P(0x0ae1c), P(0x0ae20), P(0x0b284), P(0x0b830), P(0x0be04),
+	P(0x0be18), P(0x0be1c), P(0x0be20), P(0x0c284)
+};
+
+static const uint32_t ar9380_2_0_vals_5g20[] = {
+	0x00000023, 0x00000230, 0x00000168, 0x00000e60, 0x03e803e8,
+	0x128d8027, 0x08f04800, 0x00003210, 0x00003e80, 0x0dd08f29,
+	0xa4653c00, 0x03284f3e, 0x08000000, 0x08000000, 0x08000000,
+	0xd00a8005, 0x206a022e, 0x5ac640d0, 0x06903081, 0x05eea6d4,
+	0x0000059c, 0x00000044, 0x0372161e, 0x00802020, 0x6c4000e2,
+	0x7ec88d2e, 0x31395d5e, 0x00000000, 0x0001cf9c, 0x000003b5,
+	0x0000001c, 0x02321e27, 0x5030201a, 0x0003f000, 0x000037c0,
+	0x00000104, 0x0000000a, 0xffb81018, 0x00000000, 0x000007d0,
+	0x02020002, 0x01000e0e, 0x0a021501, 0x00000e0e, 0x00000007,
+	0x00000000, 0x00000110, 0x00022222, 0x00158d18, 0x00071981,
+	0xf999a83a, 0x00000000, 0x0000019c, 0x00800000, 0x00000000,
+	0x0000019c, 0x000001b5, 0x00000000, 0x0000019c, 0x00800000,
+	0x00000000, 0x0000019c, 0x000001b5, 0x00000000
+};
+
+#ifndef IEEE80211_NO_HT
+static const uint32_t ar9380_2_0_vals_5g40[] = {
+	0x00000023, 0x00000460, 0x000002d0, 0x00001cc0, 0x07d007d0,
+	0x128d804f, 0x08f04800, 0x00003210, 0x00007d00, 0x0dd08f29,
+	0xa4653c00, 0x03284f3e, 0x00000000, 0x00000000, 0x00000000,
+	0xd00a8005, 0x206a022e, 0x5ac640d0, 0x06903081, 0x05eea6d4,
+	0x0000059c, 0x000000c4, 0x0372161e, 0x00802020, 0x6d4000e2,
+	0x7ec88d2e, 0x3139605e, 0x00000000, 0x0001cf9c, 0x000003b5,
+	0x0000001c, 0x02321e27, 0x5030201a, 0x0003f000, 0x000037c4,
+	0x00000104, 0x00000014, 0xffb81018, 0x00000000, 0x00000fa0,
+	0x02020002, 0x01000e0e, 0x0a021501, 0x00000e0e, 0x00000007,
+	0x00000000, 0x00000110, 0x00022222, 0x00158d18, 0x00071981,
+	0xf999a83a, 0x00000000, 0x0000019c, 0x00800000, 0x00000000,
+	0x0000019c, 0x000001b5, 0x00000000, 0x0000019c, 0x00800000,
+	0x00000000, 0x0000019c, 0x000001b5, 0x00000000
+};
+
+static const uint32_t ar9380_2_0_vals_2g40[] = {
+	0x00000023, 0x000002c0, 0x00000318, 0x00007c70, 0x10801600,
+	0x12e00057, 0x08f04810, 0x0000320a, 0x00006880, 0x0b283f31,
+	0x24652800, 0x05d08f20, 0x00000000, 0x00000000, 0x00000000,
+	0xd00a8005, 0x206a012e, 0x5ac640d0, 0x06903881, 0x05eea6d4,
+	0x0000059c, 0x000000c4, 0x037216a0, 0x00802020, 0x6d4000e2,
+	0x7ec84d2e, 0x3139605e, 0x00000000, 0x00021f9c, 0x000003ce,
+	0x00000021, 0x02282324, 0x50302010, 0x0001a000, 0x000037c4,
+	0x00000004, 0x00000016, 0xffb81018, 0x00000210, 0x00001130,
+	0x02020002, 0x01000e0e, 0x3a021501, 0x00000e0e, 0x0000000b,
+	0x00000150, 0x00000110, 0x00022222, 0x00158d18, 0x00071981,
+	0xf999a83a, 0x00000000, 0x0000019c, 0x00800000, 0x00000000,
+	0x0000019c, 0x000001ce, 0x00000150, 0x0000019c, 0x00800000,
+	0x00000000, 0x0000019c, 0x000001ce, 0x00000150
+};
+
+static const uint32_t ar9380_2_0_vals_2g20[] = {
+	0x00000023, 0x00000160, 0x0000018c, 0x00003e38, 0x08400b00,
+	0x12e0002b, 0x08f04810, 0x0000320a, 0x00003440, 0x0b283f31,
+	0x24652800, 0x05d08f20, 0x00000000, 0x00000000, 0x00000000,
+	0xd00a800b, 0x206a012e, 0x5ac640d0, 0x06903881, 0x05eea6d4,
+	0x00000b9c, 0x00000044, 0x037216a0, 0x00802020, 0x6c4000e2,
+	0x7ec84d2e, 0x31395d5e, 0x00000000, 0x00021f9c, 0x000003ce,
+	0x00000021, 0x02282324, 0x50302010, 0x0001a000, 0x000037c0,
+	0x00000004, 0x0000000b, 0xffb81018, 0x00000108, 0x00000898,
+	0x02020002, 0x01000e0e, 0x3a021501, 0x00000e0e, 0x0000000b,
+	0x00000150, 0x00000110, 0x00022222, 0x00158d18, 0x00071982,
+	0xf999a83a, 0x00000000, 0x0000019c, 0x00800000, 0x00000000,
+	0x0000019c, 0x000001ce, 0x00000150, 0x0000019c, 0x00800000,
+	0x00000000, 0x0000019c, 0x000001ce, 0x00000150
+};
+#endif
+
+static const uint16_t ar9380_2_0_cm_regs[] = {
+	P(0x040a4), P(0x07008), P(0x07020), P(0x07034), P(0x07038),
+	P(0x00008), P(0x00030), P(0x00034), P(0x00040), P(0x00044),
+	P(0x00048), P(0x0004c), P(0x00050), P(0x01040), P(0x01044),
+	P(0x01048), P(0x0104c), P(0x01050), P(0x01054), P(0x01058),
+	P(0x0105c), P(0x01060), P(0x01064), P(0x010f0), P(0x01270),
+	P(0x012b0), P(0x012f0), P(0x0143c), P(0x0147c), P(0x08000),
+	P(0x08004), P(0x08008), P(0x0800c), P(0x08018), P(0x08020),
+	P(0x08038), P(0x0803c), P(0x08040), P(0x08044), P(0x08048),
+	P(0x0804c), P(0x08054), P(0x08058), P(0x0805c), P(0x08060),
+	P(0x08064), P(0x08070), P(0x08074), P(0x08078), P(0x0809c),
+	P(0x080a0), P(0x080a4), P(0x080a8), P(0x080ac), P(0x080b0),
+	P(0x080b4), P(0x080b8), P(0x080bc), P(0x080c0), P(0x080c4),
+	P(0x080c8), P(0x080cc), P(0x080d0), P(0x080d4), P(0x080d8),
+	P(0x080dc), P(0x080e0), P(0x080e4), P(0x080e8), P(0x080ec),
+	P(0x080f0), P(0x080f4), P(0x080fc), P(0x08100), P(0x08108),
+	P(0x0810c), P(0x08110), P(0x08114), P(0x08118), P(0x0811c),
+	P(0x08124), P(0x08128), P(0x0812c), P(0x08130), P(0x08134),
+	P(0x08138), P(0x0813c), P(0x08144), P(0x08168), P(0x0816c),
+	P(0x08170), P(0x08174), P(0x08178), P(0x0817c), P(0x081c0),
+	P(0x081c4), P(0x081c8), P(0x081cc), P(0x081d4), P(0x081ec),
+	P(0x081f0), P(0x081f4), P(0x081f8), P(0x081fc), P(0x08240),
+	P(0x08244), P(0x08248), P(0x0824c), P(0x08250), P(0x08254),
+	P(0x08258), P(0x0825c), P(0x08260), P(0x08264), P(0x08268),
+	P(0x0826c), P(0x08270), P(0x08274), P(0x08278), P(0x0827c),
+	P(0x08284), P(0x08288), P(0x0828c), P(0x08294), P(0x08298),
+	P(0x0829c), P(0x08300), P(0x08314), P(0x0831c), P(0x08328),
+	P(0x0832c), P(0x08330), P(0x08334), P(0x08338), P(0x0833c),
+	P(0x08340), P(0x08344), P(0x08348), P(0x0835c), P(0x08360),
+	P(0x08364), P(0x08368), P(0x08370), P(0x08374), P(0x08378),
+	P(0x0837c), P(0x08380), P(0x08384), P(0x08390), P(0x08394),
+	P(0x08398), P(0x0839c), P(0x083a0), P(0x083a4), P(0x083a8),
+	P(0x083ac), P(0x083b0), P(0x083b4), P(0x083b8), P(0x083bc),
+	P(0x083c0), P(0x083c4), P(0x083c8), P(0x083cc), P(0x083d0),
+	P(0x09800), P(0x09804), P(0x09808), P(0x0980c), P(0x09814),
+	P(0x09818), P(0x0981c), P(0x09834), P(0x09838), P(0x0983c),
+	P(0x09880), P(0x09884), P(0x098a4), P(0x098b0), P(0x098d0),
+	P(0x098d4), P(0x098dc), P(0x098f0), P(0x098f4), P(0x09c04),
+	P(0x09c08), P(0x09c0c), P(0x09c10), P(0x09c14), P(0x09c18),
+	P(0x09c1c), P(0x09d00), P(0x09d04), P(0x09d08), P(0x09d0c),
+	P(0x09d10), P(0x09d14), P(0x09d18), P(0x09e08), P(0x09e24),
+	P(0x09e28), P(0x09e30), P(0x09e34), P(0x09e38), P(0x09e3c),
+	P(0x09e40), P(0x09e4c), P(0x09e50), P(0x09e54), P(0x09fc0),
+	P(0x09fc4), P(0x09fcc), P(0x09fd0), P(0x0a20c), P(0x0a220),
+	P(0x0a224), P(0x0a228), P(0x0a22c), P(0x0a234), P(0x0a23c),
+	P(0x0a244), P(0x0a2a0), P(0x0a2c0), P(0x0a2c8), P(0x0a2cc),
+	P(0x0a2d4), P(0x0a2dc), P(0x0a2e0), P(0x0a2e4), P(0x0a2e8),
+	P(0x0a2ec), P(0x0a2f0), P(0x0a2f4), P(0x0a2f8), P(0x0a344),
+	P(0x0a34c), P(0x0a350), P(0x0a364), P(0x0a370), P(0x0a390),
+	P(0x0a394), P(0x0a398), P(0x0a39c), P(0x0a3a0), P(0x0a3a4),
+	P(0x0a3a8), P(0x0a3ac), P(0x0a3c0), P(0x0a3c4), P(0x0a3c8),
+	P(0x0a3cc), P(0x0a3d0), P(0x0a3d4), P(0x0a3d8), P(0x0a3dc),
+	P(0x0a3e0), P(0x0a3e4), P(0x0a3e8), P(0x0a3ec), P(0x0a3f0),
+	P(0x0a3f4), P(0x0a3f8), P(0x0a3fc), P(0x0a400), P(0x0a404),
+	P(0x0a408), P(0x0a40c), P(0x0a414), P(0x0a418), P(0x0a41c),
+	P(0x0a420), P(0x0a424), P(0x0a428), P(0x0a42c), P(0x0a430),
+	P(0x0a434), P(0x0a438), P(0x0a43c), P(0x0a440), P(0x0a444),
+	P(0x0a448), P(0x0a44c), P(0x0a450), P(0x0a458), P(0x0a600),
+	P(0x0a604), P(0x0a608), P(0x0a60c), P(0x0a610), P(0x0a614),
+	P(0x0a618), P(0x0a61c), P(0x0a620), P(0x0a624), P(0x0a628),
+	P(0x0a62c), P(0x0a630), P(0x0a634), P(0x0a638), P(0x0a63c),
+	P(0x0a640), P(0x0a644), P(0x0a648), P(0x0a64c), P(0x0a670),
+	P(0x0a674), P(0x0a678), P(0x0a67c), P(0x0a680), P(0x0a684),
+	P(0x0a688), P(0x0a690), P(0x0a7c0), P(0x0a7c4), P(0x0a7c8),
+	P(0x0a7cc), P(0x0a7d0), P(0x0a7d4), P(0x0a7dc), P(0x0a8d0),
+	P(0x0a8d4), P(0x0a8dc), P(0x0a8f0), P(0x0a8f4), P(0x0b2d0),
+	P(0x0b2d4), P(0x0b2dc), P(0x0b2e0), P(0x0b2e4), P(0x0b2e8),
+	P(0x0b2ec), P(0x0b2f0), P(0x0b2f4), P(0x0b2f8), P(0x0b408),
+	P(0x0b40c), P(0x0b420), P(0x0b8d0), P(0x0b8d4), P(0x0b8dc),
+	P(0x0b8f0), P(0x0b8f4), P(0x0c2d0), P(0x0c2d4), P(0x0c2dc),
+	P(0x0c2e0), P(0x0c2e4), P(0x0c2e8), P(0x0c2ec), P(0x0c2f0),
+	P(0x0c2f4), P(0x0c2f8), P(0x0c408), P(0x0c40c), P(0x0c420),
+	P(0x16000), P(0x16004), P(0x16008), P(0x1600c), P(0x16040),
+	P(0x1604c), P(0x16050), P(0x16054), P(0x16058), P(0x1605c),
+	P(0x16060), P(0x16064), P(0x1606c), P(0x16080), P(0x16084),
+	P(0x16088), P(0x1608c), P(0x16090), P(0x16098), P(0x160a0),
+	P(0x160a4), P(0x160a8), P(0x160b4), P(0x160c0), P(0x160c4),
+	P(0x160c8), P(0x160cc), P(0x16100), P(0x16104), P(0x16108),
+	P(0x16140), P(0x16144), P(0x16148), P(0x16280), P(0x16284),
+	P(0x16288), P(0x1628c), P(0x16290), P(0x16294), P(0x16380),
+	P(0x16384), P(0x16388), P(0x1638c), P(0x16390), P(0x16394),
+	P(0x16398), P(0x1639c), P(0x163a0), P(0x163a4), P(0x163a8),
+	P(0x163ac), P(0x163b0), P(0x163b4), P(0x163b8), P(0x163bc),
+	P(0x163c0), P(0x163c4), P(0x163c8), P(0x163cc), P(0x163d0),
+	P(0x163d4), P(0x16400), P(0x16404), P(0x16408), P(0x1640c),
+	P(0x16440), P(0x1644c), P(0x16450), P(0x16454), P(0x16458),
+	P(0x1645c), P(0x16460), P(0x16464), P(0x1646c), P(0x16500),
+	P(0x16504), P(0x16508), P(0x16540), P(0x16544), P(0x16548),
+	P(0x16780), P(0x16784), P(0x16788), P(0x1678c), P(0x16790),
+	P(0x16794), P(0x16798), P(0x1679c), P(0x167a0), P(0x167a4),
+	P(0x167a8), P(0x167ac), P(0x167b0), P(0x167b4), P(0x167b8),
+	P(0x167bc), P(0x167c0), P(0x167c4), P(0x167c8), P(0x167cc),
+	P(0x167d0), P(0x167d4), P(0x16800), P(0x16804), P(0x16808),
+	P(0x1680c), P(0x16840), P(0x1684c), P(0x16850), P(0x16854),
+	P(0x16858), P(0x1685c), P(0x16860), P(0x16864), P(0x1686c),
+	P(0x16900), P(0x16904), P(0x16908), P(0x16940), P(0x16944),
+	P(0x16948), P(0x16b80), P(0x16b84), P(0x16b88), P(0x16b8c),
+	P(0x16b90), P(0x16b94), P(0x16b98), P(0x16b9c), P(0x16ba0),
+	P(0x16ba4), P(0x16ba8), P(0x16bac), P(0x16bb0), P(0x16bb4),
+	P(0x16bb8), P(0x16bbc), P(0x16bc0), P(0x16bc4), P(0x16bc8),
+	P(0x16bcc), P(0x16bd0), P(0x16bd4)
+};
+
+static const uint32_t ar9380_2_0_cm_vals[] = {
+	0x00a0c1c9, 0x00000000, 0x00000000, 0x00000002, 0x000004c2,
+	0x00000000, 0x00020085, 0x00000005, 0x00000000, 0x00000000,
+	0x00000008, 0x00000010, 0x00000000, 0x002ffc0f, 0x002ffc0f,
+	0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x002ffc0f,
+	0x002ffc0f, 0x002ffc0f, 0x002ffc0f, 0x00000100, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0xffffffff, 0x00000000, 0x00000000, 0x000fc78f, 0x0000000f,
+	0x00000000, 0x00000310, 0x00000020, 0x00000000, 0x0000000f,
+	0x00000000, 0x02ff0000, 0x0e070605, 0x0000000d, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x2a800000, 0x06900168,
+	0x13881c20, 0x01f40000, 0x00252500, 0x00a00000, 0x00400000,
+	0x00000000, 0xffffffff, 0x0000ffff, 0x3f3f3f3f, 0x00000000,
+	0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000052,
+	0x00000000, 0x00000000, 0x000007ff, 0x000000aa, 0x00003210,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x0000ffff, 0xffffffff, 0x00000000, 0x00000000,
+	0x18486200, 0x33332210, 0x00000000, 0x00020000, 0x00000000,
+	0x33332210, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00100000,
+	0x0010f424, 0x00000800, 0x0001e848, 0x00000000, 0x00000000,
+	0x00000000, 0x40000000, 0x00080922, 0x98a00010, 0xffffffff,
+	0x0000ffff, 0x00000000, 0x40000000, 0x003e4180, 0x00000004,
+	0x0000002c, 0x0000002c, 0x000000ff, 0x00000000, 0x00000000,
+	0x00000000, 0x00000140, 0x00000000, 0x0000010d, 0x00000000,
+	0x00000007, 0x00000302, 0x00000700, 0x00ff0000, 0x02400000,
+	0x000107ff, 0xaa48105b, 0x008f0000, 0x00000000, 0xffffffff,
+	0xffffffff, 0x00000000, 0x00000000, 0x000000ff, 0x00000000,
+	0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0x00000000, 0x00000000, 0x00000000, 0x0000fa14, 0x000f0c00,
+	0x33332210, 0x33332210, 0x33332210, 0x33332210, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x000301ff,
+	0xafe68e30, 0xfd14e000, 0x9c0a9f6b, 0x04900000, 0x9280c00a,
+	0x00000000, 0x00020028, 0x5f3ca3de, 0x0108ecff, 0x14750600,
+	0x201fff00, 0x00001042, 0x00200400, 0x52440bbe, 0x004b6a8e,
+	0x00000820, 0x00000000, 0x00000000, 0x00000000, 0xff55ff55,
+	0x0320ff55, 0x00000000, 0x00000000, 0x00046384, 0x05b6b440,
+	0x00b6b440, 0xc080a333, 0x40206c10, 0x009c4060, 0x9883800a,
+	0x01834061, 0x00c0040b, 0x00000000, 0x0038233c, 0x990bb515,
+	0x0c6f0000, 0x06336f77, 0x6af6532f, 0x0cc80c00, 0xcf946222,
+	0x0d261820, 0x00001004, 0x00ff03f1, 0x00000000, 0x803e4788,
+	0x0001efb5, 0x40000014, 0x01193b93, 0x00000000, 0x00000000,
+	0x00000000, 0x10002310, 0x01036a1e, 0x10000fff, 0x00000000,
+	0x0c000000, 0x00000001, 0x00000001, 0x00000000, 0x18c43433,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x0000a000, 0x00000000, 0x00000000, 0x00000001,
+	0x00000444, 0x001f0e0f, 0x0075393f, 0xb79f6427, 0x00000000,
+	0xaaaaaaaa, 0x3c466478, 0x20202020, 0x22222220, 0x20200020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x00000000,
+	0x00000246, 0x0cdbd380, 0x000f0f01, 0x8fa91f01, 0x00000000,
+	0x0e79e5c6, 0x00820820, 0x1ce739ce, 0x2d001dce, 0x1ce739ce,
+	0x000001ce, 0x1ce739ce, 0x000001ce, 0x1ce739ce, 0x1ce739ce,
+	0x00000000, 0x00001801, 0x00000000, 0x00000000, 0x00000000,
+	0x04000080, 0x00000001, 0x00010000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x3fad9d74, 0x0048060a, 0x00000637, 0x03020100,
+	0x09080504, 0x0d0c0b0a, 0x13121110, 0x31301514, 0x35343332,
+	0x00000036, 0x00000838, 0x00000000, 0xfffffffc, 0x00000000,
+	0x00000000, 0x00000000, 0x00000004, 0x00000001, 0x004b6a8e,
+	0x00000820, 0x00000000, 0x00000000, 0x00000000, 0x00000080,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0e79e5c0,
+	0x00820820, 0x00000000, 0x004b6a8e, 0x00000820, 0x00000000,
+	0x00000000, 0x00000000, 0x00000080, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x0e79e5c0, 0x00820820, 0x00000000,
+	0x36db6db6, 0x6db6db40, 0x73f00000, 0x00000000, 0x7f80fff8,
+	0x76d005b5, 0x556cf031, 0x43449440, 0x0c51c92c, 0x3db7fffc,
+	0xfffffffc, 0x000f0278, 0x6db60000, 0x00000000, 0x0e48048c,
+	0x54214514, 0x119f481e, 0x24926490, 0xd2888888, 0x0a108ffe,
+	0x812fc370, 0x423c8000, 0x92480080, 0x00adb6d0, 0x6db6db60,
+	0x6db6db6c, 0x01e6c000, 0x3fffbe01, 0xfff80000, 0x00080010,
+	0x10804008, 0x02084080, 0x00000000, 0x058a0001, 0x3d840208,
+	0x01a20408, 0x00038c07, 0x40000004, 0x458aa14f, 0x00000000,
+	0x00000000, 0x00800700, 0x00800700, 0x00800700, 0x00000000,
+	0x00000000, 0x00000000, 0x00000001, 0x00000001, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x000000a0, 0x000c0000, 0x14021402, 0x00001402, 0x00000000,
+	0x00000000, 0x36db6db6, 0x6db6db40, 0x73f00000, 0x00000000,
+	0x7f80fff8, 0x76d005b5, 0x556cf031, 0x43449440, 0x0c51c92c,
+	0x3db7fffc, 0xfffffffc, 0x000f0278, 0x6db60000, 0x3fffbe01,
+	0xfff80000, 0x00080010, 0x10804008, 0x02084080, 0x00000000,
+	0x00000000, 0x00000000, 0x00800700, 0x00800700, 0x00800700,
+	0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00000001,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x000000a0, 0x000c0000, 0x14021402, 0x00001402,
+	0x00000000, 0x00000000, 0x36db6db6, 0x6db6db40, 0x73f00000,
+	0x00000000, 0x7f80fff8, 0x76d005b5, 0x556cf031, 0x43449440,
+	0x0c51c92c, 0x3db7fffc, 0xfffffffc, 0x000f0278, 0x6db60000,
+	0x3fffbe01, 0xfff80000, 0x00080010, 0x10804008, 0x02084080,
+	0x00000000, 0x00000000, 0x00000000, 0x00800700, 0x00800700,
+	0x00800700, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
+	0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x000000a0, 0x000c0000, 0x14021402,
+	0x00001402, 0x00000000, 0x00000000
+};
+
+static const struct athn_ini ar9380_2_0_ini = {
+	nitems(ar9380_2_0_regs),
+	ar9380_2_0_regs,
+	ar9380_2_0_vals_5g20,
+#ifndef IEEE80211_NO_HT
+	ar9380_2_0_vals_5g40,
+	ar9380_2_0_vals_2g40,
+#endif
+	ar9380_2_0_vals_2g20,
+	nitems(ar9380_2_0_cm_regs),
+	ar9380_2_0_cm_regs,
+	ar9380_2_0_cm_vals
+};
+
+/*
+ * AR9380 2.0 Tx gains.
+ */
+static const uint16_t ar9380_2_0_tx_gain_regs[] = {
+	P(0x0a410), P(0x0a500), P(0x0a504), P(0x0a508), P(0x0a50c),
+	P(0x0a510), P(0x0a514), P(0x0a518), P(0x0a51c), P(0x0a520),
+	P(0x0a524), P(0x0a528), P(0x0a52c), P(0x0a530), P(0x0a534),
+	P(0x0a538), P(0x0a53c), P(0x0a540), P(0x0a544), P(0x0a548),
+	P(0x0a54c), P(0x0a550), P(0x0a554), P(0x0a558), P(0x0a55c),
+	P(0x0a560), P(0x0a564), P(0x0a568), P(0x0a56c), P(0x0a570),
+	P(0x0a574), P(0x0a578), P(0x0a57c), P(0x0a580), P(0x0a584),
+	P(0x0a588), P(0x0a58c), P(0x0a590), P(0x0a594), P(0x0a598),
+	P(0x0a59c), P(0x0a5a0), P(0x0a5a4), P(0x0a5a8), P(0x0a5ac),
+	P(0x0a5b0), P(0x0a5b4), P(0x0a5b8), P(0x0a5bc), P(0x0a5c0),
+	P(0x0a5c4), P(0x0a5c8), P(0x0a5cc), P(0x0a5d0), P(0x0a5d4),
+	P(0x0a5d8), P(0x0a5dc), P(0x0a5e0), P(0x0a5e4), P(0x0a5e8),
+	P(0x0a5ec), P(0x0a5f0), P(0x0a5f4), P(0x0a5f8), P(0x0a5fc),
+	P(0x16044), P(0x16048), P(0x16068), P(0x16444), P(0x16448),
+	P(0x16468), P(0x16844), P(0x16848), P(0x16868)
+};
+
+static const uint32_t ar9380_2_0_tx_gain_vals_5g[] = {
+	0x000050d9, 0x00000000, 0x06000003, 0x0a000020, 0x10000023,
+	0x16000220, 0x1c000223, 0x21020220, 0x27020223, 0x2b022220,
+	0x2f022222, 0x34022225, 0x3a02222a, 0x3e02222c, 0x4202242a,
+	0x4702244a, 0x4b02244c, 0x4e02246c, 0x5302266c, 0x5702286c,
+	0x5c04286b, 0x61042a6c, 0x66062a6c, 0x6b062e6c, 0x7006308c,
+	0x730a308a, 0x770a308c, 0x770a308c, 0x770a308c, 0x770a308c,
+	0x770a308c, 0x770a308c, 0x770a308c, 0x00800000, 0x06800003,
+	0x0a800020, 0x10800023, 0x16800220, 0x1c800223, 0x21820220,
+	0x27820223, 0x2b822220, 0x2f822222, 0x34822225, 0x3a82222a,
+	0x3e82222c, 0x4282242a, 0x4782244a, 0x4b82244c, 0x4e82246c,
+	0x5382266c, 0x5782286c, 0x5c84286b, 0x61842a6c, 0x66862a6c,
+	0x6b862e6c, 0x7086308c, 0x738a308a, 0x778a308c, 0x778a308c,
+	0x778a308c, 0x778a308c, 0x778a308c, 0x778a308c, 0x778a308c,
+	0x012492d4, 0x60001a61, 0x6db6db6c, 0x012492d4, 0x60001a61,
+	0x6db6db6c, 0x012492d4, 0x60001a61, 0x6db6db6c
+};
+
+static const uint32_t ar9380_2_0_tx_gain_vals_2g[] = {
+	0x000050d9, 0x00000000, 0x04000002, 0x08000004, 0x0b000200,
+	0x0f000202, 0x12000400, 0x16000402, 0x19000404, 0x1c000603,
+	0x21000a02, 0x25000a04, 0x28000a20, 0x2c000e20, 0x30000e22,
+	0x34000e24, 0x38001640, 0x3c001660, 0x3f001861, 0x43001a81,
+	0x47001a83, 0x4a001c84, 0x4e001ce3, 0x52001ce5, 0x56001ce9,
+	0x5a001ceb, 0x5d001eec, 0x5d001eec, 0x5d001eec, 0x5d001eec,
+	0x5d001eec, 0x5d001eec, 0x5d001eec, 0x00800000, 0x04800002,
+	0x08800004, 0x0b800200, 0x0f800202, 0x12800400, 0x16800402,
+	0x19800404, 0x1c800603, 0x21800a02, 0x25800a04, 0x28800a20,
+	0x2c800e20, 0x30800e22, 0x34800e24, 0x38801640, 0x3c801660,
+	0x3f801861, 0x43801a81, 0x47801a83, 0x4a801c84, 0x4e801ce3,
+	0x52801ce5, 0x56801ce9, 0x5a801ceb, 0x5d801eec, 0x5d801eec,
+	0x5d801eec, 0x5d801eec, 0x5d801eec, 0x5d801eec, 0x5d801eec,
+	0x012492d4, 0x60001a61, 0x6db6db6c, 0x012492d4, 0x60001a61,
+	0x6db6db6c, 0x012492d4, 0x60001a61, 0x6db6db6c
+};
+
+static const struct athn_gain ar9380_2_0_tx_gain = {
+	nitems(ar9380_2_0_tx_gain_regs),
+	ar9380_2_0_tx_gain_regs,
+	ar9380_2_0_tx_gain_vals_5g,
+	ar9380_2_0_tx_gain_vals_2g
+};
+
+/*
+ * AR9380 2.0 high ob/db Tx gains.
+ */
+static const uint32_t ar9380_2_0_tx_gain_high_ob_db_vals_5g[] = {
+	0x000050d9, 0x00002220, 0x06002223, 0x0a022220, 0x0f022223,
+	0x14022620, 0x18022622, 0x1b022822, 0x20022842, 0x22022c41,
+	0x28023042, 0x2c023044, 0x2f023644, 0x34025643, 0x38025a44,
+	0x3b025e45, 0x41025e4a, 0x48025e6c, 0x4e025e8e, 0x53025eb2,
+	0x59025eb5, 0x5f025ef6, 0x62025f56, 0x66027f56, 0x6a029f56,
+	0x70049f56, 0x7504ff56, 0x7504ff56, 0x7504ff56, 0x7504ff56,
+	0x7504ff56, 0x7504ff56, 0x7504ff56, 0x00802220, 0x06802223,
+	0x0a822220, 0x0f822223, 0x14822620, 0x18822622, 0x1b822822,
+	0x20822842, 0x22822c41, 0x28823042, 0x2c823044, 0x2f823644,
+	0x34825643, 0x38825a44, 0x3b825e45, 0x41825e4a, 0x48825e6c,
+	0x4e825e8e, 0x53825eb2, 0x59825eb5, 0x5f825ef6, 0x62825f56,
+	0x66827f56, 0x6a829f56, 0x70849f56, 0x7584ff56, 0x7584ff56,
+	0x7584ff56, 0x7584ff56, 0x7584ff56, 0x7584ff56, 0x7584ff56,
+	0x056db2e4, 0x8e481a61, 0x6db6db6c, 0x056db2e4, 0x8e481a61,
+	0x6db6db6c, 0x056db2e4, 0x8e481a61, 0x6db6db6c
+};
+
+static const uint32_t ar9380_2_0_tx_gain_high_ob_db_vals_2g[] = {
+	0x000050d9, 0x00000000, 0x04000002, 0x08000004, 0x0b000200,
+	0x0f000202, 0x11000400, 0x15000402, 0x19000404, 0x1b000603,
+	0x1f000a02, 0x23000a04, 0x26000a20, 0x2a000e20, 0x2e000e22,
+	0x31000e24, 0x34001640, 0x38001660, 0x3b001861, 0x3e001a81,
+	0x42001a83, 0x44001c84, 0x48001ce3, 0x4c001ce5, 0x50001ce9,
+	0x54001ceb, 0x56001eec, 0x56001eec, 0x56001eec, 0x56001eec,
+	0x56001eec, 0x56001eec, 0x56001eec, 0x00800000, 0x04800002,
+	0x08800004, 0x0b800200, 0x0f800202, 0x11800400, 0x15800402,
+	0x19800404, 0x1b800603, 0x1f800a02, 0x23800a04, 0x26800a20,
+	0x2a800e20, 0x2e800e22, 0x31800e24, 0x34801640, 0x38801660,
+	0x3b801861, 0x3e801a81, 0x42801a83, 0x44801c84, 0x48801ce3,
+	0x4c801ce5, 0x50801ce9, 0x54801ceb, 0x56801eec, 0x56801eec,
+	0x56801eec, 0x56801eec, 0x56801eec, 0x56801eec, 0x56801eec,
+	0x056db2e4, 0x8e481a61, 0x6db6db6c, 0x056db2e4, 0x8e481a61,
+	0x6db6db6c, 0x056db2e4, 0x8e481a61, 0x6db6db6c
+};
+
+static const struct athn_gain ar9380_2_0_tx_gain_high_ob_db = {
+	nitems(ar9380_2_0_tx_gain_regs),
+	ar9380_2_0_tx_gain_regs,
+	ar9380_2_0_tx_gain_high_ob_db_vals_5g,
+	ar9380_2_0_tx_gain_high_ob_db_vals_2g
+};
+
+/*
+ * AR9380 2.0 low ob/db Tx gains.
+ */
+static const uint32_t ar9380_2_0_tx_gain_low_ob_db_vals_5g[] = {
+	0x000050d9, 0x00000000, 0x06000003, 0x0a000020, 0x10000023,
+	0x16000220, 0x1c000223, 0x21020220, 0x27020223, 0x2b022220,
+	0x2f022222, 0x34022225, 0x3a02222a, 0x3e02222c, 0x4202242a,
+	0x4702244a, 0x4b02244c, 0x4e02246c, 0x5302266c, 0x5702286c,
+	0x5c04286b, 0x61042a6c, 0x66062a6c, 0x6b062e6c, 0x7006308c,
+	0x730a308a, 0x770a308c, 0x770a308c, 0x770a308c, 0x770a308c,
+	0x770a308c, 0x770a308c, 0x770a308c, 0x00800000, 0x06800003,
+	0x0a800020, 0x10800023, 0x16800220, 0x1c800223, 0x21820220,
+	0x27820223, 0x2b822220, 0x2f822222, 0x34822225, 0x3a82222a,
+	0x3e82222c, 0x4282242a, 0x4782244a, 0x4b82244c, 0x4e82246c,
+	0x5382266c, 0x5782286c, 0x5c84286b, 0x61842a6c, 0x66862a6c,
+	0x6b862e6c, 0x7086308c, 0x738a308a, 0x778a308c, 0x778a308c,
+	0x778a308c, 0x778a308c, 0x778a308c, 0x778a308c, 0x778a308c,
+	0x012492d4, 0x64001a61, 0x6db6db6c, 0x012492d4, 0x64001a61,
+	0x6db6db6c, 0x012492d4, 0x64001a61, 0x6db6db6c
+};
+
+static const uint32_t ar9380_2_0_tx_gain_low_ob_db_vals_2g[] = {
+	0x000050d9, 0x00000000, 0x04000002, 0x08000004, 0x0b000200,
+	0x0f000202, 0x12000400, 0x16000402, 0x19000404, 0x1c000603,
+	0x21000a02, 0x25000a04, 0x28000a20, 0x2c000e20, 0x30000e22,
+	0x34000e24, 0x38001640, 0x3c001660, 0x3f001861, 0x43001a81,
+	0x47001a83, 0x4a001c84, 0x4e001ce3, 0x52001ce5, 0x56001ce9,
+	0x5a001ceb, 0x5d001eec, 0x5d001eec, 0x5d001eec, 0x5d001eec,
+	0x5d001eec, 0x5d001eec, 0x5d001eec, 0x00800000, 0x04800002,
+	0x08800004, 0x0b800200, 0x0f800202, 0x12800400, 0x16800402,
+	0x19800404, 0x1c800603, 0x21800a02, 0x25800a04, 0x28800a20,
+	0x2c800e20, 0x30800e22, 0x34800e24, 0x38801640, 0x3c801660,
+	0x3f801861, 0x43801a81, 0x47801a83, 0x4a801c84, 0x4e801ce3,
+	0x52801ce5, 0x56801ce9, 0x5a801ceb, 0x5d801eec, 0x5d801eec,
+	0x5d801eec, 0x5d801eec, 0x5d801eec, 0x5d801eec, 0x5d801eec,
+	0x012492d4, 0x64001a61, 0x6db6db6c, 0x012492d4, 0x64001a61,
+	0x6db6db6c, 0x012492d4, 0x64001a61, 0x6db6db6c
+};
+
+static const struct athn_gain ar9380_2_0_tx_gain_low_ob_db = {
+	nitems(ar9380_2_0_tx_gain_regs),
+	ar9380_2_0_tx_gain_regs,
+	ar9380_2_0_tx_gain_low_ob_db_vals_5g,
+	ar9380_2_0_tx_gain_low_ob_db_vals_2g
+};
+
+/*
+ * AR9380 2.0 Rx gains.
+ */
+static const uint16_t ar9380_2_0_rx_gain_regs[] = {
+	P(0x0a000), P(0x0a004), P(0x0a008), P(0x0a00c), P(0x0a010),
+	P(0x0a014), P(0x0a018), P(0x0a01c), P(0x0a020), P(0x0a024),
+	P(0x0a028), P(0x0a02c), P(0x0a030), P(0x0a034), P(0x0a038),
+	P(0x0a03c), P(0x0a040), P(0x0a044), P(0x0a048), P(0x0a04c),
+	P(0x0a050), P(0x0a054), P(0x0a058), P(0x0a05c), P(0x0a060),
+	P(0x0a064), P(0x0a068), P(0x0a06c), P(0x0a070), P(0x0a074),
+	P(0x0a078), P(0x0a07c), P(0x0a080), P(0x0a084), P(0x0a088),
+	P(0x0a08c), P(0x0a090), P(0x0a094), P(0x0a098), P(0x0a09c),
+	P(0x0a0a0), P(0x0a0a4), P(0x0a0a8), P(0x0a0ac), P(0x0a0b0),
+	P(0x0a0b4), P(0x0a0b8), P(0x0a0bc), P(0x0a0c0), P(0x0a0c4),
+	P(0x0a0c8), P(0x0a0cc), P(0x0a0d0), P(0x0a0d4), P(0x0a0d8),
+	P(0x0a0dc), P(0x0a0e0), P(0x0a0e4), P(0x0a0e8), P(0x0a0ec),
+	P(0x0a0f0), P(0x0a0f4), P(0x0a0f8), P(0x0a0fc), P(0x0a100),
+	P(0x0a104), P(0x0a108), P(0x0a10c), P(0x0a110), P(0x0a114),
+	P(0x0a118), P(0x0a11c), P(0x0a120), P(0x0a124), P(0x0a128),
+	P(0x0a12c), P(0x0a130), P(0x0a134), P(0x0a138), P(0x0a13c),
+	P(0x0a140), P(0x0a144), P(0x0a148), P(0x0a14c), P(0x0a150),
+	P(0x0a154), P(0x0a158), P(0x0a15c), P(0x0a160), P(0x0a164),
+	P(0x0a168), P(0x0a16c), P(0x0a170), P(0x0a174), P(0x0a178),
+	P(0x0a17c), P(0x0a180), P(0x0a184), P(0x0a188), P(0x0a18c),
+	P(0x0a190), P(0x0a194), P(0x0a198), P(0x0a19c), P(0x0a1a0),
+	P(0x0a1a4), P(0x0a1a8), P(0x0a1ac), P(0x0a1b0), P(0x0a1b4),
+	P(0x0a1b8), P(0x0a1bc), P(0x0a1c0), P(0x0a1c4), P(0x0a1c8),
+	P(0x0a1cc), P(0x0a1d0), P(0x0a1d4), P(0x0a1d8), P(0x0a1dc),
+	P(0x0a1e0), P(0x0a1e4), P(0x0a1e8), P(0x0a1ec), P(0x0a1f0),
+	P(0x0a1f4), P(0x0a1f8), P(0x0a1fc), P(0x0b000), P(0x0b004),
+	P(0x0b008), P(0x0b00c), P(0x0b010), P(0x0b014), P(0x0b018),
+	P(0x0b01c), P(0x0b020), P(0x0b024), P(0x0b028), P(0x0b02c),
+	P(0x0b030), P(0x0b034), P(0x0b038), P(0x0b03c), P(0x0b040),
+	P(0x0b044), P(0x0b048), P(0x0b04c), P(0x0b050), P(0x0b054),
+	P(0x0b058), P(0x0b05c), P(0x0b060), P(0x0b064), P(0x0b068),
+	P(0x0b06c), P(0x0b070), P(0x0b074), P(0x0b078), P(0x0b07c),
+	P(0x0b080), P(0x0b084), P(0x0b088), P(0x0b08c), P(0x0b090),
+	P(0x0b094), P(0x0b098), P(0x0b09c), P(0x0b0a0), P(0x0b0a4),
+	P(0x0b0a8), P(0x0b0ac), P(0x0b0b0), P(0x0b0b4), P(0x0b0b8),
+	P(0x0b0bc), P(0x0b0c0), P(0x0b0c4), P(0x0b0c8), P(0x0b0cc),
+	P(0x0b0d0), P(0x0b0d4), P(0x0b0d8), P(0x0b0dc), P(0x0b0e0),
+	P(0x0b0e4), P(0x0b0e8), P(0x0b0ec), P(0x0b0f0), P(0x0b0f4),
+	P(0x0b0f8), P(0x0b0fc), P(0x0b100), P(0x0b104), P(0x0b108),
+	P(0x0b10c), P(0x0b110), P(0x0b114), P(0x0b118), P(0x0b11c),
+	P(0x0b120), P(0x0b124), P(0x0b128), P(0x0b12c), P(0x0b130),
+	P(0x0b134), P(0x0b138), P(0x0b13c), P(0x0b140), P(0x0b144),
+	P(0x0b148), P(0x0b14c), P(0x0b150), P(0x0b154), P(0x0b158),
+	P(0x0b15c), P(0x0b160), P(0x0b164), P(0x0b168), P(0x0b16c),
+	P(0x0b170), P(0x0b174), P(0x0b178), P(0x0b17c), P(0x0b180),
+	P(0x0b184), P(0x0b188), P(0x0b18c), P(0x0b190), P(0x0b194),
+	P(0x0b198), P(0x0b19c), P(0x0b1a0), P(0x0b1a4), P(0x0b1a8),
+	P(0x0b1ac), P(0x0b1b0), P(0x0b1b4), P(0x0b1b8), P(0x0b1bc),
+	P(0x0b1c0), P(0x0b1c4), P(0x0b1c8), P(0x0b1cc), P(0x0b1d0),
+	P(0x0b1d4), P(0x0b1d8), P(0x0b1dc), P(0x0b1e0), P(0x0b1e4),
+	P(0x0b1e8), P(0x0b1ec), P(0x0b1f0), P(0x0b1f4), P(0x0b1f8),
+	P(0x0b1fc)
+};
+
+static const uint32_t ar9380_2_0_rx_gain_vals[] = {
+	0x00010000, 0x00030002, 0x00050004, 0x00810080, 0x01800082,
+	0x01820181, 0x01840183, 0x01880185, 0x018a0189, 0x02850284,
+	0x02890288, 0x028b028a, 0x028d028c, 0x02910290, 0x02930292,
+	0x03910390, 0x03930392, 0x03950394, 0x00000396, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x28282828, 0x21212128, 0x21212121,
+	0x1c1c1c21, 0x1c1c1c1c, 0x17171c1c, 0x02020212, 0x02020202,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x001f0000, 0x011f0100,
+	0x011d011e, 0x011b011c, 0x02030204, 0x02010202, 0x021f0200,
+	0x021d021e, 0x03010302, 0x031f0300, 0x0402031e, 0x04000401,
+	0x041e041f, 0x05010502, 0x051f0500, 0x0602051e, 0x06000601,
+	0x061e061f, 0x0703061d, 0x07010702, 0x00000700, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x001f0000, 0x011f0100, 0x011d011e, 0x011b011c, 0x02030204,
+	0x02010202, 0x021f0200, 0x021d021e, 0x03010302, 0x031f0300,
+	0x0402031e, 0x04000401, 0x041e041f, 0x05010502, 0x051f0500,
+	0x0602051e, 0x06000601, 0x061e061f, 0x0703061d, 0x07010702,
+	0x00000700, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000396,
+	0x00000396, 0x00000396, 0x00000196, 0x00010000, 0x00030002,
+	0x00050004, 0x00810080, 0x00830082, 0x01810180, 0x01830182,
+	0x01850184, 0x02810280, 0x02830282, 0x02850284, 0x02890288,
+	0x028b028a, 0x0388028c, 0x038a0389, 0x038c038b, 0x0390038d,
+	0x03920391, 0x03940393, 0x03960395, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x32323232, 0x2f2f3232, 0x23282a2d, 0x1c1e2123, 0x14171919,
+	0x0e0e1214, 0x03050707, 0x00030303, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x003f0020, 0x00400041, 0x0140005f, 0x0160015f,
+	0x017e017f, 0x02410242, 0x025f0240, 0x027f0260, 0x0341027e,
+	0x035f0340, 0x037f0360, 0x04400441, 0x0460045f, 0x0541047f,
+	0x055f0540, 0x057f0560, 0x06400641, 0x0660065f, 0x067e067f,
+	0x07410742, 0x075f0740, 0x077f0760, 0x07800781, 0x07a0079f,
+	0x07c107bf, 0x000007c0, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x003f0020, 0x00400041,
+	0x0140005f, 0x0160015f, 0x017e017f, 0x02410242, 0x025f0240,
+	0x027f0260, 0x0341027e, 0x035f0340, 0x037f0360, 0x04400441,
+	0x0460045f, 0x0541047f, 0x055f0540, 0x057f0560, 0x06400641,
+	0x0660065f, 0x067e067f, 0x07410742, 0x075f0740, 0x077f0760,
+	0x07800781, 0x07a0079f, 0x07c107bf, 0x000007c0, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000396, 0x00000396, 0x00000396,
+	0x00000196
+};
+
+static const struct athn_gain ar9380_2_0_rx_gain = {
+	nitems(ar9380_2_0_rx_gain_regs),
+	ar9380_2_0_rx_gain_regs,
+	ar9380_2_0_rx_gain_vals,
+	ar9380_2_0_rx_gain_vals
+};
+
+/*
+ * AR9380 2.0 without external low-noise amplifier Rx gains.
+ */
+static const uint32_t ar9380_2_0_rx_gain_wo_xlna_vals[] = {
+	0x00010000, 0x00030002, 0x00050004, 0x00810080, 0x01800082,
+	0x01820181, 0x01840183, 0x01880185, 0x018a0189, 0x02850284,
+	0x02890288, 0x03850384, 0x03890388, 0x038b038a, 0x038d038c,
+	0x03910390, 0x03930392, 0x03950394, 0x00000396, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x28282828, 0x28282828, 0x28282828,
+	0x28282828, 0x28282828, 0x21212128, 0x171c1c1c, 0x02020212,
+	0x00000202, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x001f0000, 0x011f0100,
+	0x011d011e, 0x011b011c, 0x02030204, 0x02010202, 0x021f0200,
+	0x021d021e, 0x03010302, 0x031f0300, 0x0402031e, 0x04000401,
+	0x041e041f, 0x05010502, 0x051f0500, 0x0602051e, 0x06000601,
+	0x061e061f, 0x0703061d, 0x07010702, 0x00000700, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x001f0000, 0x011f0100, 0x011d011e, 0x011b011c, 0x02030204,
+	0x02010202, 0x021f0200, 0x021d021e, 0x03010302, 0x031f0300,
+	0x0402031e, 0x04000401, 0x041e041f, 0x05010502, 0x051f0500,
+	0x0602051e, 0x06000601, 0x061e061f, 0x0703061d, 0x07010702,
+	0x00000700, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000396,
+	0x00000396, 0x00000396, 0x00000296, 0x00010000, 0x00030002,
+	0x00050004, 0x00810080, 0x00830082, 0x01810180, 0x01830182,
+	0x01850184, 0x02810280, 0x02830282, 0x02850284, 0x02890288,
+	0x028b028a, 0x0388028c, 0x038a0389, 0x038c038b, 0x0390038d,
+	0x03920391, 0x03940393, 0x03960395, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x32323232, 0x2f2f3232, 0x23282a2d, 0x1c1e2123, 0x14171919,
+	0x0e0e1214, 0x03050707, 0x00030303, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x003f0020, 0x00400041, 0x0140005f, 0x0160015f,
+	0x017e017f, 0x02410242, 0x025f0240, 0x027f0260, 0x0341027e,
+	0x035f0340, 0x037f0360, 0x04400441, 0x0460045f, 0x0541047f,
+	0x055f0540, 0x057f0560, 0x06400641, 0x0660065f, 0x067e067f,
+	0x07410742, 0x075f0740, 0x077f0760, 0x07800781, 0x07a0079f,
+	0x07c107bf, 0x000007c0, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x003f0020, 0x00400041,
+	0x0140005f, 0x0160015f, 0x017e017f, 0x02410242, 0x025f0240,
+	0x027f0260, 0x0341027e, 0x035f0340, 0x037f0360, 0x04400441,
+	0x0460045f, 0x0541047f, 0x055f0540, 0x057f0560, 0x06400641,
+	0x0660065f, 0x067e067f, 0x07410742, 0x075f0740, 0x077f0760,
+	0x07800781, 0x07a0079f, 0x07c107bf, 0x000007c0, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000396, 0x00000396, 0x00000396,
+	0x00000196
+};
+
+static const struct athn_gain ar9380_2_0_rx_gain_wo_xlna = {
+	nitems(ar9380_2_0_rx_gain_regs),
+	ar9380_2_0_rx_gain_regs,
+	ar9380_2_0_rx_gain_wo_xlna_vals,
+	ar9380_2_0_rx_gain_wo_xlna_vals
+};
+
+/*
+ * Serializer/Deserializer programming.
+ */
+static const uint32_t ar9380_2_0_serdes[] = {
+	0x08212e5e,
+	0x0008003b
+};
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c
index 0bddedd1e54..b687eb8979c 100644
--- a/sys/dev/ic/athn.c
+++ b/sys/dev/ic/athn.c
@@ -1,8 +1,8 @@
-/*	$OpenBSD: athn.c,v 1.36 2010/04/20 22:05:43 tedu Exp $	*/
+/*	$OpenBSD: athn.c,v 1.37 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
- * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2008-2010 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -70,21 +70,11 @@ void		athn_radiotap_attach(struct athn_softc *);
 void		athn_get_chanlist(struct athn_softc *);
 const char *	athn_get_mac_name(struct athn_softc *);
 const char *	athn_get_rf_name(struct athn_softc *);
-int		athn_tx_alloc(struct athn_softc *);
-void		athn_tx_free(struct athn_softc *);
-int		athn_rx_alloc(struct athn_softc *);
-void		athn_rx_free(struct athn_softc *);
-void		athn_rx_start(struct athn_softc *);
 void		athn_led_init(struct athn_softc *);
 void		athn_btcoex_init(struct athn_softc *);
 void		athn_btcoex_enable(struct athn_softc *);
 void		athn_btcoex_disable(struct athn_softc *);
-void		athn_rfsilent_init(struct athn_softc *);
 void		athn_set_rxfilter(struct athn_softc *, uint32_t);
-int		athn_gpio_read(struct athn_softc *, int);
-void		athn_gpio_write(struct athn_softc *, int, int);
-void		athn_gpio_config_output(struct athn_softc *, int, int);
-void		athn_gpio_config_input(struct athn_softc *, int);
 void		athn_get_chipid(struct athn_softc *);
 int		athn_reset_power_on(struct athn_softc *);
 int		athn_reset(struct athn_softc *, int);
@@ -95,19 +85,11 @@ void		athn_set_power_sleep(struct athn_softc *);
 void		athn_write_serdes(struct athn_softc *, const uint32_t [9]);
 void		athn_config_pcie(struct athn_softc *);
 void		athn_config_nonpcie(struct athn_softc *);
-uint8_t		athn_get_rf_rev(struct athn_softc *);
 int		athn_set_chan(struct athn_softc *, struct ieee80211_channel *,
 		    struct ieee80211_channel *);
 int		athn_switch_chan(struct athn_softc *,
 		    struct ieee80211_channel *, struct ieee80211_channel *);
 void		athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);
-void		athn_set_delta_slope(struct athn_softc *,
-		    struct ieee80211_channel *, struct ieee80211_channel *);
-void		athn_set_phy(struct athn_softc *, struct ieee80211_channel *,
-		    struct ieee80211_channel *);
-int		athn_read_rom_word(struct athn_softc *, uint32_t, uint16_t *);
-int		athn_read_rom(struct athn_softc *);
-void		athn_swap_rom(struct athn_softc *);
 void		athn_reset_key(struct athn_softc *, int);
 int		athn_set_key(struct ieee80211com *, struct ieee80211_node *,
 		    struct ieee80211_key *);
@@ -115,37 +97,26 @@ void		athn_delete_key(struct ieee80211com *, struct ieee80211_node *,
 		    struct ieee80211_key *);
 void		athn_iter_func(void *, struct ieee80211_node *);
 void		athn_calib_to(void *);
-void		athn_do_calib(struct athn_softc *);
 int		athn_init_calib(struct athn_softc *,
 		    struct ieee80211_channel *, struct ieee80211_channel *);
-void		athn_init_chains(struct athn_softc *);
-uint8_t		athn_get_vpd(uint8_t, const uint8_t *, const uint8_t *, int);
+uint8_t		athn_chan2fbin(struct ieee80211_channel *);
 int		athn_interpolate(int, int, int, int, int);
-void		athn_init_baseband(struct athn_softc *);
+void		athn_get_pier_ival(uint8_t, const uint8_t *, int, int *,
+		    int *);
 void		athn_init_dma(struct athn_softc *);
+void		athn_rx_start(struct athn_softc *);
 void		athn_inc_tx_trigger_level(struct athn_softc *);
 int		athn_stop_rx_dma(struct athn_softc *);
 int		athn_rx_abort(struct athn_softc *);
+void		athn_tx_reclaim(struct athn_softc *, int);
 int		athn_tx_pending(struct athn_softc *, int);
 void		athn_stop_tx_dma(struct athn_softc *, int);
-void		athn_tx_reclaim(struct athn_softc *, int);
-void		athn_rx_radiotap(struct athn_softc *, struct mbuf *,
-		    struct ar_rx_desc *);
-void		athn_rx_intr(struct athn_softc *);
-int		athn_tx_process(struct athn_softc *, int);
-void		athn_tx_intr(struct athn_softc *);
 int		athn_txtime(struct athn_softc *, int, int, u_int);
-int		athn_tx(struct athn_softc *, struct mbuf *,
-		    struct ieee80211_node *);
 void		athn_set_beacon_timers(struct athn_softc *);
-void		athn_set_rf_mode(struct athn_softc *,
-		    struct ieee80211_channel *);
 void		athn_set_opmode(struct athn_softc *);
 void		athn_set_bss(struct athn_softc *, struct ieee80211_node *);
 void		athn_enable_interrupts(struct athn_softc *);
 void		athn_disable_interrupts(struct athn_softc *);
-void		athn_hw_init(struct athn_softc *, struct ieee80211_channel *,
-		    struct ieee80211_channel *);
 void		athn_init_qos(struct athn_softc *);
 int		athn_hw_reset(struct athn_softc *, struct ieee80211_channel *,
 		    struct ieee80211_channel *);
@@ -165,30 +136,29 @@ int		athn_ioctl(struct ifnet *, u_long, caddr_t);
 int		athn_init(struct ifnet *);
 void		athn_stop(struct ifnet *, int);
 void		athn_init_tx_queues(struct athn_softc *);
-void		athn_calib_iq(struct athn_softc *);
-void		athn_calib_adc_gain(struct athn_softc *);
-void		athn_calib_adc_dc_off(struct athn_softc *);
-void		athn_read_noisefloor(struct athn_softc *, int16_t *,
-		    int16_t *);
-void		athn_get_noisefloor(struct athn_softc *,
-		    struct ieee80211_channel *);
-void		athn_write_noisefloor(struct athn_softc *, int16_t *,
-		    int16_t *);
-void		athn_bb_load_noisefloor(struct athn_softc *);
-void		athn_noisefloor_calib(struct athn_softc *);
 int32_t		athn_ani_get_rssi(struct athn_softc *);
-void		athn_ani_set_noise_immunity_level(struct athn_softc *, int);
-void		athn_ani_ena_ofdm_weak_signal(struct athn_softc *);
-void		athn_ani_dis_ofdm_weak_signal(struct athn_softc *);
-void		athn_ani_set_cck_weak_signal(struct athn_softc *, int);
-void		athn_ani_set_firstep_level(struct athn_softc *, int);
-void		athn_ani_set_spur_immunity_level(struct athn_softc *, int);
 void		athn_ani_ofdm_err_trigger(struct athn_softc *);
 void		athn_ani_cck_err_trigger(struct athn_softc *);
 void		athn_ani_lower_immunity(struct athn_softc *);
 void		athn_ani_restart(struct athn_softc *);
 void		athn_ani_monitor(struct athn_softc *);
 
+/* Extern functions. */
+int		ar5416_attach(struct athn_softc *);
+int		ar9280_attach(struct athn_softc *);
+int		ar9285_attach(struct athn_softc *);
+int		ar9287_attach(struct athn_softc *);
+int		ar9380_attach(struct athn_softc *);
+int		ar5416_init_calib(struct athn_softc *,
+		    struct ieee80211_channel *, struct ieee80211_channel *);
+int		ar9285_1_2_init_calib(struct athn_softc *,
+		    struct ieee80211_channel *, struct ieee80211_channel *);
+int		ar9003_init_calib(struct athn_softc *);
+void		ar9285_pa_calib(struct athn_softc *);
+void		ar9287_1_2_enable_async_fifo(struct athn_softc *);
+void		ar9287_1_2_setup_async_fifo(struct athn_softc *);
+void		ar9003_reset_txsring(struct athn_softc *);
+
 struct cfdriver athn_cd = {
 	NULL, "athn", DV_IFNET
 };
@@ -198,8 +168,6 @@ athn_attach(struct athn_softc *sc)
 {
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &ic->ic_if;
-	struct ar_base_eep_header *base;
-	uint8_t eep_ver, kc_entries_exp;
 	int error;
 
 	if ((error = athn_reset_power_on(sc)) != 0) {
@@ -207,73 +175,44 @@ athn_attach(struct athn_softc *sc)
 		return (error);
 	}
 
-	if (AR_SREV_5416(sc) || AR_SREV_9160(sc))
-		ar5416_attach(sc);
-	else if (AR_SREV_9280(sc))
-		ar9280_attach(sc);
-	else if (AR_SREV_9285(sc))
-		ar9285_attach(sc);
-	else if (AR_SREV_9287(sc))
-		ar9287_attach(sc);
-
 	if ((error = athn_set_power_awake(sc)) != 0) {
 		printf(": could not wakeup chip\n");
 		return (error);
 	}
 
-	/* Retrieve PHY Revision. */
-	sc->phy_rev = AR_READ(sc, AR_PHY_CHIP_ID);
-
-	if (!(sc->flags & ATHN_FLAG_PCIE))
-		athn_config_nonpcie(sc);
-	else
-		athn_config_pcie(sc);
-
-	/* Allow access to analog chips. */
-	AR_WRITE(sc, AR_PHY(0), 0x00000007);
-	/* Get RF revision. */
-	sc->rf_rev = athn_get_rf_rev(sc);
-
-	/* Read entire ROM content. */
-	if ((error = athn_read_rom(sc)) != 0) {
-		printf(": could not read ROM\n");
+	if (AR_SREV_5416(sc) || AR_SREV_9160(sc))
+		error = ar5416_attach(sc);
+	else if (AR_SREV_9280(sc))
+		error = ar9280_attach(sc);
+	else if (AR_SREV_9285(sc))
+		error = ar9285_attach(sc);
+	else if (AR_SREV_9287(sc))
+		error = ar9287_attach(sc);
+	else if (AR_SREV_9380(sc))
+		error = ar9380_attach(sc);
+	if (error != 0) {
+		printf(": could not attach chip\n");
 		return (error);
 	}
-	base = sc->eep;
-
-	eep_ver = (base->version >> 12) & 0xf;
-	sc->eep_rev = (base->version & 0xfff);
-	if (eep_ver != AR_EEP_VER || sc->eep_rev == 0) {
-		printf(": unsupported ROM version %d.%d\n",  eep_ver,
-		    sc->eep_rev);
-		return (EINVAL);
-	}
-	sc->ops.setup(sc);
 
 	/* We can put the chip in sleep state now. */
 	athn_set_power_sleep(sc);
 
-	IEEE80211_ADDR_COPY(ic->ic_myaddr, base->macAddr);
+	error = sc->ops.dma_alloc(sc);
+	if (error != 0) {
+		printf("%s: could not allocate DMA resources\n",
+		    sc->sc_dev.dv_xname);
+		return (error);
+	}
+
 	printf(", address %s\n", ether_sprintf(ic->ic_myaddr));
 
-	/* Check if we have a hardware radio switch. */
-	if (base->rfSilent & AR_EEP_RFSILENT_ENABLED) {
-		sc->flags |= ATHN_FLAG_RFSILENT;
-		/* Get GPIO pin used by hardware radio switch. */
-		sc->rfsilent_pin = MS(base->rfSilent,
-		    AR_EEP_RFSILENT_GPIO_SEL);
-		/* Get polarity of hardware radio switch. */
-		if (base->rfSilent & AR_EEP_RFSILENT_POLARITY)
-			sc->flags |= ATHN_FLAG_RFSILENT_REVERSED;
-		DPRINTF(("Found RF switch connected to GPIO pin %d\n",
+	if (sc->flags & ATHN_FLAG_RFSILENT) {
+		DPRINTF(("found RF switch connected to GPIO pin %d\n",
 		    sc->rfsilent_pin));
 	}
-
-	/* Get the number of HW key cache entries. */
-	kc_entries_exp = MS(base->deviceCap, AR_EEP_DEVCAP_KC_ENTRIES);
-	sc->kc_entries = (kc_entries_exp != 0) ?
-	    1 << kc_entries_exp : AR_KEYTABLE_SIZE;
 	DPRINTF(("%d key cache entries\n", sc->kc_entries));
+
 	/*
 	 * In HostAP mode, the number of STAs that we can handle is
 	 * limited by the number of entries in the HW key cache.
@@ -284,14 +223,6 @@ athn_attach(struct athn_softc *sc)
 	DPRINTF(("using %s loop power control\n",
 	    (sc->flags & ATHN_FLAG_OLPC) ? "open" : "closed"));
 
-	sc->txchainmask = base->txMask;
-	if (sc->mac_ver == AR_SREV_VERSION_5416_PCI &&
-	    !(base->opCapFlags & AR_OPFLAGS_11A)) {
-		/* NB: Linux has a bug here. */
-		/* For single-band AR5416 PCI, use GPIO pin 0. */
-		sc->rxchainmask = athn_gpio_read(sc, 0) ? 0x5 : 0x7;
-	} else
-		sc->rxchainmask = base->rxMask;
 	DPRINTF(("txchainmask=0x%x rxchainmask=0x%x\n",
 	    sc->txchainmask, sc->rxchainmask));
 	/* Count the number of bits set (in lowest 3 bits). */
@@ -304,19 +235,6 @@ athn_attach(struct athn_softc *sc)
 	    ((sc->rxchainmask >> 1) & 1) +
 	    ((sc->rxchainmask >> 0) & 1);
 
-	error = athn_tx_alloc(sc);
-	if (error != 0) {
-		printf("%s: could not allocate Tx DMA resources\n",
-		    sc->sc_dev.dv_xname);
-		return (error);
-	}
-	error = athn_rx_alloc(sc);
-	if (error != 0) {
-		printf("%s: could not allocate Rx DMA resources\n",
-		    sc->sc_dev.dv_xname);
-		return (error);
-	}
-
 	if (AR_SINGLE_CHIP(sc)) {
 		printf("%s: %s rev %d (%dT%dR), ROM rev %d\n",
 		    sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev,
@@ -348,35 +266,51 @@ athn_attach(struct athn_softc *sc)
 	    IEEE80211_C_PMGT;		/* power saving supported */
 
 #ifndef IEEE80211_NO_HT
-	if (base->opCapFlags & AR_OPFLAGS_11N) {
+	if (sc->flags & ATHN_FLAG_11N) {
+		int i, ntxstreams, nrxstreams;
+
 		/* Set HT capabilities. */
 		ic->ic_htcaps =
 		    IEEE80211_HTCAP_SMPS_DIS |
 		    IEEE80211_HTCAP_CBW20_40 |
 		    IEEE80211_HTCAP_SGI40 |
 		    IEEE80211_HTCAP_DSSSCCK40;
+		if (AR_SREV_9380_10_OR_LATER(sc))
+			ic->ic_htcaps |= IEEE80211_HTCAP_LDPC;
+		if (AR_SREV_9280_10_OR_LATER(sc)) {
+			ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
+			ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT;
+		}
+		ntxstreams = sc->ntxchains;
+		nrxstreams = sc->nrxchains;
+		if (!AR_SREV_9380_10_OR_LATER(sc)) {
+			ntxstreams = MIN(ntxstreams, 2);
+			nrxstreams = MIN(nrxstreams, 2);
+		}
+		/* Set supported HT rates. */
+		for (i = 0; i < nrxstreams; i++)
+			ic->ic_sup_mcs[i] = 0xff;
+		/* Set the "Tx MCS Set Defined" bit. */
+		ic->ic_sup_mcs[12] |= 0x01;
+		if (ntxstreams != nrxstreams) {
+			/* Set "Tx Rx MCS Set Not Equal" bit. */
+			ic->ic_sup_mcs[12] |= 0x02;
+			ic->ic_sup_mcs[12] |= (ntxstreams - 1) << 2;
+		}
 	}
 #endif
 
 	/* Set supported rates. */
-	if (base->opCapFlags & AR_OPFLAGS_11G) {
+	if (sc->flags & ATHN_FLAG_11G) {
 		ic->ic_sup_rates[IEEE80211_MODE_11B] =
 		    ieee80211_std_rateset_11b;
 		ic->ic_sup_rates[IEEE80211_MODE_11G] =
 		    ieee80211_std_rateset_11g;
 	}
-	if (base->opCapFlags & AR_OPFLAGS_11A) {
+	if (sc->flags & ATHN_FLAG_11A) {
 		ic->ic_sup_rates[IEEE80211_MODE_11A] =
 		    ieee80211_std_rateset_11a;
 	}
-#ifndef IEEE80211_NO_HT
-	if (base->opCapFlags & AR_OPFLAGS_11N) {
-		/* Set supported HT rates. */
-		ic->ic_sup_mcs[0] = 0xff;
-		if (sc->nrxchains > 1)
-			ic->ic_sup_mcs[1] = 0xff;
-	}
-#endif
 
 	/* Get the list of auhtorized/supported channels. */
 	athn_get_chanlist(sc);
@@ -425,11 +359,12 @@ athn_detach(struct athn_softc *sc)
 	timeout_del(&sc->scan_to);
 	timeout_del(&sc->calib_to);
 
-	/* Free Tx/Rx DMA resources. */
 	for (qid = 0; qid < ATHN_QID_COUNT; qid++)
 		athn_tx_reclaim(sc, qid);
-	athn_tx_free(sc);
-	athn_rx_free(sc);
+
+	/* Free Tx/Rx DMA resources. */
+	sc->ops.dma_free(sc);
+
 	/* Free ROM copy. */
 	if (sc->eep != NULL)
 		free(sc->eep, M_DEVBUF);
@@ -461,13 +396,11 @@ athn_radiotap_attach(struct athn_softc *sc)
 void
 athn_get_chanlist(struct athn_softc *sc)
 {
-	struct ar_base_eep_header *base = sc->eep;
 	struct ieee80211com *ic = &sc->sc_ic;
 	uint8_t chan;
 	int i;
 
-	/* XXX Regulatory domain. */
-	if (base->opCapFlags & AR_OPFLAGS_11G) {
+	if (sc->flags & ATHN_FLAG_11G) {
 		for (i = 1; i <= 14; i++) {
 			chan = i;
 			ic->ic_channels[chan].ic_freq =
@@ -477,7 +410,7 @@ athn_get_chanlist(struct athn_softc *sc)
 			    IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
 		}
 	}
-	if (base->opCapFlags & AR_OPFLAGS_11A) {
+	if (sc->flags & ATHN_FLAG_11A) {
 		for (i = 0; i < nitems(athn_5ghz_chans); i++) {
 			chan = athn_5ghz_chans[i];
 			ic->ic_channels[chan].ic_freq =
@@ -487,223 +420,14 @@ athn_get_chanlist(struct athn_softc *sc)
 	}
 }
 
-int
-athn_tx_alloc(struct athn_softc *sc)
-{
-	struct athn_tx_buf *bf;
-	bus_size_t size;
-	int error, nsegs, i;
-
-	/*
-	 * Allocate a pool of Tx descriptors shared between all Tx queues.
-	 */
-	size = ATHN_NTXBUFS * ATHN_MAX_SCATTER * sizeof (struct ar_tx_desc);
-
-	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
-	    BUS_DMA_NOWAIT, &sc->map);
-	if (error != 0)
-		goto fail;
-
-	error = bus_dmamem_alloc(sc->sc_dmat, size, 4, 0, &sc->seg, 1,
-	    &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
-	if (error != 0)
-		goto fail;
-
-	error = bus_dmamem_map(sc->sc_dmat, &sc->seg, 1, size,
-	    (caddr_t *)&sc->descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
-	if (error != 0)
-		goto fail;
-
-	error = bus_dmamap_load_raw(sc->sc_dmat, sc->map, &sc->seg, 1, size,
-	    BUS_DMA_NOWAIT);
-	if (error != 0)
-		goto fail;
-
-	SIMPLEQ_INIT(&sc->txbufs);
-	for (i = 0; i < ATHN_NTXBUFS; i++) {
-		bf = &sc->txpool[i];
-
-		error = bus_dmamap_create(sc->sc_dmat, ATHN_TXBUFSZ,
-		    ATHN_MAX_SCATTER, ATHN_TXBUFSZ, 0, BUS_DMA_NOWAIT,
-		    &bf->bf_map);
-		if (error != 0) {
-			printf("%s: could not create Tx buf DMA map\n",
-			    sc->sc_dev.dv_xname);
-			goto fail;
-		}
-
-		bf->bf_descs = &sc->descs[i * ATHN_MAX_SCATTER];
-		bf->bf_daddr = sc->map->dm_segs[0].ds_addr +
-		    i * ATHN_MAX_SCATTER * sizeof (struct ar_tx_desc);
-
-		SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
-	}
-	return (0);
- fail:
-	athn_tx_free(sc);
-	return (error);
-}
-
-void
-athn_tx_free(struct athn_softc *sc)
-{
-	struct athn_tx_buf *bf;
-	int i;
-
-	for (i = 0; i < ATHN_NTXBUFS; i++) {
-		bf = &sc->txpool[i];
-
-		if (bf->bf_map != NULL)
-			bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
-	}
-	/* Free Tx descriptors. */
-	if (sc->map != NULL) {
-		if (sc->descs != NULL) {
-			bus_dmamap_unload(sc->sc_dmat, sc->map);
-			bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->descs,
-			    ATHN_NTXBUFS * ATHN_MAX_SCATTER *
-			    sizeof (struct ar_tx_desc));
-			bus_dmamem_free(sc->sc_dmat, &sc->seg, 1);
-		}
-		bus_dmamap_destroy(sc->sc_dmat, sc->map);
-	}
-}
-
-int
-athn_rx_alloc(struct athn_softc *sc)
-{
-	struct athn_rxq *rxq = &sc->rxq;
-	struct athn_rx_buf *bf;
-	struct ar_rx_desc *ds;
-	bus_size_t size;
-	int error, nsegs, i;
-
-	size = ATHN_NRXBUFS * sizeof (struct ar_rx_desc);
-
-	error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
-	    BUS_DMA_NOWAIT, &rxq->map);
-	if (error != 0)
-		goto fail;
-
-	error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rxq->seg, 1,
-	    &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
-	if (error != 0)
-		goto fail;
-
-	error = bus_dmamem_map(sc->sc_dmat, &rxq->seg, 1, size,
-	    (caddr_t *)&rxq->descs, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
-	if (error != 0)
-		goto fail;
-
-	error = bus_dmamap_load_raw(sc->sc_dmat, rxq->map, &rxq->seg, 1,
-	    size, BUS_DMA_NOWAIT);
-	if (error != 0)
-		goto fail;
-
-	for (i = 0; i < ATHN_NRXBUFS; i++) {
-		bf = &rxq->bf[i];
-		ds = &rxq->descs[i];
-
-		error = bus_dmamap_create(sc->sc_dmat, ATHN_RXBUFSZ, 1,
-		    ATHN_RXBUFSZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
-		    &bf->bf_map);
-		if (error != 0) {
-			printf("%s: could not create Rx buf DMA map\n",
-			    sc->sc_dev.dv_xname);
-			goto fail;
-		}
-		/*
-		 * Assumes MCLGETI returns cache-line-size aligned buffers.
-		 */
-		bf->bf_m = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
-		if (bf->bf_m == NULL) {
-			printf("%s: could not allocate Rx mbuf\n",
-			    sc->sc_dev.dv_xname);
-			error = ENOBUFS;
-			goto fail;
-		}
-
-		error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
-		    mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
-		    BUS_DMA_NOWAIT | BUS_DMA_READ);
-		if (error != 0) {
-			printf("%s: could not DMA map Rx buffer\n",
-			    sc->sc_dev.dv_xname);
-			goto fail;
-		}
-
-		bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
-		    bf->bf_map->dm_mapsize, BUS_DMASYNC_PREREAD);
-
-		bf->bf_desc = ds;
-		bf->bf_daddr = rxq->map->dm_segs[0].ds_addr +
-		    i * sizeof (struct ar_rx_desc);
-	}
-	return (0);
- fail:
-	athn_rx_free(sc);
-	return (error);
-}
-
-void
-athn_rx_free(struct athn_softc *sc)
-{
-	struct athn_rxq *rxq = &sc->rxq;
-	struct athn_rx_buf *bf;
-	int i;
-
-	for (i = 0; i < ATHN_NRXBUFS; i++) {
-		bf = &rxq->bf[i];
-
-		if (bf->bf_map != NULL)
-			bus_dmamap_destroy(sc->sc_dmat, bf->bf_map);
-		if (bf->bf_m != NULL)
-			m_freem(bf->bf_m);
-	}
-	/* Free Rx descriptors. */
-	if (rxq->descs != NULL) {
-		if (rxq->descs != NULL) {
-			bus_dmamap_unload(sc->sc_dmat, rxq->map);
-			bus_dmamem_unmap(sc->sc_dmat, (caddr_t)rxq->descs,
-			    ATHN_NRXBUFS * sizeof (struct ar_rx_desc));
-			bus_dmamem_free(sc->sc_dmat, &rxq->seg, 1);
-		}
-		bus_dmamap_destroy(sc->sc_dmat, rxq->map);
-	}
-}
-
 void
 athn_rx_start(struct athn_softc *sc)
 {
 	struct ieee80211com *ic = &sc->sc_ic;
-	struct athn_rxq *rxq = &sc->rxq;
-	struct athn_rx_buf *bf;
-	struct ar_rx_desc *ds;
 	uint32_t rfilt;
-	int i;
 
-	/* Setup and link Rx descriptors. */
-	SIMPLEQ_INIT(&rxq->head);
-	rxq->lastds = NULL;
-	for (i = 0; i < ATHN_NRXBUFS; i++) {
-		bf = &rxq->bf[i];
-		ds = bf->bf_desc;
-
-		memset(ds, 0, sizeof (*ds));
-		ds->ds_data = bf->bf_map->dm_segs[0].ds_addr;
-		ds->ds_ctl1 = SM(AR_RXC1_BUF_LEN, ATHN_RXBUFSZ);
-
-		if (rxq->lastds != NULL)
-			rxq->lastds->ds_link = bf->bf_daddr;
-		SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
-		rxq->lastds = ds;
-	}
-	bus_dmamap_sync(sc->sc_dmat, rxq->map, 0, rxq->map->dm_mapsize,
-	    BUS_DMASYNC_PREREAD);
-
-	/* Enable Rx. */
-	AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
-	AR_WRITE(sc, AR_CR, AR_CR_RXE);
+	/* Setup Rx DMA descriptors. */
+	sc->ops.rx_enable(sc);
 
 	/* Set Rx filter. */
 	rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST;
@@ -777,144 +501,12 @@ athn_intr(void *xsc)
 {
 	struct athn_softc *sc = xsc;
 	struct ifnet *ifp = &sc->sc_ic.ic_if;
-	uint32_t intr, intr2, intr5, sync;
 
 	if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) !=
 	    (IFF_UP | IFF_RUNNING))
 		return (0);
 
-	/* Get pending interrupts. */
-	intr = AR_READ(sc, AR_INTR_ASYNC_CAUSE);
-	if (!(intr & AR_INTR_MAC_IRQ) || intr == AR_INTR_SPURIOUS) {
-		intr = AR_READ(sc, AR_INTR_SYNC_CAUSE);
-		if (intr == AR_INTR_SPURIOUS || (intr & sc->isync) == 0)
-			return (0);	/* Not for us. */
-	}
-
-	if ((AR_READ(sc, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
-	    (AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
-		intr = AR_READ(sc, AR_ISR);
-	else
-		intr = 0;
-	sync = AR_READ(sc, AR_INTR_SYNC_CAUSE) & sc->isync;
-	if (intr == 0 && sync == 0)
-		return (0);	/* Not for us. */
-
-	if (intr != 0) {
-		if (intr & AR_ISR_BCNMISC) {
-			intr2 = AR_READ(sc, AR_ISR_S2);
-			if (intr2 & AR_ISR_S2_TIM)
-				/* TBD */;
-			if (intr2 & AR_ISR_S2_TSFOOR)
-				/* TBD */;
-		}
-		intr = AR_READ(sc, AR_ISR_RAC);
-		if (intr == AR_INTR_SPURIOUS)
-			return (1);
-
-		if (intr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
-			athn_rx_intr(sc);
-		if (intr & (AR_ISR_RXOK | AR_ISR_RXERR | AR_ISR_RXORN))
-			athn_rx_intr(sc);
-
-		if (intr & (AR_ISR_TXOK | AR_ISR_TXDESC |
-		    AR_ISR_TXERR | AR_ISR_TXEOL))
-			athn_tx_intr(sc);
-
-		if (intr & AR_ISR_GENTMR) {
-			intr5 = AR_READ(sc, AR_ISR_S5_S);
-			if (intr5 & AR_ISR_GENTMR) {
-				DPRINTF(("GENTMR trigger=%d thresh=%d\n",
-				    MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
-				    MS(intr5, AR_ISR_S5_GENTIMER_THRESH)));
-			}
-		}
-
-		intr5 = AR_READ(sc, AR_ISR_S5_S);
-		if (intr5 & AR_ISR_S5_TIM_TIMER)
-			/* TBD */;
-	}
-	if (sync != 0) {
-		if (sync & (AR_INTR_SYNC_HOST1_FATAL |
-		    AR_INTR_SYNC_HOST1_PERR))
-			/* TBD */;
-
-		if (sync & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
-			AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
-			AR_WRITE(sc, AR_RC, 0);
-		}
-
-		if ((sc->flags & ATHN_FLAG_RFSILENT) &&
-		    (sync & AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin))) {
-			printf("%s: radio switch turned off\n",
-			    sc->sc_dev.dv_xname);
-			/* Turn the interface down. */
-			ifp->if_flags &= ~IFF_UP;
-			athn_stop(ifp, 1);
-			return (1);
-		}
-
-		AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
-		(void)AR_READ(sc, AR_INTR_SYNC_CAUSE);
-	}
-	return (1);
-}
-
-/*
- * Access to General Purpose Input/Output ports.
- */
-int
-athn_gpio_read(struct athn_softc *sc, int pin)
-{
-	KASSERT(pin < sc->ngpiopins);
-	return ((AR_READ(sc, AR_GPIO_IN_OUT) >> (sc->ngpiopins + pin)) & 1);
-}
-
-void
-athn_gpio_write(struct athn_softc *sc, int pin, int set)
-{
-	uint32_t reg;
-
-	KASSERT(pin < sc->ngpiopins);
-	reg = AR_READ(sc, AR_GPIO_IN_OUT);
-	if (set)
-		reg |= 1 << pin;
-	else
-		reg &= ~(1 << pin);
-	AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
-}
-
-void
-athn_gpio_config_input(struct athn_softc *sc, int pin)
-{
-	uint32_t reg;
-
-	reg = AR_READ(sc, AR_GPIO_OE_OUT);
-	reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
-	reg |= AR_GPIO_OE_OUT_DRV_NO << (pin * 2);
-	AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
-}
-
-void
-athn_gpio_config_output(struct athn_softc *sc, int pin, int type)
-{
-	uint32_t reg;
-	int mux, off;
-
-	mux = pin / 6;
-	off = pin % 6;
-
-	reg = AR_READ(sc, AR_GPIO_OUTPUT_MUX(mux));
-	if (!AR_SREV_9280_20_OR_LATER(sc) && mux == 0)
-		reg = (reg & ~0x1f0) | (reg & 0x1f0) << 1;
-	reg &= ~(0x1f << (off * 5));
-	reg |= (type & 0x1f) << (off * 5);
-	AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
-
-	reg = AR_READ(sc, AR_GPIO_OE_OUT);
-	reg &= ~(AR_GPIO_OE_OUT_DRV_M << (pin * 2));
-	reg |= AR_GPIO_OE_OUT_DRV_ALL << (pin * 2);
-	AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
+	return (sc->ops.intr(sc));
 }
 
 void
@@ -952,13 +544,20 @@ athn_get_mac_name(struct athn_softc *sc)
 		return ("AR9285");
 	case AR_SREV_VERSION_9287:
 		return ("AR9287");
+	case AR_SREV_VERSION_9380:
+		return ("AR9380");
 	}
 	return ("unknown");
 }
 
+/*
+ * Return RF chip name (not for single-chip solutions.)
+ */
 const char *
 athn_get_rf_name(struct athn_softc *sc)
 {
+	KASSERT(!AR_SINGLE_CHIP(sc));
+
 	switch (sc->rf_rev) {
 	case AR_RAD5133_SREV_MAJOR:	/* Dual-band 3T3R. */
 		return ("AR5133");
@@ -981,13 +580,16 @@ athn_reset_power_on(struct athn_softc *sc)
 	AR_WRITE(sc, AR_RTC_FORCE_WAKE,
 	    AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
 
-	/* Make sure no DMA is active by doing an AHB reset. */
-	AR_WRITE(sc, AR_RC, AR_RC_AHB);
-
+	/* XXX on first call, we do not know the chip id yet. */
+	if (!AR_SREV_9380_10_OR_LATER(sc)) {
+		/* Make sure no DMA is active by doing an AHB reset. */
+		AR_WRITE(sc, AR_RC, AR_RC_AHB);
+	}
 	/* RTC reset and clear. */
 	AR_WRITE(sc, AR_RTC_RESET, 0);
 	DELAY(2);
-	AR_WRITE(sc, AR_RC, 0);
+	if (!AR_SREV_9380_10_OR_LATER(sc))
+		AR_WRITE(sc, AR_RC, 0);
 	AR_WRITE(sc, AR_RTC_RESET, 1);
 
 	/* Poll until RTC is ON. */
@@ -1020,8 +622,9 @@ athn_reset(struct athn_softc *sc, int cold)
 	if (AR_READ(sc, AR_INTR_SYNC_CAUSE) &
 	    (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
 		AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
-		AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
-	} else
+		AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
+		    (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0));
+	} else if (!AR_SREV_9380_10_OR_LATER(sc))
 		AR_WRITE(sc, AR_RC, AR_RC_AHB);
 
 	AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
@@ -1052,7 +655,8 @@ athn_set_power_awake(struct athn_softc *sc)
 	    AR_RTC_STATUS_SHUTDOWN) {
 		if ((error = athn_reset_power_on(sc)) != 0)
 			return (error);
-		athn_init_pll(sc, NULL);
+		if (!AR_SREV_9380_10_OR_LATER(sc))
+			athn_init_pll(sc, NULL);
 	}
 	AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
 	DELAY(50);	/* Give chip the chance to awake. */
@@ -1078,8 +682,10 @@ void
 athn_set_power_sleep(struct athn_softc *sc)
 {
 	AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
+	/* Allow the MAC to go to sleep. */
 	AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
-	AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
+	if (!AR_SREV_9380_10_OR_LATER(sc))
+		AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
 	/*
 	 * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode
 	 * results in high power consumption on AR5416 chipsets.
@@ -1093,7 +699,10 @@ athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c)
 {
 	uint32_t pll;
 
-	if (AR_SREV_9280_10_OR_LATER(sc)) {
+	if (AR_SREV_9380_10_OR_LATER(sc)) {
+		pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
+		pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
+	} else if (AR_SREV_9280_10_OR_LATER(sc)) {
 		pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
 		if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) {
 			if (AR_SREV_9280_20(sc)) {
@@ -1160,53 +769,12 @@ athn_config_nonpcie(struct athn_softc *sc)
 	athn_write_serdes(sc, ar_nonpcie_serdes);
 }
 
-uint8_t
-athn_reverse_bits(uint8_t v, int nbits)
-{
-	KASSERT(nbits <= 8);
-	v = ((v >> 1) & 0x55) | ((v & 0x55) << 1);
-	v = ((v >> 2) & 0x33) | ((v & 0x33) << 2);
-	v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4);
-	return (v >> (8 - nbits));
-}
-
-uint8_t
-athn_get_rf_rev(struct athn_softc *sc)
-{
-	uint8_t rev, reg;
-	int i;
-
-	AR_WRITE(sc, AR_PHY(0x36), 0x00007058);
-	for (i = 0; i < 8; i++)
-		AR_WRITE(sc, AR_PHY(0x20), 0x00010000);
-	reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff;
-	reg = (reg & 0xf0) >> 4 | (reg & 0x0f) << 4;
-
-	rev = athn_reverse_bits(reg, 8);
-	if ((rev & AR_RADIO_SREV_MAJOR) == 0)
-		rev = AR_RAD5133_SREV_MAJOR;
-	return (rev);
-}
-
-static __inline uint32_t
-athn_synth_delay(struct athn_softc *sc)
-{
-	uint32_t delay;
-
-	delay = MS(AR_READ(sc, AR_PHY_RX_DELAY), AR_PHY_RX_DELAY_DELAY);
-	if (sc->sc_ic.ic_curmode == IEEE80211_MODE_11B)
-		delay = (delay * 4) / 22;
-	else
-		delay = delay / 10;	/* in 100ns steps */
-	return (delay);
-}
-
 int
 athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c,
     struct ieee80211_channel *extc)
 {
 	struct athn_ops *ops = &sc->ops;
-	int error, qid, ntries;
+	int error, qid;
 
 	/* Check that Tx is stopped, otherwise RF Bus grant will not work. */
 	for (qid = 0; qid < ATHN_QID_COUNT; qid++)
@@ -1214,18 +782,10 @@ athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c,
 			return (EBUSY);
 
 	/* Request RF Bus grant. */
-	AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
-	for (ntries = 0; ntries < 10000; ntries++) {
-		if (AR_READ(sc, AR_PHY_RFBUS_GRANT) & AR_PHY_RFBUS_GRANT_EN)
-			break;
-		DELAY(10);
-	}
-	if (ntries == 10000) {
-		DPRINTF(("could not kill baseband Rx"));
-		return (ETIMEDOUT);
-	}
+	if ((error = ops->rf_bus_request(sc)) != 0)
+		return (error);
 
-	athn_set_phy(sc, c, extc);
+	ops->set_phy(sc, c, extc);
 
 	/* Change the synthesizer. */
 	if ((error = ops->set_synth(sc, c, extc)) != 0)
@@ -1237,15 +797,12 @@ athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c,
 	/* Set transmit power values for new channel. */
 	ops->set_txpower(sc, c, extc);
 
-	/* Wait for the synthesizer to settle. */
-	DELAY(AR_BASE_PHY_ACTIVE_DELAY + athn_synth_delay(sc));
-
 	/* Release the RF Bus grant. */
-	AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
+	ops->rf_bus_release(sc);
 
 	/* Write delta slope coeffs for modes where OFDM may be used. */
 	if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B)
-		athn_set_delta_slope(sc, c, extc);
+		ops->set_delta_slope(sc, c, extc);
 
 	ops->spur_mitigate(sc, c, extc);
 	/* XXX Load noisefloor values and start calibration. */
@@ -1280,7 +837,7 @@ athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c,
 		goto reset;
 
 	/* AR9280 always needs a full reset. */
-/*	if (AR_SREV_9280(sc)) */
+/*	if (AR_SREV_9280(sc))*/
 		goto reset;
 
 	/* If band or bandwidth changes, we need to do a full reset. */
@@ -1329,149 +886,6 @@ athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa)
 }
 
 void
-athn_set_delta_slope(struct athn_softc *sc, struct ieee80211_channel *c,
-    struct ieee80211_channel *extc)
-{
-	uint32_t coeff, exp, man, reg;
-
-	/* Set Delta Slope (exponent and mantissa). */
-	coeff = (100 << 24) / c->ic_freq;
-	athn_get_delta_slope(coeff, &exp, &man);
-	DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man));
-
-	reg = AR_READ(sc, AR_PHY_TIMING3);
-	reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
-	reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
-	AR_WRITE(sc, AR_PHY_TIMING3, reg);
-
-	/* For Short GI, coeff is 9/10 that of normal coeff. */
-	coeff = (9 * coeff) / 10;
-	athn_get_delta_slope(coeff, &exp, &man);
-	DPRINTFN(5, ("delta slope coeff exp=%u man=%u\n", exp, man));
-
-	reg = AR_READ(sc, AR_PHY_HALFGI);
-	reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
-	reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
-	AR_WRITE(sc, AR_PHY_HALFGI, reg);
-}
-
-void
-athn_set_phy(struct athn_softc *sc, struct ieee80211_channel *c,
-    struct ieee80211_channel *extc)
-{
-	uint32_t phy;
-
-	if (AR_SREV_9285_10_OR_LATER(sc))
-		phy = AR_READ(sc, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO;
-	else
-		phy = 0;
-	phy |= AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 |
-	    AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
-	if (extc != NULL) {
-		phy |= AR_PHY_FC_DYN2040_EN;
-		if (extc > c)	/* XXX */
-			phy |= AR_PHY_FC_DYN2040_PRI_CH;
-	}
-	AR_WRITE(sc, AR_PHY_TURBO, phy);
-
-	AR_WRITE(sc, AR_2040_MODE,
-	    (extc != NULL) ? AR_2040_JOINED_RX_CLEAR : 0);
-
-	AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
-	AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
-}
-
-int
-athn_read_rom_word(struct athn_softc *sc, uint32_t addr, uint16_t *val)
-{
-	uint32_t reg;
-	int ntries;
-
-	/* Read 16-bit value from ROM. */
-	reg = AR_READ(sc, AR_EEPROM_OFFSET(addr));
-	for (ntries = 0; ntries < 1000; ntries++) {
-		reg = AR_READ(sc, AR_EEPROM_STATUS_DATA);
-		if (!(reg & (AR_EEPROM_STATUS_DATA_BUSY |
-		    AR_EEPROM_STATUS_DATA_PROT_ACCESS))) {
-			*val = MS(reg, AR_EEPROM_STATUS_DATA_VAL);
-			return (0);
-		}
-		DELAY(10);
-	}
-	*val = 0xffff;
-	return (ETIMEDOUT);
-}
-
-int
-athn_read_rom(struct athn_softc *sc)
-{
-	uint32_t addr, end;
-	uint16_t magic, sum, *eep;
-	int need_swap = 0;
-	int error;
-
-	/* Determine ROM endianness. */
-	error = athn_read_rom_word(sc, AR_EEPROM_MAGIC_OFFSET, &magic);
-	if (error != 0)
-		return (error);
-	if (magic != AR_EEPROM_MAGIC) {
-		if (magic != swap16(AR_EEPROM_MAGIC)) {
-			DPRINTF(("invalid ROM magic 0x%x != 0x%x\n",
-			    magic, AR_EEPROM_MAGIC));
-			return (EIO);
-		}
-		DPRINTF(("non-native ROM endianness\n"));
-		need_swap = 1;
-	}
-
-	/* Allocate space to store ROM in host memory. */
-	sc->eep = malloc(sc->eep_size, M_DEVBUF, M_NOWAIT);
-	if (sc->eep == NULL)
-		return (ENOMEM);
-
-	/* Read entire ROM and compute checksum. */
-	sum = 0;
-	eep = sc->eep;
-	end = sc->eep_base + sc->eep_size / sizeof (uint16_t);
-	for (addr = sc->eep_base; addr < end; addr++, eep++) {
-		if ((error = athn_read_rom_word(sc, addr, eep)) != 0) {
-			DPRINTF(("could not read ROM at 0x%x\n", addr));
-			return (error);
-		}
-		if (need_swap)
-			*eep = swap16(*eep);
-		sum ^= *eep;
-	}
-	if (sum != 0xffff) {
-		printf("%s: bad ROM checksum 0x%04x\n",
-		    sc->sc_dev.dv_xname, sum);
-		return (EIO);
-	}
-	if (need_swap)
-		athn_swap_rom(sc);
-
-	return (0);
-}
-
-void
-athn_swap_rom(struct athn_softc *sc)
-{
-	struct ar_base_eep_header *base = sc->eep;
-
-	/* Swap common fields first. */
-	base->length = swap16(base->length);
-	base->version = swap16(base->version);
-	base->regDmn[0] = swap16(base->regDmn[0]);
-	base->regDmn[1] = swap16(base->regDmn[1]);
-	base->rfSilent = swap16(base->rfSilent);
-	base->blueToothOptions = swap16(base->blueToothOptions);
-	base->deviceCap = swap16(base->deviceCap);
-
-	/* Swap device-dependent fields. */
-	sc->ops.swap_rom(sc);
-}
-
-void
 athn_reset_key(struct athn_softc *sc, int entry)
 {
 	/*
@@ -1604,23 +1018,26 @@ athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
 void
 athn_led_init(struct athn_softc *sc)
 {
-	athn_gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+	struct athn_ops *ops = &sc->ops;
+
+	ops->gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 	/* LED off, active low. */
-	athn_gpio_write(sc, sc->led_pin, 1);
+	ops->gpio_write(sc, sc->led_pin, 1);
 }
 
 #ifdef ATHN_BT_COEXISTENCE
 void
 athn_btcoex_init(struct athn_softc *sc)
 {
+	struct athn_ops *ops = &sc->ops;
 	uint32_t reg;
 
 	if (sc->flags & ATHN_FLAG_BTCOEX2WIRE) {
 		/* Connect bt_active to baseband. */
-		AR_CLRBITS(sc, AR_GPIO_INPUT_EN_VAL,
+		AR_CLRBITS(sc, sc->gpio_input_en_off,
 		    AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
 		    AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF);
-		AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL,
+		AR_SETBITS(sc, sc->gpio_input_en_off,
 		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
 
 		reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
@@ -1628,9 +1045,9 @@ athn_btcoex_init(struct athn_softc *sc)
 		    AR_GPIO_BTACTIVE_PIN);
 		AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
 
-		athn_gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
+		ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
 	} else {	/* 3-wire. */
-		AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL,
+		AR_SETBITS(sc, sc->gpio_input_en_off,
 		    AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
 		    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
 
@@ -1641,14 +1058,15 @@ athn_btcoex_init(struct athn_softc *sc)
 		    AR_GPIO_BTPRIORITY_PIN);
 		AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
 
-		athn_gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
-		athn_gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN);
+		ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
+		ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN);
 	}
 }
 
 void
 athn_btcoex_enable(struct athn_softc *sc)
 {
+	struct athn_ops *ops = &sc->ops;
 	uint32_t reg;
 
 	if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) {
@@ -1669,11 +1087,11 @@ athn_btcoex_enable(struct athn_softc *sc)
 		AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE);
 		AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX);
 
-		athn_gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
+		ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
 		    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
 
 	} else {	/* 2-wire. */
-		athn_gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
+		ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
 		    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
 	}
 	reg = AR_READ(sc, AR_GPIO_PDPU);
@@ -1691,9 +1109,11 @@ athn_btcoex_enable(struct athn_softc *sc)
 void
 athn_btcoex_disable(struct athn_softc *sc)
 {
-	athn_gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0);
+	struct athn_ops *ops = &sc->ops;
+
+	ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0);
 
-	athn_gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
+	ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
 	    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 
 	if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) {
@@ -1708,24 +1128,6 @@ athn_btcoex_disable(struct athn_softc *sc)
 #endif
 
 void
-athn_rfsilent_init(struct athn_softc *sc)
-{
-	uint32_t reg;
-
-	/* Configure hardware radio switch. */
-	AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-	reg = AR_READ(sc, AR_GPIO_INPUT_MUX2);
-	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
-	AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
-	athn_gpio_config_input(sc, sc->rfsilent_pin);
-	AR_SETBITS(sc, AR_PHY_TEST, AR_PHY_TEST_RFSILENT_BB);
-	if (!(sc->flags & ATHN_FLAG_RFSILENT_REVERSED)) {
-		AR_SETBITS(sc, AR_GPIO_INTR_POL,
-		    AR_GPIO_INTR_POL_PIN(sc->rfsilent_pin));
-	}
-}
-
-void
 athn_iter_func(void *arg, struct ieee80211_node *ni)
 {
 	struct athn_softc *sc = arg;
@@ -1744,20 +1146,10 @@ athn_calib_to(void *arg)
 	s = splnet();
 #ifdef notyet
 	/* XXX ANI. */
+	athn_ani_monitor(sc);
 	/* XXX OLPC temperature compensation. */
 
-	if (AR_READ(sc, AR_PHY_TIMING_CTRL4_0) & AR_PHY_TIMING_CTRL4_DO_CAL) {
-		/* Calibration in progress, come back later. */
-		timeout_add_msec(&sc->calib_to, 500);
-		splx(s);
-		return;
-	}
-	if (sc->calib_mask & ATHN_CAL_ADC_GAIN)
-		athn_calib_iq(sc);
-	else if (sc->calib_mask & ATHN_CAL_ADC_DC)
-		athn_calib_adc_gain(sc);
-	else if (sc->calib_mask & ATHN_CAL_IQ)
-		athn_calib_adc_dc_off(sc);
+	sc->ops.next_calib(sc);
 #endif
 	if (ic->ic_fixed_rate == -1) {
 		if (ic->ic_opmode == IEEE80211_M_STA)
@@ -1769,292 +1161,16 @@ athn_calib_to(void *arg)
 	splx(s);
 }
 
-void
-athn_do_calib(struct athn_softc *sc)
-{
-	int log = AR_MAX_LOG_CAL;	/* XXX */
-	uint32_t mode = 0, reg;
-
-	reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
-	reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);
-	AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
-
-	if (sc->calib_mask & ATHN_CAL_ADC_GAIN)
-		mode = AR_PHY_CALMODE_ADC_GAIN;
-	else if (sc->calib_mask & ATHN_CAL_ADC_DC)
-		mode = AR_PHY_CALMODE_ADC_DC_PER;
-	else if (sc->calib_mask & ATHN_CAL_IQ)
-		mode = AR_PHY_CALMODE_IQ;
-	AR_WRITE(sc, AR_PHY_CALMODE, mode);
-
-	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0, AR_PHY_TIMING_CTRL4_DO_CAL);
-}
-
-void
-athn_calib_iq(struct athn_softc *sc)
-{
-	struct athn_iq_cal *cal;
-	uint32_t reg, i_coff_denom, q_coff_denom;
-	int32_t i_coff, q_coff;
-	int i, iq_corr_neg;
-
-	for (i = 0; i < AR_MAX_CHAINS; i++) {
-		cal = &sc->calib.iq[i];
-
-		/* Accumulate IQ calibration measures (clear on read). */
-		cal->pwr_meas_i += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
-		cal->pwr_meas_q += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
-		cal->iq_corr_meas +=
-		    (int32_t)AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
-	}
-	if (++sc->calib.nsamples < AR_CAL_SAMPLES) {
-		/* Not enough samples accumulated, continue. */
-		athn_do_calib(sc);
-		return;
-	}
-
-	for (i = 0; i < sc->nrxchains; i++) {
-		cal = &sc->calib.iq[i];
-
-		if (cal->pwr_meas_q == 0)
-			continue;
-
-		if ((iq_corr_neg = cal->iq_corr_meas < 0))
-			cal->iq_corr_meas = -cal->iq_corr_meas;
-
-		i_coff_denom =
-		    (cal->pwr_meas_i / 2 + cal->pwr_meas_q / 2) / 128;
-		q_coff_denom = cal->pwr_meas_q / 64;
-
-		if (i_coff_denom == 0 || q_coff_denom == 0)
-			continue;	/* Prevents division by zero. */
-
-		i_coff = cal->iq_corr_meas / i_coff_denom;
-		q_coff = (cal->pwr_meas_i / q_coff_denom) - 64;
-
-		/* Negate i_coff if iq_corr_meas is positive. */
-		if (!iq_corr_neg)
-			i_coff = 0x40 - (i_coff & 0x3f);
-		if (q_coff > 15)
-			q_coff = 15;
-		else if (q_coff <= -16)
-			q_coff = 16;
-
-		DPRINTFN(2, ("IQ calibration for chain %d\n", i));
-		reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i));
-		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
-		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);
-		AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);
-	}
-
-	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
-	    AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
-}
-
-void
-athn_calib_adc_gain(struct athn_softc *sc)
-{
-	struct athn_adc_cal *cal;
-	uint32_t reg, gain_mismatch_i, gain_mismatch_q;
-	int i;
-
-	for (i = 0; i < AR_MAX_CHAINS; i++) {
-		cal = &sc->calib.adc_gain[i];
-
-		/* Accumulate ADC gain measures (clear on read). */
-		cal->pwr_meas_odd_i  += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
-		cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
-		cal->pwr_meas_odd_q  += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
-		cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
-	}
-	if (++sc->calib.nsamples < AR_CAL_SAMPLES) {
-		/* Not enough samples accumulated, continue. */
-		athn_do_calib(sc);
-		return;
-	}
-
-	for (i = 0; i < sc->nrxchains; i++) {
-		cal = &sc->calib.adc_gain[i];
-
-		if (cal->pwr_meas_odd_i == 0 || cal->pwr_meas_even_q == 0)
-			continue;	/* Prevents division by zero. */
-
-		gain_mismatch_i =
-		    (cal->pwr_meas_even_i * 32) / cal->pwr_meas_odd_i;
-		gain_mismatch_q =
-		    (cal->pwr_meas_odd_q * 32) / cal->pwr_meas_even_q;
-
-		DPRINTFN(2, ("ADC gain calibration for chain %d\n", i));
-		reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
-		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);
-		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);
-		AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
-	}
-
-	AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
-	    AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
-}
-
-void
-athn_calib_adc_dc_off(struct athn_softc *sc)
-{
-	struct athn_adc_cal *cal;
-	int32_t dc_offset_mismatch_i, dc_offset_mismatch_q;
-	uint32_t reg;
-	int count, i;
-
-	for (i = 0; i < AR_MAX_CHAINS; i++) {
-		cal = &sc->calib.adc_dc_offset[i];
-
-		/* Accumulate ADC DC offset measures (clear on read). */
-		cal->pwr_meas_odd_i  += AR_READ(sc, AR_PHY_CAL_MEAS_0(i));
-		cal->pwr_meas_even_i += AR_READ(sc, AR_PHY_CAL_MEAS_1(i));
-		cal->pwr_meas_odd_q  += AR_READ(sc, AR_PHY_CAL_MEAS_2(i));
-		cal->pwr_meas_even_q += AR_READ(sc, AR_PHY_CAL_MEAS_3(i));
-	}
-	if (++sc->calib.nsamples < AR_CAL_SAMPLES) {
-		/* Not enough samples accumulated, continue. */
-		athn_do_calib(sc);
-		return;
-	}
-
-	count = (1 << (AR_MAX_LOG_CAL + 5)) * sc->calib.nsamples;
-
-	for (i = 0; i < sc->nrxchains; i++) {
-		cal = &sc->calib.adc_dc_offset[i];
-
-		dc_offset_mismatch_i =
-		    (cal->pwr_meas_even_i - cal->pwr_meas_odd_i * 2) / count;
-		dc_offset_mismatch_q =
-		    (cal->pwr_meas_odd_q - cal->pwr_meas_even_q * 2) / count;
-
-		DPRINTFN(2, ("ADC DC offset calibration for chain %d\n", i));
-		reg = AR_READ(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
-		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,
-		    dc_offset_mismatch_q);
-		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,
-		    dc_offset_mismatch_i);
-		AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
-	}
-
-	AR_SETBITS(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
-	    AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
-}
-
-void
-athn_read_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
-{
-/* Sign-extend 9-bit value to 16-bit. */
-#define SIGN_EXT(v)	((((int16_t)(v)) << 7) >> 7)
-	uint32_t reg;
-	int i;
-
-	for (i = 0; i < sc->nrxchains; i++) {
-		reg = AR_READ(sc, AR_PHY_CCA(i));
-		if (AR_SREV_9280_10_OR_LATER(sc))
-			nf[i] = MS(reg, AR9280_PHY_MINCCA_PWR);
-		else
-			nf[i] = MS(reg, AR_PHY_MINCCA_PWR);
-		nf[i] = SIGN_EXT(nf[i]);
-
-		reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
-		if (AR_SREV_9280_10_OR_LATER(sc))
-			nf_ext[i] = MS(reg, AR9280_PHY_EXT_MINCCA_PWR);
-		else
-			nf_ext[i] = MS(reg, AR_PHY_EXT_MINCCA_PWR);
-		nf_ext[i] = SIGN_EXT(nf_ext[i]);
-	}
-#undef SIGN_EXT
-}
-
-void
-athn_write_noisefloor(struct athn_softc *sc, int16_t *nf, int16_t *nf_ext)
-{
-	uint32_t reg;
-	int i;
-
-	for (i = 0; i < sc->nrxchains; i++) {
-		reg = AR_READ(sc, AR_PHY_CCA(i));
-		reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
-		AR_WRITE(sc, AR_PHY_CCA(i), reg);
-
-		reg = AR_READ(sc, AR_PHY_EXT_CCA(i));
-		reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
-		AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
-	}
-}
-
-void
-athn_get_noisefloor(struct athn_softc *sc, struct ieee80211_channel *c)
-{
-	int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
-	int i;
-
-	if (AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
-		/* Noisefloor calibration not finished. */
-		return;
-	}
-	/* Noisefloor calibration is finished. */
-	athn_read_noisefloor(sc, nf, nf_ext);
-
-	/* Update noisefloor history. */
-	for (i = 0; i < sc->nrxchains; i++) {
-		sc->nf_hist[sc->nf_hist_cur].nf[i] = nf[i];
-		sc->nf_hist[sc->nf_hist_cur].nf_ext[i] = nf_ext[i];
-	}
-	if (++sc->nf_hist_cur >= ATHN_NF_CAL_HIST_MAX)
-		sc->nf_hist_cur = 0;
-}
-
-void
-athn_bb_load_noisefloor(struct athn_softc *sc)
-{
-	int16_t nf[AR_MAX_CHAINS], nf_ext[AR_MAX_CHAINS];
-	int i, ntries;
-
-	/* Write filtered noisefloor values. */
-	for (i = 0; i < sc->nrxchains; i++) {
-		nf[i] = sc->nf_priv[i] * 2;
-		nf_ext[i] = sc->nf_ext_priv[i] * 2;
-	}
-	athn_write_noisefloor(sc, nf, nf_ext);
-
-	/* Load filtered noisefloor values into baseband. */
-	AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
-	AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
-	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
-	/* Wait for load to complete. */
-	for (ntries = 0; ntries < 5; ntries++) {
-		if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
-			break;
-		DELAY(50);
-	}
-#ifdef ATHN_DEBUG
-	if (ntries == 5 && athn_debug > 0)
-		printf("failed to load noisefloor values\n");
-#endif
-
-	/* Restore noisefloor values to initial (max) values. */
-	for (i = 0; i < AR_MAX_CHAINS; i++)
-		nf[i] = nf_ext[i] = -50 * 2;
-	athn_write_noisefloor(sc, nf, nf_ext);
-}
-
-void
-athn_noisefloor_calib(struct athn_softc *sc)
-{
-	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
-	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
-	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
-}
-
 int
 athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
     struct ieee80211_channel *extc)
 {
+	struct athn_ops *ops = &sc->ops;
 	int error;
 
-	if (AR_SREV_9285_12_OR_LATER(sc))
+	if (AR_SREV_9380_10_OR_LATER(sc))
+		error = ar9003_init_calib(sc);
+	else if (AR_SREV_9285_12_OR_LATER(sc))
 		error = ar9285_1_2_init_calib(sc, c, extc);
 	else
 		error = ar5416_init_calib(sc, c, extc);
@@ -2066,23 +1182,26 @@ athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
 		ar9285_pa_calib(sc);
 
 	/* Do noisefloor calibration. */
-	AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
+	ops->noisefloor_calib(sc);
 
-	if (AR_SREV_9160_10_OR_LATER(sc)) {
-		/* Enable IQ calibration. */
-		sc->calib_mask = ATHN_CAL_IQ;
+	if (!AR_SREV_9160_10_OR_LATER(sc))
+		return (0);
 
-		/* Enable ADC gain and ADC DC offset calibrations. */
-		if (IEEE80211_IS_CHAN_5GHZ(c) || extc != NULL)
-			sc->calib_mask |= ATHN_CAL_ADC_GAIN | ATHN_CAL_ADC_DC;
+	/* Enable IQ calibration. */
+	sc->calib_mask = ATHN_CAL_IQ;
 
-		athn_do_calib(sc);
+	if (!AR_SREV_9380_10_OR_LATER(sc) &&
+	    (IEEE80211_IS_CHAN_5GHZ(c) || extc != NULL)) {
+		/* Enable ADC gain and ADC DC offset calibrations. */
+		sc->calib_mask |= ATHN_CAL_ADC_GAIN | ATHN_CAL_ADC_DC;
 	}
+
+	ops->do_calib(sc);
 	return (0);
 }
 
 /*
- * Anti-noise immunity.
+ * Adaptive noise immunity.
  */
 int32_t
 athn_ani_get_rssi(struct athn_softc *sc)
@@ -2091,148 +1210,32 @@ athn_ani_get_rssi(struct athn_softc *sc)
 }
 
 void
-athn_ani_set_noise_immunity_level(struct athn_softc *sc, int level)
-{
-	int high = level == 4;
-	uint32_t reg;
-
-	reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
-	reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
-	AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
-
-	reg = AR_READ(sc, AR_PHY_AGC_CTL1);
-	reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);
-	reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);
-	AR_WRITE(sc, AR_PHY_AGC_CTL1, reg);
-
-	reg = AR_READ(sc, AR_PHY_FIND_SIG);
-	reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
-	AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
-
-	sc->ani.noise_immunity_level = level;
-}
-
-void
-athn_ani_ena_ofdm_weak_signal(struct athn_softc *sc)
-{
-	uint32_t reg;
-
-	reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
-	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
-	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
-	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
-	AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
-
-	reg = AR_READ(sc, AR_PHY_SFCORR);
-	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
-	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
-	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
-	AR_WRITE(sc, AR_PHY_SFCORR, reg);
-
-	reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
-	AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
-
-	AR_SETBITS(sc, AR_PHY_SFCORR_LOW,
-	    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
-
-	sc->ani.ofdm_weak_signal = 1;
-}
-
-void
-athn_ani_dis_ofdm_weak_signal(struct athn_softc *sc)
-{
-	uint32_t reg;
-
-	reg = AR_READ(sc, AR_PHY_SFCORR_LOW);
-	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
-	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
-	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
-	AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
-
-	reg = AR_READ(sc, AR_PHY_SFCORR);
-	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
-	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
-	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
-	AR_WRITE(sc, AR_PHY_SFCORR, reg);
-
-	reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
-	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
-	AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
-
-	AR_CLRBITS(sc, AR_PHY_SFCORR_LOW,
-	    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
-
-	sc->ani.ofdm_weak_signal = 0;
-}
-
-void
-athn_ani_set_cck_weak_signal(struct athn_softc *sc, int high)
-{
-	uint32_t reg;
-
-	reg = AR_READ(sc, AR_PHY_CCK_DETECT);
-	reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
-	AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
-
-	sc->ani.cck_weak_signal = high;
-}
-
-void
-athn_ani_set_firstep_level(struct athn_softc *sc, int level)
-{
-	uint32_t reg;
-
-	reg = AR_READ(sc, AR_PHY_FIND_SIG);
-	reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
-	AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
-
-	sc->ani.firstep_level = level;
-}
-
-void
-athn_ani_set_spur_immunity_level(struct athn_softc *sc, int level)
-{
-	uint32_t reg;
-
-	reg = AR_READ(sc, AR_PHY_TIMING5);
-	reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
-	AR_WRITE(sc, AR_PHY_TIMING5, reg);
-
-	sc->ani.spur_immunity_level = level;
-}
-
-void
 athn_ani_ofdm_err_trigger(struct athn_softc *sc)
 {
 	struct athn_ani *ani = &sc->ani;
+	struct athn_ops *ops = &sc->ops;
 	int32_t rssi;
 
 	/* First, raise noise immunity level, up to max. */
 	if (ani->noise_immunity_level < 4) {
-		athn_ani_set_noise_immunity_level(sc,
-		    ani->noise_immunity_level + 1);
+		ani->noise_immunity_level++;
+		ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
 		return;
 	}
 
 	/* Then, raise our spur immunity level, up to max. */
 	if (ani->spur_immunity_level < 7) {
-		athn_ani_set_spur_immunity_level(sc,
-		    ani->spur_immunity_level + 1);
+		ani->spur_immunity_level++;
+		ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
 		return;
 	}
 
 #ifndef IEEE80211_STA_ONLY
 	if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
-		if (ani->firstep_level < 2)
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level + 1);
+		if (ani->firstep_level < 2) {
+			ani->firstep_level++;
+			ops->set_firstep_level(sc, ani->firstep_level);
+		}
 		return;
 	}
 #endif
@@ -2243,22 +1246,26 @@ athn_ani_ofdm_err_trigger(struct athn_softc *sc)
 		 * or raise first step level as last resort.
 		 */
 		if (ani->ofdm_weak_signal) {
-			athn_ani_dis_ofdm_weak_signal(sc);
-			athn_ani_set_spur_immunity_level(sc, 0);
+			ani->ofdm_weak_signal = 0;
+			ops->disable_ofdm_weak_signal(sc);
+			ani->spur_immunity_level = 0;
+			ops->set_spur_immunity_level(sc, 0);
 		} else if (ani->firstep_level < 2) {
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level + 1);
+			ani->firstep_level++;
+			ops->set_firstep_level(sc, ani->firstep_level);
 		}
 	} else if (rssi > ATHN_ANI_RSSI_THR_LOW) {
 		/*
 		 * Beacon RSSI is in mid range, we need OFDM weak signal
 		 * detection but we can raise first step level.
 		 */
-		if (!ani->ofdm_weak_signal)
-			athn_ani_ena_ofdm_weak_signal(sc);
+		if (!ani->ofdm_weak_signal) {
+			ani->ofdm_weak_signal = 1;
+			ops->enable_ofdm_weak_signal(sc);
+		}
 		if (ani->firstep_level < 2) {
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level + 1);
+			ani->firstep_level++;
+			ops->set_firstep_level(sc, ani->firstep_level);
 		}
 	} else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) {
 		/*
@@ -2266,10 +1273,14 @@ athn_ani_ofdm_err_trigger(struct athn_softc *sc)
 		 * signal detection and zero first step level to maximize
 		 * CCK sensitivity.
 		 */
-		if (ani->ofdm_weak_signal)
-			athn_ani_dis_ofdm_weak_signal(sc);
-		if (ani->firstep_level > 0)
-			athn_ani_set_firstep_level(sc, 0);
+		if (ani->ofdm_weak_signal) {
+			ani->ofdm_weak_signal = 0;
+			ops->disable_ofdm_weak_signal(sc);
+		}
+		if (ani->firstep_level > 0) {
+			ani->firstep_level = 0;
+			ops->set_firstep_level(sc, 0);
+		}
 	}
 }
 
@@ -2277,20 +1288,22 @@ void
 athn_ani_cck_err_trigger(struct athn_softc *sc)
 {
 	struct athn_ani *ani = &sc->ani;
+	struct athn_ops *ops = &sc->ops;
 	int32_t rssi;
 
 	/* Raise noise immunity level, up to max. */
 	if (ani->noise_immunity_level < 4) {
-		athn_ani_set_noise_immunity_level(sc,
-		    ani->noise_immunity_level + 1);
+		ani->noise_immunity_level++;
+		ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
 		return;
 	}
 
 #ifndef IEEE80211_STA_ONLY
 	if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
-		if (ani->firstep_level < 2)
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level + 1);
+		if (ani->firstep_level < 2) {
+			ani->firstep_level++;
+			ops->set_firstep_level(sc, ani->firstep_level);
+		}
 		return;
 	}
 #endif
@@ -2300,16 +1313,19 @@ athn_ani_cck_err_trigger(struct athn_softc *sc)
 		 * Beacon RSSI is in mid or high range, raise first step
 		 * level.
 		 */
-		if (ani->firstep_level < 2)
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level + 1);
+		if (ani->firstep_level < 2) {
+			ani->firstep_level++;
+			ops->set_firstep_level(sc, ani->firstep_level);
+		}
 	} else if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11A) {
 		/*
 		 * Beacon RSSI is low, zero first step level to maximize
 		 * CCK sensitivity.
 		 */
-		if (ani->firstep_level > 0)
-			athn_ani_set_firstep_level(sc, 0);
+		if (ani->firstep_level > 0) {
+			ani->firstep_level = 0;
+			ops->set_firstep_level(sc, 0);
+		}
 	}
 }
 
@@ -2317,13 +1333,15 @@ void
 athn_ani_lower_immunity(struct athn_softc *sc)
 {
 	struct athn_ani *ani = &sc->ani;
+	struct athn_ops *ops = &sc->ops;
 	int32_t rssi;
 
 #ifndef IEEE80211_STA_ONLY
 	if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
-		if (ani->firstep_level > 0)
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level - 1);
+		if (ani->firstep_level > 0) {
+			ani->firstep_level--;
+			ops->set_firstep_level(sc, ani->firstep_level);
+		}
 		return;
 	}
 #endif
@@ -2339,19 +1357,20 @@ athn_ani_lower_immunity(struct athn_softc *sc)
 		 * detection or lower first step level.
 		 */
 		if (!ani->ofdm_weak_signal) {
-			athn_ani_ena_ofdm_weak_signal(sc);
+			ani->ofdm_weak_signal = 1;
+			ops->enable_ofdm_weak_signal(sc);
 			return;
 		}
 		if (ani->firstep_level > 0) {
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level - 1);
+			ani->firstep_level--;
+			ops->set_firstep_level(sc, ani->firstep_level);
 			return;
 		}
 	} else {
 		/* Beacon RSSI is low, lower first step level. */
 		if (ani->firstep_level > 0) {
-			athn_ani_set_firstep_level(sc,
-			    ani->firstep_level - 1);
+			ani->firstep_level--;
+			ops->set_firstep_level(sc, ani->firstep_level);
 			return;
 		}
 	}
@@ -2359,12 +1378,13 @@ athn_ani_lower_immunity(struct athn_softc *sc)
 	 * Lower spur immunity level down to zero, or if all else fails,
 	 * lower noise immunity level down to zero.
 	 */
-	if (ani->spur_immunity_level > 0)
-		athn_ani_set_spur_immunity_level(sc,
-		    ani->spur_immunity_level - 1);
-	else if (ani->noise_immunity_level > 0)
-		athn_ani_set_noise_immunity_level(sc,
-		    ani->noise_immunity_level - 1);
+	if (ani->spur_immunity_level > 0) {
+		ani->spur_immunity_level--;
+		ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
+	} else if (ani->noise_immunity_level > 0) {
+		ani->noise_immunity_level--;
+		ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
+	}
 }
 
 void
@@ -2461,22 +1481,13 @@ athn_chan2fbin(struct ieee80211_channel *c)
 		return ((c->ic_freq - 4800) / 5);
 }
 
-void
-athn_init_chains(struct athn_softc *sc)
+int
+athn_interpolate(int x, int x1, int y1, int x2, int y2)
 {
-	if (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5)
-		AR_SETBITS(sc, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
-
-	/* Setup chain masks. */
-	if (sc->mac_ver <= AR_SREV_VERSION_9160 &&
-	    (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5)) {
-		AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  0x7);
-		AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, 0x7);
-	} else {
-		AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  sc->rxchainmask);
-		AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
-	}
-	AR_WRITE(sc, AR_SELFGEN_MASK, sc->txchainmask);
+	if (x1 == x2)	/* Prevents division by zero. */
+		return (y1);
+	/* Linear interpolation. */
+	return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1));
 }
 
 void
@@ -2497,279 +1508,15 @@ athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers,
 		*hi = *lo;
 }
 
-uint8_t
-athn_get_vpd(uint8_t pwr, const uint8_t *pwrPdg, const uint8_t *vpdPdg,
-    int nicepts)
-{
-	uint8_t vpd;
-	int i, lo, hi;
-
-	for (i = 0; i < nicepts; i++)
-		if (pwrPdg[i] > pwr)
-			break;
-	hi = i;
-	lo = hi - 1;
-	if (lo == -1)
-		lo = hi;
-	else if (hi == nicepts)
-		hi = lo;
-
-	vpd = athn_interpolate(pwr, pwrPdg[lo], vpdPdg[lo],
-	    pwrPdg[hi], vpdPdg[hi]);
-	return (vpd);
-}
-
-void
-athn_get_pdadcs(struct athn_softc *sc, uint8_t fbin, struct athn_pier *lopier,
-    struct athn_pier *hipier, int nxpdgains, int nicepts, uint8_t overlap,
-    uint8_t *boundaries, uint8_t *pdadcs)
-{
-#define DB(x)	((x) / 2)	/* Convert half dB to dB. */
-	uint8_t minpwr[AR_PD_GAINS_IN_MASK], maxpwr[AR_PD_GAINS_IN_MASK];
-	uint8_t vpd[AR_MAX_PWR_RANGE_IN_HALF_DB], pwr;
-	uint8_t lovpd, hivpd, boundary;
-	int16_t ss, delta, vpdstep, val;
-	int i, j, npdadcs, nvpds, maxidx, tgtidx;
-
-	/* Compute min and max power in half dB for each pdGain. */
-	for (i = 0; i < nxpdgains; i++) {
-		minpwr[i] = MAX(lopier->pwr[i][0], hipier->pwr[i][0]);
-		maxpwr[i] = MIN(lopier->pwr[i][nicepts - 1],
-		    hipier->pwr[i][nicepts - 1]);
-	}
-
-	npdadcs = 0;
-	for (i = 0; i < nxpdgains; i++) {
-		if (i != nxpdgains - 1)
-			boundaries[i] = DB(maxpwr[i] + minpwr[i + 1]) / 2;
-		else
-			boundaries[i] = DB(maxpwr[i]);
-		if (boundaries[i] > AR_MAX_RATE_POWER)
-			boundaries[i] = AR_MAX_RATE_POWER;
-
-		if (i == 0 && !AR_SREV_5416_20_OR_LATER(sc)) {
-			/* Fix the gain delta (AR5416 1.0 only.) */
-			delta = boundaries[0] - 23;
-			boundaries[0] = 23;
-		} else
-			delta = 0;
-
-		/* Find starting index for this pdGain. */
-		if (i != 0) {
-			ss = boundaries[i - 1] - DB(minpwr[i]) -
-			    overlap + 1 + delta;
-		} else if (AR_SREV_9280_10_OR_LATER(sc)) {
-			ss = -DB(minpwr[i]);
-		} else
-			ss = 0;
-
-		/* Compute Vpd table for this pdGain. */
-		nvpds = DB(maxpwr[i] - minpwr[i]) + 1;
-		memset(vpd, 0, sizeof(vpd));
-		pwr = minpwr[i];
-		for (j = 0; j < nvpds; j++) {
-			/* Get lower and higher Vpd. */
-			lovpd = athn_get_vpd(pwr, lopier->pwr[i],
-			    lopier->vpd[i], nicepts);
-			hivpd = athn_get_vpd(pwr, hipier->pwr[i],
-			    hipier->vpd[i], nicepts);
-
-			/* Interpolate the final Vpd. */
-			vpd[j] = athn_interpolate(fbin,
-			    lopier->fbin, lovpd, hipier->fbin, hivpd);
-
-			pwr += 2;	/* In half dB. */
-		}
-
-		/* Extrapolate data for ss < 0. */
-		if (vpd[1] > vpd[0])
-			vpdstep = vpd[1] - vpd[0];
-		else
-			vpdstep = 1;
-		while (ss < 0 && npdadcs < AR_NUM_PDADC_VALUES - 1) {
-			val = vpd[0] + ss * vpdstep;
-			pdadcs[npdadcs++] = MAX(val, 0);
-			ss++;
-		}
-
-		tgtidx = boundaries[i] + overlap - DB(minpwr[i]);
-		maxidx = MIN(tgtidx, nvpds);
-		while (ss < maxidx && npdadcs < AR_NUM_PDADC_VALUES - 1)
-			pdadcs[npdadcs++] = vpd[ss++];
-
-		if (tgtidx <= maxidx)
-			continue;
-
-		/* Extrapolate data for maxidx <= ss <= tgtidx. */
-		if (vpd[nvpds - 1] > vpd[nvpds - 2])
-			vpdstep = vpd[nvpds - 1] - vpd[nvpds - 2];
-		else
-			vpdstep = 1;
-		while (ss <= tgtidx && npdadcs < AR_NUM_PDADC_VALUES - 1) {
-			val = vpd[nvpds - 1] + (ss - maxidx + 1) * vpdstep;
-			pdadcs[npdadcs++] = MIN(val, 255);
-			ss++;
-		}
-	}
-
-	/* Fill remaining PDADC and boundaries entries. */
-	if (AR_SREV_9285(sc))
-		boundary = AR9285_PD_GAIN_BOUNDARY_DEFAULT;
-	else	/* Fill with latest. */
-		boundary = boundaries[nxpdgains - 1];
-
-	for (; nxpdgains < AR_PD_GAINS_IN_MASK; nxpdgains++)
-		boundaries[nxpdgains] = boundary;
-
-	for (; npdadcs < AR_NUM_PDADC_VALUES; npdadcs++)
-		pdadcs[npdadcs] = pdadcs[npdadcs - 1];
-#undef DB
-}
-
-int
-athn_interpolate(int x, int x1, int y1, int x2, int y2)
-{
-	if (x1 == x2)	/* Prevents division by zero. */
-		return (y1);
-	/* Linear interpolation. */
-	return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1));
-}
-
-void
-athn_get_lg_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
-    uint8_t ctl, const struct ar_cal_target_power_leg *tgt, int nchans,
-    uint8_t tpow[4])
-{
-	uint8_t fbin;
-	int i, lo, hi;
-
-	/* Find interval (lower and upper indices.) */
-	fbin = athn_chan2fbin(c);
-	for (i = 0; i < nchans; i++) {
-		if (tgt[i].bChannel == AR_BCHAN_UNUSED ||
-		    tgt[i].bChannel > fbin)
-			break;
-	}
-	hi = i;
-	lo = hi - 1;
-	if (lo == -1)
-		lo = hi;
-	else if (hi == nchans || tgt[hi].bChannel == AR_BCHAN_UNUSED)
-		hi = lo;
-
-	/* Interpolate values. */
-	for (i = 0; i < 4; i++) {
-		tpow[i] = athn_interpolate(fbin,
-		    tgt[lo].bChannel, tgt[lo].tPow2x[i],
-		    tgt[hi].bChannel, tgt[hi].tPow2x[i]);
-	}
-	/* XXX Apply conformance test limit. */
-}
-
-#ifndef IEEE80211_NO_HT
-void
-athn_get_ht_tpow(struct athn_softc *sc, struct ieee80211_channel *c,
-    uint8_t ctl, const struct ar_cal_target_power_ht *tgt, int nchans,
-    uint8_t tpow[8])
-{
-	uint8_t fbin;
-	int i, lo, hi;
-
-	/* Find interval (lower and upper indices.) */
-	fbin = athn_chan2fbin(c);
-	for (i = 0; i < nchans; i++) {
-		if (tgt[i].bChannel == AR_BCHAN_UNUSED ||
-		    tgt[i].bChannel > fbin)
-			break;
-	}
-	hi = i;
-	lo = hi - 1;
-	if (lo == -1)
-		lo = hi;
-	else if (hi == nchans || tgt[hi].bChannel == AR_BCHAN_UNUSED)
-		hi = lo;
-
-	/* Interpolate values. */
-	for (i = 0; i < 8; i++) {
-		tpow[i] = athn_interpolate(fbin,
-		    tgt[lo].bChannel, tgt[lo].tPow2x[i],
-		    tgt[hi].bChannel, tgt[hi].tPow2x[i]);
-	}
-	/* XXX Apply conformance test limit. */
-}
-#endif
-
-void
-athn_write_txpower(struct athn_softc *sc, int16_t power[ATHN_POWER_COUNT])
-{
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE1,
-	    (power[ATHN_POWER_OFDM18  ] & 0x3f) << 24 |
-	    (power[ATHN_POWER_OFDM12  ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_OFDM9   ] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_OFDM6   ] & 0x3f));
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE2,
-	    (power[ATHN_POWER_OFDM54  ] & 0x3f) << 24 |
-	    (power[ATHN_POWER_OFDM48  ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_OFDM36  ] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_OFDM24  ] & 0x3f));
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE3,
-	    (power[ATHN_POWER_CCK2_SP ] & 0x3f) << 24 |
-	    (power[ATHN_POWER_CCK2_LP ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_XR      ] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_CCK1_LP ] & 0x3f));
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE4,
-	    (power[ATHN_POWER_CCK11_SP] & 0x3f) << 24 |
-	    (power[ATHN_POWER_CCK11_LP] & 0x3f) << 16 |
-	    (power[ATHN_POWER_CCK55_SP] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_CCK55_LP] & 0x3f));
-#ifndef IEEE80211_NO_HT
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE5,
-	    (power[ATHN_POWER_HT20(3) ] & 0x3f) << 24 |
-	    (power[ATHN_POWER_HT20(2) ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_HT20(1) ] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_HT20(0) ] & 0x3f));
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE6,
-	    (power[ATHN_POWER_HT20(7) ] & 0x3f) << 24 |
-	    (power[ATHN_POWER_HT20(6) ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_HT20(5) ] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_HT20(4) ] & 0x3f));
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE7,
-	    (power[ATHN_POWER_HT40(3) ] & 0x3f) << 24 |
-	    (power[ATHN_POWER_HT40(2) ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_HT40(1) ] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_HT40(0) ] & 0x3f));
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE8,
-	    (power[ATHN_POWER_HT40(7) ] & 0x3f) << 24 |
-	    (power[ATHN_POWER_HT40(6) ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_HT40(5) ] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_HT40(4) ] & 0x3f));
-	AR_WRITE(sc, AR_PHY_POWER_TX_RATE9,
-	    (power[ATHN_POWER_OFDM_EXT] & 0x3f) << 24 |
-	    (power[ATHN_POWER_CCK_EXT ] & 0x3f) << 16 |
-	    (power[ATHN_POWER_OFDM_DUP] & 0x3f) <<  8 |
-	    (power[ATHN_POWER_CCK_DUP ] & 0x3f));
-#endif
-}
-
-void
-athn_init_baseband(struct athn_softc *sc)
-{
-	uint32_t synth_delay;
-
-	synth_delay = athn_synth_delay(sc);
-	/* Activate the PHY (includes baseband activate and synthesizer on). */
-	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-	DELAY(AR_BASE_PHY_ACTIVE_DELAY + synth_delay);
-}
-
 void
 athn_init_dma(struct athn_softc *sc)
 {
 	uint32_t reg;
 
-	/* Set AHB not to do cacheline prefetches. */
-	AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
-
+	if (!AR_SREV_9380_10_OR_LATER(sc)) {
+		/* Set AHB not to do cacheline prefetches. */
+		AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
+	}
 	reg = AR_READ(sc, AR_TXCFG);
 	/* Let MAC DMA reads be in 128-byte chunks. */
 	reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);
@@ -2777,7 +1524,7 @@ athn_init_dma(struct athn_softc *sc)
 	/* Set initial Tx trigger level. */
 	if (AR_SREV_9285(sc))
 		reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);
-	else
+	else if (!AR_SREV_9380_10_OR_LATER(sc))
 		reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);
 	AR_WRITE(sc, AR_TXCFG, reg);
 
@@ -2793,6 +1540,10 @@ athn_init_dma(struct athn_softc *sc)
 	AR_WRITE(sc, AR_PCU_TXBUF_CTRL, AR_SREV_9285(sc) ?
 	    AR9285_PCU_TXBUF_CTRL_USABLE_SIZE :
 	    AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+
+	/* Reset Tx status ring. */
+	if (AR_SREV_9380_10_OR_LATER(sc))
+		ar9003_reset_txsring(sc);
 }
 
 void
@@ -2844,6 +1595,29 @@ athn_rx_abort(struct athn_softc *sc)
 	return (ETIMEDOUT);
 }
 
+void
+athn_tx_reclaim(struct athn_softc *sc, int qid)
+{
+	struct athn_txq *txq = &sc->txq[qid];
+	struct athn_tx_buf *bf;
+
+	/* Reclaim all buffers queued in the specified Tx queue. */
+	/* NB: Tx DMA must be stopped. */
+	while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) {
+		SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
+
+		bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
+		    bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
+		bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
+		m_freem(bf->bf_m);
+		bf->bf_m = NULL;
+		bf->bf_ni = NULL;	/* Nodes already freed! */
+
+		/* Link Tx buffer back to global free list. */
+		SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
+	}
+}
+
 int
 athn_tx_pending(struct athn_softc *sc, int qid)
 {
@@ -2889,362 +1663,6 @@ athn_stop_tx_dma(struct athn_softc *sc, int qid)
 	AR_WRITE(sc, AR_Q_TXD, 0);
 }
 
-void
-athn_tx_reclaim(struct athn_softc *sc, int qid)
-{
-	struct athn_txq *txq = &sc->txq[qid];
-	struct athn_tx_buf *bf;
-
-	/* Reclaim all buffers queued in the specified Tx queue. */
-	/* NB: Tx DMA must be stopped. */
-	while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) {
-		SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
-
-		bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
-		    bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
-		bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
-		m_freem(bf->bf_m);
-		bf->bf_m = NULL;
-		bf->bf_ni = NULL;	/* Nodes already freed! */
-
-		/* Link Tx buffer back to global free list. */
-		SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
-	}
-}
-
-#if NBPFILTER > 0
-void
-athn_rx_radiotap(struct athn_softc *sc, struct mbuf *m, struct ar_rx_desc *ds)
-{
-#define IEEE80211_RADIOTAP_F_SHORTGI	0x80	/* XXX from FBSD */
-
-	struct athn_rx_radiotap_header *tap = &sc->sc_rxtap;
-	struct ieee80211com *ic = &sc->sc_ic;
-	struct mbuf mb;
-	uint64_t tsf;
-	uint32_t tstamp;
-	uint8_t rate;
-
-	/* Extend the 15-bit timestamp from Rx descriptor to 64-bit TSF. */
-	tstamp = ds->ds_status2;
-	tsf = AR_READ(sc, AR_TSF_U32);
-	tsf = tsf << 32 | AR_READ(sc, AR_TSF_L32);
-	if ((tsf & 0x7fff) < tstamp)
-		tsf -= 0x8000;
-	tsf = (tsf & ~0x7fff) | tstamp;
-
-	tap->wr_flags = IEEE80211_RADIOTAP_F_FCS;
-	tap->wr_tsft = htole64(tsf);
-	tap->wr_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
-	tap->wr_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
-	tap->wr_dbm_antsignal = MS(ds->ds_status4, AR_RXS4_RSSI_COMBINED);
-	/* XXX noise. */
-	tap->wr_antenna = MS(ds->ds_status3, AR_RXS3_ANTENNA);
-	tap->wr_rate = 0;	/* In case it can't be found below. */
-	if (AR_SREV_5416_20_OR_LATER(sc))
-		rate = MS(ds->ds_status0, AR_RXS0_RATE);
-	else
-		rate = MS(ds->ds_status3, AR_RXS3_RATE);
-	if (rate & 0x80) {		/* HT. */
-		/* Bit 7 set means HT MCS instead of rate. */
-		tap->wr_rate = rate;
-		if (!(ds->ds_status3 & AR_RXS3_GI))
-			tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
-
-	} else if (rate & 0x10) {	/* CCK. */
-		if (rate & 0x04)
-			tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
-		switch (rate & ~0x14) {
-		case 0xb: tap->wr_rate =   2; break;
-		case 0xa: tap->wr_rate =   4; break;
-		case 0x9: tap->wr_rate =  11; break;
-		case 0x8: tap->wr_rate =  22; break;
-		}
-	} else {			/* OFDM. */
-		switch (rate) {
-		case 0xb: tap->wr_rate =  12; break;
-		case 0xf: tap->wr_rate =  18; break;
-		case 0xa: tap->wr_rate =  24; break;
-		case 0xe: tap->wr_rate =  36; break;
-		case 0x9: tap->wr_rate =  48; break;
-		case 0xd: tap->wr_rate =  72; break;
-		case 0x8: tap->wr_rate =  96; break;
-		case 0xc: tap->wr_rate = 108; break;
-		}
-	}
-	mb.m_data = (caddr_t)tap;
-	mb.m_len = sc->sc_rxtap_len;
-	mb.m_next = m;
-	mb.m_nextpkt = NULL;
-	mb.m_type = 0;
-	mb.m_flags = 0;
-	bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN);
-}
-#endif
-
-static __inline int
-athn_rx_process(struct athn_softc *sc)
-{
-	struct ieee80211com *ic = &sc->sc_ic;
-	struct ifnet *ifp = &ic->ic_if;
-	struct athn_rxq *rxq = &sc->rxq;
-	struct athn_rx_buf *bf, *nbf;
-	struct ar_rx_desc *ds;
-	struct ieee80211_frame *wh;
-	struct ieee80211_rxinfo rxi;
-	struct ieee80211_node *ni;
-	struct mbuf *m, *m1;
-	int error, len;
-
-	bf = SIMPLEQ_FIRST(&rxq->head);
-	if (__predict_false(bf == NULL)) {	/* Should not happen. */
-		printf("%s: Rx queue is empty!\n", sc->sc_dev.dv_xname);
-		return (ENOENT);
-	}
-	ds = bf->bf_desc;
-
-	if (!(ds->ds_status8 & AR_RXS8_DONE)) {
-		/*
-		 * On some parts, the status words can get corrupted
-		 * (including the "done" bit), so we check the next
-		 * descriptor "done" bit.  If it is set, it is a good
-		 * indication that the status words are corrupted, so
-		 * we skip this descriptor and drop the frame.
-		 */
-		nbf = SIMPLEQ_NEXT(bf, bf_list);
-		if (nbf != NULL &&
-		    (nbf->bf_desc->ds_status8 & AR_RXS8_DONE)) {
-			DPRINTF(("corrupted descriptor status=0x%x\n",
-			    ds->ds_status8));
-			/* HW will not "move" RXDP in this case, so do it. */
-			AR_WRITE(sc, AR_RXDP, nbf->bf_daddr);
-			ifp->if_ierrors++;
-			goto skip;
-		}
-		return (EBUSY);
-	}
-
-	if (__predict_false(ds->ds_status1 & AR_RXS1_MORE)) {
-		/* Drop frames that span multiple Rx descriptors. */
-		DPRINTF(("dropping split frame\n"));
-		ifp->if_ierrors++;
-		goto skip;
-	}
-	if (!(ds->ds_status8 & AR_RXS8_FRAME_OK)) {
-		if (ds->ds_status8 & AR_RXS8_CRC_ERR)
-			DPRINTFN(6, ("CRC error\n"));
-		else if (ds->ds_status8 & AR_RXS8_PHY_ERR)
-			DPRINTFN(6, ("PHY error=0x%x\n",
-			    MS(ds->ds_status8, AR_RXS8_PHY_ERR_CODE)));
-		else if (ds->ds_status8 & AR_RXS8_DECRYPT_CRC_ERR)
-			DPRINTFN(6, ("Decryption CRC error\n"));
-		else if (ds->ds_status8 & AR_RXS8_MICHAEL_ERR) {
-			DPRINTFN(2, ("Michael MIC failure\n"));
-			/* Report Michael MIC failures to net80211. */
-			ic->ic_stats.is_rx_locmicfail++;
-			ieee80211_michael_mic_failure(ic, 0);
-			/*
-			 * XXX Check that it is not a control frame
-			 * (invalid MIC failures on valid ctl frames.)
-			 */
-		}
-		ifp->if_ierrors++;
-		goto skip;
-	}
-
-	len = MS(ds->ds_status1, AR_RXS1_DATA_LEN);
-	if (__predict_false(len == 0 || len > ATHN_RXBUFSZ)) {
-		DPRINTF(("corrupted descriptor length=%d\n", len));
-		ifp->if_ierrors++;
-		goto skip;
-	}
-
-	/* Allocate a new Rx buffer. */
-	m1 = MCLGETI(NULL, M_DONTWAIT, NULL, ATHN_RXBUFSZ);
-	if (__predict_false(m1 == NULL)) {
-		ic->ic_stats.is_rx_nombuf++;
-		ifp->if_ierrors++;
-		goto skip;
-	}
-
-	/* Sync and unmap the old Rx buffer. */
-	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, ATHN_RXBUFSZ,
-	    BUS_DMASYNC_POSTREAD);
-	bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
-
-	/* Map the new Rx buffer. */
-	error = bus_dmamap_load(sc->sc_dmat, bf->bf_map, mtod(m1, void *),
-	    ATHN_RXBUFSZ, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ);
-	if (__predict_false(error != 0)) {
-		m_freem(m1);
-
-		/* Remap the old Rx buffer or panic. */
-		error = bus_dmamap_load(sc->sc_dmat, bf->bf_map,
-		    mtod(bf->bf_m, void *), ATHN_RXBUFSZ, NULL,
-		    BUS_DMA_NOWAIT | BUS_DMA_READ);
-		KASSERT(error != 0);
-		ifp->if_ierrors++;
-		goto skip;
-	}
-
-	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
-	    BUS_DMASYNC_PREREAD);
-
-	/* Write physical address of new Rx buffer. */
-	ds->ds_data = bf->bf_map->dm_segs[0].ds_addr;
-
-	m = bf->bf_m;
-	bf->bf_m = m1;
-
-	/* Finalize mbuf. */
-	m->m_pkthdr.rcvif = ifp;
-	m->m_pkthdr.len = m->m_len = len;
-
-	/* Grab a reference to the source node. */
-	wh = mtod(m, struct ieee80211_frame *);
-	ni = ieee80211_find_rxnode(ic, wh);
-
-	/* Remove any HW padding after the 802.11 header. */
-	if (!(wh->i_fc[0] & IEEE80211_FC0_TYPE_CTL)) {
-		u_int hdrlen = ieee80211_get_hdrlen(wh);
-		if (hdrlen & 3) {
-			ovbcopy(wh, (caddr_t)wh + 2, hdrlen);
-			m_adj(m, 2);	/* XXX sure? */
-		}
-	}
-#if NBPFILTER > 0
-	if (__predict_false(sc->sc_drvbpf != NULL))
-		athn_rx_radiotap(sc, m, ds);
-#endif
-	/* Trim 802.11 FCS after radiotap. */
-	m_adj(m, -IEEE80211_CRC_LEN);
-
-	/* Send the frame to the 802.11 layer. */
-	rxi.rxi_flags = 0;	/* XXX */
-	rxi.rxi_rssi = MS(ds->ds_status4, AR_RXS4_RSSI_COMBINED);
-	rxi.rxi_tstamp = ds->ds_status2;
-	ieee80211_input(ifp, m, ni, &rxi);
-
-	/* Node is no longer needed. */
-	ieee80211_release_node(ic, ni);
-
- skip:
-	/* Unlink this descriptor from head. */
-	SIMPLEQ_REMOVE_HEAD(&rxq->head, bf_list);
-	memset(&ds->ds_status0, 0, 36);	/* XXX Really needed? */
-	ds->ds_status8 &= ~AR_RXS8_DONE;
-	ds->ds_link = 0;
-
-	/* Re-use this descriptor and link it to tail. */
-	if (__predict_true(!SIMPLEQ_EMPTY(&rxq->head)))
-		rxq->lastds->ds_link = bf->bf_daddr;
-	else
-		AR_WRITE(sc, AR_RXDP, bf->bf_daddr);
-	SIMPLEQ_INSERT_TAIL(&rxq->head, bf, bf_list);
-	rxq->lastds = ds;
-
-	/* Re-enable Rx. */
-	AR_WRITE(sc, AR_CR, AR_CR_RXE);
-	return (0);
-}
-
-void
-athn_rx_intr(struct athn_softc *sc)
-{
-	while (athn_rx_process(sc) == 0);
-}
-
-int
-athn_tx_process(struct athn_softc *sc, int qid)
-{
-	struct ieee80211com *ic = &sc->sc_ic;
-	struct ifnet *ifp = &ic->ic_if;
-	struct athn_txq *txq = &sc->txq[qid];
-	struct athn_node *an;
-	struct athn_tx_buf *bf;
-	struct ar_tx_desc *ds;
-	uint8_t failcnt;
-
-	bf = SIMPLEQ_FIRST(&txq->head);
-	if (__predict_false(bf == NULL))
-		return (ENOENT);
-	/* Get descriptor of last DMA segment. */
-	ds = &bf->bf_descs[bf->bf_map->dm_nsegs - 1];
-
-	if (!(ds->ds_status9 & AR_TXS9_DONE))
-		return (EBUSY);
-
-	SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
-	ifp->if_opackets++;
-
-	sc->sc_tx_timer = 0;
-
-	if (ds->ds_status1 & AR_TXS1_EXCESSIVE_RETRIES)
-		ifp->if_oerrors++;
-
-	if (ds->ds_status1 & AR_TXS1_UNDERRUN)
-		athn_inc_tx_trigger_level(sc);
-
-	an = (struct athn_node *)bf->bf_ni;
-	/*
-	 * NB: the data fail count contains the number of un-acked tries
-	 * for the final series used.  We must add the number of tries for
-	 * each series that was fully processed.
-	 */
-	failcnt  = MS(ds->ds_status1, AR_TXS1_DATA_FAIL_CNT);
-	/* XXX Assume two tries per series. */
-	failcnt += MS(ds->ds_status9, AR_TXS9_FINAL_IDX) * 2;
-
-	/* Update rate control statistics. */
-	an->amn.amn_txcnt++;
-	if (failcnt > 0)
-		an->amn.amn_retrycnt++;
-
-	DPRINTFN(5, ("Tx done qid=%d status1=%d fail count=%d\n",
-	    qid, ds->ds_status1, failcnt));
-
-	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
-	    BUS_DMASYNC_POSTWRITE);
-	bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
-
-	m_freem(bf->bf_m);
-	bf->bf_m = NULL;
-	ieee80211_release_node(ic, bf->bf_ni);
-	bf->bf_ni = NULL;
-
-	/* Link Tx buffer back to global free list. */
-	SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
-	return (0);
-}
-
-void
-athn_tx_intr(struct athn_softc *sc)
-{
-	struct ieee80211com *ic = &sc->sc_ic;
-	struct ifnet *ifp = &ic->ic_if;
-	uint16_t mask = 0;
-	uint32_t reg;
-	int qid;
-
-	reg = AR_READ(sc, AR_ISR_S0_S);
-	mask |= MS(reg, AR_ISR_S0_QCU_TXOK);
-	mask |= MS(reg, AR_ISR_S0_QCU_TXDESC);
-
-	reg = AR_READ(sc, AR_ISR_S1_S);
-	mask |= MS(reg, AR_ISR_S1_QCU_TXERR);
-	mask |= MS(reg, AR_ISR_S1_QCU_TXEOL);
-
-	DPRINTFN(4, ("Tx interrupt mask=0x%x\n", mask));
-	for (qid = 0; mask != 0; mask >>= 1, qid++) {
-		if (mask & 1)
-			while (athn_tx_process(sc, qid) == 0);
-	}
-	if (!SIMPLEQ_EMPTY(&sc->txbufs)) {
-		ifp->if_flags &= ~IFF_OACTIVE;
-		athn_start(ifp);
-	}
-}
-
 int
 athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags)
 {
@@ -3268,364 +1686,10 @@ athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags)
 #undef divround
 }
 
-int
-athn_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
-{
-	struct ieee80211com *ic = &sc->sc_ic;
-	struct ieee80211_key *k = NULL;
-	struct ieee80211_frame *wh;
-	struct athn_series series[4];
-	struct ar_tx_desc *ds, *lastds;
-	struct athn_txq *txq;
-	struct athn_tx_buf *bf;
-	struct athn_node *an = (void *)ni;
-	struct mbuf *m1;
-	uintptr_t entry;
-	uint16_t qos;
-	uint8_t txpower, type, encrtype, tid, ridx[4];
-	int i, error, totlen, hasqos, qid;
-
-	/* Grab a Tx buffer from our global free list. */
-	bf = SIMPLEQ_FIRST(&sc->txbufs);
-	KASSERT(bf != NULL);
-	SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list);
-
-	/* Map 802.11 frame type to hardware frame type. */
-	wh = mtod(m, struct ieee80211_frame *);
-	if ((wh->i_fc[0] &
-	    (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
-	    (IEEE80211_FC0_TYPE_MGT  | IEEE80211_FC0_SUBTYPE_BEACON))
-		type = AR_FRAME_TYPE_BEACON;
-	else if ((wh->i_fc[0] &
-	    (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
-	    (IEEE80211_FC0_TYPE_MGT  | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
-		type = AR_FRAME_TYPE_PROBE_RESP;
-	else if ((wh->i_fc[0] &
-	    (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
-	    (IEEE80211_FC0_TYPE_MGT  | IEEE80211_FC0_SUBTYPE_ATIM))
-		type = AR_FRAME_TYPE_ATIM;
-	else if ((wh->i_fc[0] &
-	    (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
-	    (IEEE80211_FC0_TYPE_CTL  | IEEE80211_FC0_SUBTYPE_PS_POLL))
-		type = AR_FRAME_TYPE_PSPOLL;
-	else
-		type = AR_FRAME_TYPE_NORMAL;
-
-	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
-		k = ieee80211_get_txkey(ic, wh, ni);
-		if ((m = ieee80211_encrypt(ic, m, k)) == NULL)
-			return (ENOBUFS);
-		wh = mtod(m, struct ieee80211_frame *);
-	}
-
-	/* XXX 2-byte padding for QoS and 4-addr headers. */
-
-	/* Select the HW Tx queue to use for this frame. */
-	if ((hasqos = ieee80211_has_qos(wh))) {
-		qos = ieee80211_get_qos(wh);
-		tid = qos & IEEE80211_QOS_TID;
-		qid = athn_ac2qid[ieee80211_up_to_ac(ic, tid)];
-	} else if (type == AR_FRAME_TYPE_BEACON) {
-		qid = ATHN_QID_BEACON;
-	} else if (type == AR_FRAME_TYPE_PSPOLL) {
-		qid = ATHN_QID_PSPOLL;
-	} else
-		qid = ATHN_QID_AC_BE;
-	txq = &sc->txq[qid];
-
-	/* Select the transmit rates to use for this frame. */
-	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
-	    (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
-	    IEEE80211_FC0_TYPE_DATA) {
-		/* Use lowest rate for all tries. */
-		ridx[0] = ridx[1] = ridx[2] = ridx[3] =
-		    (ic->ic_curmode == IEEE80211_MODE_11A) ?
-			ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK1;
-	} else if (ic->ic_fixed_rate != -1) {
-		/* Use same fixed rate for all tries. */
-		ridx[0] = ridx[1] = ridx[2] = ridx[3] =
-		    sc->fixed_ridx;
-	} else {
-		int txrate = ni->ni_txrate;
-		/* Use fallback table of the node. */
-		for (i = 0; i < 4; i++) {
-			ridx[i] = an->ridx[txrate];
-			txrate = an->fallback[txrate];
-		}
-	}
-
-#if NBPFILTER > 0
-	if (__predict_false(sc->sc_drvbpf != NULL)) {
-		struct athn_tx_radiotap_header *tap = &sc->sc_txtap;
-		struct mbuf mb;
-
-		tap->wt_flags = 0;
-		/* Use initial transmit rate. */
-		tap->wt_rate = athn_rates[ridx[0]].rate;
-		tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq);
-		tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags);
-		tap->wt_hwqueue = qid;
-		if (ridx[0] != ATHN_RIDX_CCK1 &&
-		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
-			tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
-		mb.m_data = (caddr_t)tap;
-		mb.m_len = sc->sc_txtap_len;
-		mb.m_next = m;
-		mb.m_nextpkt = NULL;
-		mb.m_type = 0;
-		mb.m_flags = 0;
-		bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT);
-	}
-#endif
-
-	/* DMA map mbuf. */
-	error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
-	    BUS_DMA_NOWAIT | BUS_DMA_WRITE);
-	if (__predict_false(error != 0)) {
-		if (error != EFBIG) {
-			printf("%s: can't map mbuf (error %d)\n",
-			    sc->sc_dev.dv_xname, error);
-			m_freem(m);
-			return (error);
-		}
-		/*
-		 * DMA mapping requires too many DMA segments; linearize
-		 * mbuf in kernel virtual address space and retry.
-		 */
-		MGETHDR(m1, M_DONTWAIT, MT_DATA);
-		if (m1 == NULL) {
-			m_freem(m);
-			return (ENOBUFS);
-		}
-		if (m->m_pkthdr.len > MHLEN) {
-			MCLGET(m1, M_DONTWAIT);
-			if (!(m1->m_flags & M_EXT)) {
-				m_freem(m);
-				m_freem(m1);
-				return (ENOBUFS);
-			}
-		}
-		m_copydata(m, 0, m->m_pkthdr.len, mtod(m1, caddr_t));
-		m1->m_pkthdr.len = m1->m_len = m->m_pkthdr.len;
-		m_freem(m);
-		m = m1;
-
-		error = bus_dmamap_load_mbuf(sc->sc_dmat, bf->bf_map, m,
-		    BUS_DMA_NOWAIT | BUS_DMA_WRITE);
-		if (error != 0) {
-			printf("%s: can't map mbuf (error %d)\n",
-			    sc->sc_dev.dv_xname, error);
-			m_freem(m);
-			return (error);
-		}
-	}
-	bf->bf_m = m;
-	bf->bf_ni = ni;
-
-	wh = mtod(m, struct ieee80211_frame *);
-
-	totlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
-
-	/* Clear all Tx descriptors that we will use. */
-	memset(bf->bf_descs, 0, bf->bf_map->dm_nsegs * sizeof (*ds));
-
-	/* Setup first Tx descriptor. */
-	ds = &bf->bf_descs[0];
-
-	ds->ds_ctl0 = AR_TXC0_INTR_REQ | AR_TXC0_CLR_DEST_MASK;
-	txpower = AR_MAX_RATE_POWER;	/* Get from per-rate registers. */
-	ds->ds_ctl0 |= SM(AR_TXC0_XMIT_POWER, txpower);
-
-	ds->ds_ctl1 = SM(AR_TXC1_FRAME_TYPE, type);
-
-	if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
-	    (hasqos && (qos & IEEE80211_QOS_ACK_POLICY_MASK) ==
-	     IEEE80211_QOS_ACK_POLICY_NOACK))
-		ds->ds_ctl1 |= AR_TXC1_NO_ACK;
-
-	if (0 && wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
-		/* Retrieve key for encryption. */
-		k = ieee80211_get_txkey(ic, wh, ni);
-		/*
-		 * Map 802.11 cipher to hardware encryption type and
-		 * compute crypto overhead.
-		 */
-		switch (k->k_cipher) {
-		case IEEE80211_CIPHER_WEP40:
-		case IEEE80211_CIPHER_WEP104:
-			encrtype = AR_ENCR_TYPE_WEP;
-			totlen += 8;
-			break;
-		case IEEE80211_CIPHER_TKIP:
-			encrtype = AR_ENCR_TYPE_TKIP;
-			totlen += 20;
-			break;
-		case IEEE80211_CIPHER_CCMP:
-			encrtype = AR_ENCR_TYPE_AES;
-			totlen += 16;
-			break;
-		default:
-			panic("unsupported cipher");	/* XXX BIP? */
-		}
-		/*
-		 * NB: The key cache entry index is stored in the key
-		 * private field when the key is installed.
-		 */
-		entry = (uintptr_t)k->k_priv;
-		ds->ds_ctl1 |= SM(AR_TXC1_DEST_IDX, entry);
-		ds->ds_ctl0 |= AR_TXC0_DEST_IDX_VALID;
-	} else
-		encrtype = AR_ENCR_TYPE_CLEAR;
-	ds->ds_ctl6 = SM(AR_TXC6_ENCR_TYPE, encrtype);
-
-	/* Check if frame must be protected using RTS/CTS or CTS-to-self. */
-	if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
-		/* NB: Group frames are sent using CCK in 802.11b/g. */
-		if (totlen > ic->ic_rtsthreshold) {
-			ds->ds_ctl0 |= AR_TXC0_RTS_ENABLE;
-		} else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
-		    athn_rates[ridx[0]].phy == IEEE80211_T_OFDM) {
-			if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
-				ds->ds_ctl0 |= AR_TXC0_RTS_ENABLE;
-			else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
-				ds->ds_ctl0 |= AR_TXC0_CTS_ENABLE;
-		}
-	}
-	if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
-		/* Disable multi-rate retries when protection is used. */
-		ridx[1] = ridx[2] = ridx[3] = ridx[0];
-	}
-	/* Setup multi-rate retries. */
-	for (i = 0; i < 4; i++) {
-		series[i].hwrate = athn_rates[ridx[i]].hwrate;
-		if (athn_rates[ridx[i]].phy == IEEE80211_T_DS &&
-		    ridx[i] != ATHN_RIDX_CCK1 &&
-		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
-			series[i].hwrate |= 0x04;
-		series[i].dur = 0;
-	}
-	if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
-		/* Compute duration for each series. */
-		for (i = 0; i < 4; i++) {
-			series[i].dur = athn_txtime(sc, IEEE80211_ACK_LEN,
-			    athn_rates[ridx[i]].rspridx, ic->ic_flags);
-		}
-	}
-
-	/* Write number of tries for each series. */
-	ds->ds_ctl2 =
-	    SM(AR_TXC2_XMIT_DATA_TRIES0, 2) |
-	    SM(AR_TXC2_XMIT_DATA_TRIES1, 2) |
-	    SM(AR_TXC2_XMIT_DATA_TRIES2, 2) |
-	    SM(AR_TXC2_XMIT_DATA_TRIES3, 4);
-
-	/* Tell HW to update duration field in 802.11 header. */
-	if (type != AR_FRAME_TYPE_PSPOLL)
-		ds->ds_ctl2 |= AR_TXC2_DUR_UPDATE_ENA;
-
-	/* Write Tx rate for each series. */
-	ds->ds_ctl3 =
-	    SM(AR_TXC3_XMIT_RATE0, series[0].hwrate) |
-	    SM(AR_TXC3_XMIT_RATE1, series[1].hwrate) |
-	    SM(AR_TXC3_XMIT_RATE2, series[2].hwrate) |
-	    SM(AR_TXC3_XMIT_RATE3, series[3].hwrate);
-
-	/* Write duration for each series. */
-	ds->ds_ctl4 =
-	    SM(AR_TXC4_PACKET_DUR0, series[0].dur) |
-	    SM(AR_TXC4_PACKET_DUR1, series[1].dur);
-	ds->ds_ctl5 =
-	    SM(AR_TXC5_PACKET_DUR2, series[2].dur) |
-	    SM(AR_TXC5_PACKET_DUR3, series[3].dur);
-
-	/* Use the same Tx chains for all tries. */
-	ds->ds_ctl7 =
-	    SM(AR_TXC7_CHAIN_SEL0, sc->txchainmask) |
-	    SM(AR_TXC7_CHAIN_SEL1, sc->txchainmask) |
-	    SM(AR_TXC7_CHAIN_SEL2, sc->txchainmask) |
-	    SM(AR_TXC7_CHAIN_SEL3, sc->txchainmask);
-#ifdef notyet
-#ifndef IEEE80211_NO_HT
-	/* Use the same short GI setting for all tries. */
-	if (ic->ic_flags & IEEE80211_F_SHGI)
-		ds->ds_ctl7 |= AR_TXC7_GI0123;
-	/* Use the same channel width for all tries. */
-	if (ic->ic_flags & IEEE80211_F_CBW40)
-		ds->ds_ctl7 |= AR_TXC7_2040_0123;
-#endif
-#endif
-
-	if (ds->ds_ctl0 & (AR_TXC0_RTS_ENABLE | AR_TXC0_CTS_ENABLE)) {
-		uint8_t protridx, hwrate;
-		uint16_t dur = 0;
-
-		/* Use the same protection mode for all tries. */
-		if (ds->ds_ctl0 & AR_TXC0_RTS_ENABLE) {
-			ds->ds_ctl4 |= AR_TXC4_RTSCTS_QUAL01;
-			ds->ds_ctl5 |= AR_TXC5_RTSCTS_QUAL23;
-		}
-		/* Select protection rate (suboptimal but ok.) */
-		protridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
-		    ATHN_RIDX_OFDM6 : ATHN_RIDX_CCK2;
-		if (ds->ds_ctl0 & AR_TXC0_RTS_ENABLE) {
-			/* Account for CTS duration. */
-			dur += athn_txtime(sc, IEEE80211_ACK_LEN,
-			    athn_rates[protridx].rspridx, ic->ic_flags);
-		}
-		dur += athn_txtime(sc, totlen, ridx[0], ic->ic_flags);
-		if (!(ds->ds_ctl1 & AR_TXC1_NO_ACK)) {
-			/* Account for ACK duration. */
-			dur += athn_txtime(sc, IEEE80211_ACK_LEN,
-			    athn_rates[ridx[0]].rspridx, ic->ic_flags);
-		}
-		/* Write protection frame duration and rate. */
-		ds->ds_ctl2 |= SM(AR_TXC2_BURST_DUR, dur);
-		hwrate = athn_rates[protridx].hwrate;
-		if (protridx == ATHN_RIDX_CCK2 &&
-		    (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
-			hwrate |= 0x04;
-		ds->ds_ctl7 |= SM(AR_TXC7_RTSCTS_RATE, hwrate);
-	}
-
-	/* Finalize first Tx descriptor and fill others (if any.) */
-	ds->ds_ctl0 |= SM(AR_TXC0_FRAME_LEN, totlen);
-
-	for (i = 0; i < bf->bf_map->dm_nsegs; i++, ds++) {
-		ds->ds_data = bf->bf_map->dm_segs[i].ds_addr;
-		ds->ds_ctl1 |= SM(AR_TXC1_BUF_LEN,
-		    bf->bf_map->dm_segs[i].ds_len);
-
-		if (i != bf->bf_map->dm_nsegs - 1)
-			ds->ds_ctl1 |= AR_TXC1_MORE;
-		ds->ds_link = 0;
-
-		/* Chain Tx descriptor. */
-		if (i != 0)
-			lastds->ds_link = bf->bf_daddr + i * sizeof (*ds);
-		lastds = ds;
-	}
-	if (!SIMPLEQ_EMPTY(&txq->head))
-		txq->lastds->ds_link = bf->bf_daddr;
-	else
-		AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
-	txq->lastds = lastds;
-	SIMPLEQ_INSERT_TAIL(&txq->head, bf, bf_list);
-
-	DPRINTFN(6, ("Tx qid=%d nsegs=%d ctl0=0x%x ctl1=0x%x ctl3=0x%x\n",
-	    qid, bf->bf_map->dm_nsegs, bf->bf_descs[0].ds_ctl0,
-	    bf->bf_descs[0].ds_ctl1, bf->bf_descs[0].ds_ctl3));
-
-	bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0, bf->bf_map->dm_mapsize,
-	    BUS_DMASYNC_PREWRITE);
-
-	/* Kick Tx. */
-	AR_WRITE(sc, AR_Q_TXE, 1 << qid);
-	return (0);
-}
-
 void
 athn_init_tx_queues(struct athn_softc *sc)
 {
+	uint32_t reg;
 	int qid;
 
 	for (qid = 0; qid < ATHN_QID_COUNT; qid++) {
@@ -3652,8 +1716,15 @@ athn_init_tx_queues(struct athn_softc *sc)
 	       AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) |
 	    AR_D_MISC_BEACON_USE |
 	    AR_D_MISC_POST_FR_BKOFF_DIS);
+	if (AR_SREV_9380_10_OR_LATER(sc)) {
+		/* CWmin and CWmax should be 0 for beacon queue. */
+		reg = AR_READ(sc, AR_DLCL_IFS(ATHN_QID_BEACON));
+		reg = RW(reg, AR_D_LCL_IFS_CWMIN, 0);
+		reg = RW(reg, AR_D_LCL_IFS_CWMAX, 0);
+		AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON), reg);
+	}
 
-	/* Init CAB queue. */
+	/* Init CAB (Content After Beacon) queue. */
 	AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB),
 	    AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 |
 	    AR_Q_MISC_CBR_INCR_DIS0);
@@ -3669,6 +1740,10 @@ athn_init_tx_queues(struct athn_softc *sc)
 	AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),
 	    AR_D_MISC_POST_FR_BKOFF_DIS);
 
+	if (AR_SREV_9380_10_OR_LATER(sc)) {
+		/* Enable MAC descriptor CRC check. */
+		AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
+	}
 	/* Enable DESC interrupts for all Tx queues. */
 	AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);
 	/* Enable EOL interrupts for all Tx queues except UAPSD. */
@@ -3676,108 +1751,6 @@ athn_init_tx_queues(struct athn_softc *sc)
 }
 
 void
-athn_set_viterbi_mask(struct athn_softc *sc, int bin)
-{
-	uint32_t mask[4], reg;
-	uint8_t m[62], p[62];	/* XXX use bit arrays? */
-	int i, bit, cur;
-
-	/* Compute pilot mask. */
-	cur = -6000;
-	for (i = 0; i < 4; i++) {
-		mask[i] = 0;
-		for (bit = 0; bit < 30; bit++) {
-			if (abs(cur - bin) < 100)
-				mask[i] |= 1 << bit;
-			cur += 100;
-		}
-		if (cur == 0)	/* Skip entry "0". */
-			cur = 100;
-	}
-	/* Write entries from -6000 to -3100. */
-	AR_WRITE(sc, AR_PHY_TIMING7, mask[0]);
-	AR_WRITE(sc, AR_PHY_TIMING9, mask[0]);
-	/* Write entries from -3000 to -100. */
-	AR_WRITE(sc, AR_PHY_TIMING8, mask[1]);
-	AR_WRITE(sc, AR_PHY_TIMING10, mask[1]);
-	/* Write entries from 100 to 3000. */
-	AR_WRITE(sc, AR_PHY_PILOT_MASK_01_30, mask[2]);
-	AR_WRITE(sc, AR_PHY_CHANNEL_MASK_01_30, mask[2]);
-	/* Write entries from 3100 to 6000. */
-	AR_WRITE(sc, AR_PHY_PILOT_MASK_31_60, mask[3]);
-	AR_WRITE(sc, AR_PHY_CHANNEL_MASK_31_60, mask[3]);
-
-	/* Compute viterbi mask. */
-	for (cur = 6100; cur >= 0; cur -= 100)
-		p[+cur / 100] = abs(cur - bin) < 75;
-	for (cur = -100; cur >= -6100; cur -= 100)
-		m[-cur / 100] = abs(cur - bin) < 75;
-
-	/* Write viterbi mask (XXX needs to be reworked.) */
-	reg =
-	    m[46] << 30 | m[47] << 28 | m[48] << 26 | m[49] << 24 |
-	    m[50] << 22 | m[51] << 20 | m[52] << 18 | m[53] << 16 |
-	    m[54] << 14 | m[55] << 12 | m[56] << 10 | m[57] <<  8 |
-	    m[58] <<  6 | m[59] <<  4 | m[60] <<  2 | m[61] <<  0;
-	AR_WRITE(sc, AR_PHY_BIN_MASK_1, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_46_61, reg);
-
-	/* XXX m[48] should be m[38] ? */
-	reg =             m[31] << 28 | m[32] << 26 | m[33] << 24 |
-	    m[34] << 22 | m[35] << 20 | m[36] << 18 | m[37] << 16 |
-	    m[48] << 14 | m[39] << 12 | m[40] << 10 | m[41] <<  8 |
-	    m[42] <<  6 | m[43] <<  4 | m[44] <<  2 | m[45] <<  0;
-	AR_WRITE(sc, AR_PHY_BIN_MASK_2, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_31_45, reg);
-
-	/* XXX This one is weird too. */
-	reg =
-	    m[16] << 30 | m[16] << 28 | m[18] << 26 | m[18] << 24 |
-	    m[20] << 22 | m[20] << 20 | m[22] << 18 | m[22] << 16 |
-	    m[24] << 14 | m[24] << 12 | m[25] << 10 | m[26] <<  8 |
-	    m[27] <<  6 | m[28] <<  4 | m[29] <<  2 | m[30] <<  0;
-	AR_WRITE(sc, AR_PHY_BIN_MASK_3, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_16_30, reg);
-
-	reg =
-	    m[ 0] << 30 | m[ 1] << 28 | m[ 2] << 26 | m[ 3] << 24 |
-	    m[ 4] << 22 | m[ 5] << 20 | m[ 6] << 18 | m[ 7] << 16 |
-	    m[ 8] << 14 | m[ 9] << 12 | m[10] << 10 | m[11] <<  8 |
-	    m[12] <<  6 | m[13] <<  4 | m[14] <<  2 | m[15] <<  0;
-	AR_WRITE(sc, AR_PHY_MASK_CTL, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_M_00_15, reg);
-
-	reg =             p[15] << 28 | p[14] << 26 | p[13] << 24 |
-	    p[12] << 22 | p[11] << 20 | p[10] << 18 | p[ 9] << 16 |
-	    p[ 8] << 14 | p[ 7] << 12 | p[ 6] << 10 | p[ 5] <<  8 |
-	    p[ 4] <<  6 | p[ 3] <<  4 | p[ 2] <<  2 | p[ 1] <<  0;
-	AR_WRITE(sc, AR_PHY_BIN_MASK2_1, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_15_01, reg);
-
-	reg =             p[30] << 28 | p[29] << 26 | p[28] << 24 |
-	    p[27] << 22 | p[26] << 20 | p[25] << 18 | p[24] << 16 |
-	    p[23] << 14 | p[22] << 12 | p[21] << 10 | p[20] <<  8 |
-	    p[19] <<  6 | p[18] <<  4 | p[17] <<  2 | p[16] <<  0;
-	AR_WRITE(sc, AR_PHY_BIN_MASK2_2, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_30_16, reg);
-
-	reg =             p[45] << 28 | p[44] << 26 | p[43] << 24 |
-	    p[42] << 22 | p[41] << 20 | p[40] << 18 | p[39] << 16 |
-	    p[38] << 14 | p[37] << 12 | p[36] << 10 | p[35] <<  8 |
-	    p[34] <<  6 | p[33] <<  4 | p[32] <<  2 | p[31] <<  0;
-	AR_WRITE(sc, AR_PHY_BIN_MASK2_3, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_45_31, reg);
-
-	reg =
-	    p[61] << 30 | p[60] << 28 | p[59] << 26 | p[58] << 24 |
-	    p[57] << 22 | p[56] << 20 | p[55] << 18 | p[54] << 16 |
-	    p[53] << 14 | p[52] << 12 | p[51] << 10 | p[50] <<  8 |
-	    p[49] <<  6 | p[48] <<  4 | p[47] <<  2 | p[46] <<  0;
-	AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);
-	AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);
-}
-
-void
 athn_set_beacon_timers(struct athn_softc *sc)
 {
 	struct ieee80211com *ic = &sc->sc_ic;
@@ -3845,22 +1818,6 @@ athn_set_beacon_timers(struct athn_softc *sc)
 }
 
 void
-athn_set_rf_mode(struct athn_softc *sc, struct ieee80211_channel *c)
-{
-	uint32_t reg;
-
-	reg = IEEE80211_IS_CHAN_2GHZ(c) ?
-	    AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
-	if (!AR_SREV_9280_10_OR_LATER(sc)) {
-		reg |= IEEE80211_IS_CHAN_2GHZ(c) ?
-		    AR_PHY_MODE_RF2GHZ : AR_PHY_MODE_RF5GHZ;
-	} else if (AR_SREV_9280_20(sc) && 0 /* XXX */) {
-		reg |= AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE;
-	}
-	AR_WRITE(sc, AR_PHY_MODE, reg);
-}
-
-void
 athn_set_opmode(struct athn_softc *sc)
 {
 	uint32_t reg;
@@ -3912,9 +1869,12 @@ athn_enable_interrupts(struct athn_softc *sc)
 
 	athn_disable_interrupts(sc);	/* XXX */
 
+	/* XXX cleanup, use sc->imask */
 	mask = AR_IMR_TXDESC | AR_IMR_TXEOL | AR_IMR_RXERR | AR_IMR_RXEOL |
 	    AR_IMR_RXORN | AR_IMR_GENTMR | AR_IMR_BCNMISC | AR_IMR_RXMINTR |
 	    AR_IMR_RXINTM;
+	if (AR_SREV_9380_10_OR_LATER(sc))
+		mask |= AR_IMR_RXERR | AR_IMR_HP_RXOK;
 	AR_WRITE(sc, AR_IMR, mask);
 
 	mask2 = AR_READ(sc, AR_IMR_S2);
@@ -3956,102 +1916,6 @@ athn_disable_interrupts(struct athn_softc *sc)
 }
 
 void
-athn_hw_init(struct athn_softc *sc, struct ieee80211_channel *c,
-    struct ieee80211_channel *extc)
-{
-	struct athn_ops *ops = &sc->ops;
-	const struct athn_ini *ini = sc->ini;
-	const uint32_t *pvals;
-	int i;
-
-	AR_WRITE(sc, AR_PHY(0), 0x00000007);
-	AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
-
-	if (!AR_SINGLE_CHIP(sc))
-		ar5416_reset_addac(sc, c);
-
-	AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
-
-	/* First initialization step (depends on channel band/bandwidth). */
-#ifndef IEEE80211_NO_HT
-	if (extc != NULL) {
-		if (IEEE80211_IS_CHAN_2GHZ(c))
-			pvals = ini->vals_2g40;
-		else
-			pvals = ini->vals_5g40;
-	} else
-#endif
-	{
-		if (IEEE80211_IS_CHAN_2GHZ(c))
-			pvals = ini->vals_2g20;
-		else
-			pvals = ini->vals_5g20;
-	}
-	DPRINTFN(4, ("writing per-mode init vals\n"));
-	for (i = 0; i < ini->nregs; i++) {
-		AR_WRITE(sc, ini->regs[i], pvals[i]);
-		if (AR_IS_ANALOG_REG(ini->regs[i]))
-			DELAY(100);
-		if ((i & 0x1f) == 0)
-			DELAY(1);
-	}
-
-	if (AR_SREV_9280_20(sc) || AR_SREV_9287_10_OR_LATER(sc))
-		ar9280_reset_rx_gain(sc, c);
-	if (AR_SREV_9280_20(sc) || AR_SREV_9285_12(sc) ||
-	    AR_SREV_9287_10_OR_LATER(sc))
-		ar9280_reset_tx_gain(sc, c);
-
-	/* Second initialization step (common to all channels). */
-	DPRINTFN(4, ("writing common init vals\n"));
-	for (i = 0; i < ini->ncmregs; i++) {
-		AR_WRITE(sc, ini->cmregs[i], ini->cmvals[i]);
-		if (AR_IS_ANALOG_REG(ini->cmregs[i]))
-			DELAY(100);
-		if ((i & 0x1f) == 0)
-			DELAY(1);
-	}
-
-	if (!AR_SINGLE_CHIP(sc))
-		ar5416_reset_bb_gain(sc, c);
-
-	/*
-	 * Set the RX_ABORT and RX_DIS bits to prevent frames with corrupted
-	 * descriptor status.
-	 */
-	AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
-
-	/* Hardware workarounds for occasional Rx data corruption. */
-	if (AR_SREV_9287_10_OR_LATER(sc))
-		AR_CLRBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_HWWAR1);
-	else if (AR_SREV_9280_10_OR_LATER(sc))
-		AR_CLRBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_HWWAR1 |
-		    AR_PCU_MISC_MODE2_HWWAR2);
-
-	if (AR_SREV_5416_20_OR_LATER(sc) && !AR_SREV_9280_10_OR_LATER(sc)) {
-		/* Disable baseband clock gating. */
-		AR_WRITE(sc, AR_PHY(651), 0x11);
-
-		if (AR_SREV_9160(sc)) {
-			/* Disable RIFS search to fix baseband hang. */
-			AR_CLRBITS(sc, AR_PHY_HEAVY_CLIP_FACTOR_RIFS,
-			    AR_PHY_RIFS_INIT_DELAY_M);
-		}
-	}
-
-	athn_set_phy(sc, c, extc);
-	athn_init_chains(sc);
-
-	if (sc->flags & ATHN_FLAG_OLPC)
-		sc->ops.olpc_init(sc);
-
-	ops->set_txpower(sc, c, extc);
-
-	if (!AR_SINGLE_CHIP(sc))
-		ar5416_rf_reset(sc, c);
-}
-
-void
 athn_init_qos(struct athn_softc *sc)
 {
 	/* Initialize QoS settings. */
@@ -4094,7 +1958,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 	    AR_CFG_LED_BLINK_SLOW);
 
 	/* Mark PHY as inactive. */
-	AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
+	ops->disable_phy(sc);
 
 	if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) {
 		/* Save TSF before it gets cleared. */
@@ -4118,11 +1982,11 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 
 	athn_init_pll(sc, c);
-	athn_set_rf_mode(sc, c);
+	ops->set_rf_mode(sc, c);
 
 	if (sc->flags & ATHN_FLAG_RFSILENT) {
 		/* Check that the radio is not disabled by hardware switch. */
-		reg = athn_gpio_read(sc, sc->rfsilent_pin);
+		reg = ops->gpio_read(sc, sc->rfsilent_pin);
 		if (sc->flags & ATHN_FLAG_RFSILENT_REVERSED)
 			reg = !reg;
 		if (!reg) {
@@ -4138,13 +2002,13 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 
 	if (AR_SREV_9280_10_OR_LATER(sc))
-		AR_SETBITS(sc, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
+		AR_SETBITS(sc, sc->gpio_input_en_off, AR_GPIO_JTAG_DISABLE);
 
-	if (AR_SREV_9287_12_OR_LATER(sc))
+	if (AR_SREV_9287_12_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
 		ar9287_1_2_enable_async_fifo(sc);
 
 	/* Write init values to hardware. */
-	athn_hw_init(sc, c, extc);
+	ops->hw_init(sc, c, extc);
 
 	/*
 	 * Only >=AR9280 2.0 parts are capable of encrypting unicast
@@ -4167,7 +2031,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 	}
 
 	if (ic->ic_curmode != IEEE80211_MODE_11B)
-		athn_set_delta_slope(sc, c, extc);
+		ops->set_delta_slope(sc, c, extc);
 
 	ops->spur_mitigate(sc, c, extc);
 	ops->init_from_rom(sc, c, extc);
@@ -4209,6 +2073,8 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 
 	/* Initialize interrupt mask. */
 	sc->imask = AR_IMR_DEFAULT;
+	if (AR_SREV_9380_10_OR_LATER(sc))
+		sc->imask |= AR_IMR_HP_RXOK;
 #ifndef IEEE80211_STA_ONLY
 	if (ic->ic_opmode == IEEE80211_M_HOSTAP)
 		sc->imask |= AR_IMR_MIB;
@@ -4221,6 +2087,12 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 		sc->isync |= AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin);
 	AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync);
 	AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
+	if (AR_SREV_9380_10_OR_LATER(sc)) {
+		AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
+		AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
+		AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0);
+		AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0);
+	}
 
 	athn_init_qos(sc);
 
@@ -4236,12 +2108,12 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 	athn_init_dma(sc);
 
 	/* Program OBS bus to see MAC interrupts. */
-	AR_WRITE(sc, AR_OBS, 8);
+	AR_WRITE(sc, sc->obs_off, 8);
 
 	/* Setup interrupt mitigation. */
 	AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
 
-	athn_init_baseband(sc);
+	ops->init_baseband(sc);
 
 	if ((error = athn_init_calib(sc, c, extc)) != 0) {
 		printf("%s: could not initialize calibration\n",
@@ -4249,11 +2121,7 @@ athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
 		return (error);
 	}
 
-	if (sc->rxchainmask == 0x3 || sc->rxchainmask == 0x5) {
-		/* XXX why again? */
-		AR_WRITE(sc, AR_PHY_RX_CHAINMASK,  sc->rxchainmask);
-		AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->rxchainmask);
-	}
+	ops->set_rxchains(sc);
 
 	AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ);
 
@@ -4354,19 +2222,20 @@ athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
 {
 	struct ifnet *ifp = &ic->ic_if;
 	struct athn_softc *sc = ifp->if_softc;
+	struct athn_ops *ops = &sc->ops;
 	int error;
 
 	timeout_del(&sc->calib_to);
 	if (nstate != IEEE80211_S_SCAN)
-		athn_gpio_write(sc, sc->led_pin, 1);
+		ops->gpio_write(sc, sc->led_pin, 1);
 
 	switch (nstate) {
 	case IEEE80211_S_INIT:
 		break;
 	case IEEE80211_S_SCAN:
 		/* Make the LED blink while scanning. */
-		athn_gpio_write(sc, sc->led_pin,
-		    !athn_gpio_read(sc, sc->led_pin));
+		ops->gpio_write(sc, sc->led_pin,
+		    !ops->gpio_read(sc, sc->led_pin));
 		error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL);
 		if (error != 0)
 			return (error);
@@ -4380,7 +2249,7 @@ athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
 	case IEEE80211_S_ASSOC:
 		break;
 	case IEEE80211_S_RUN:
-		athn_gpio_write(sc, sc->led_pin, 0);
+		ops->gpio_write(sc, sc->led_pin, 0);
 
 		if (ic->ic_opmode == IEEE80211_M_MONITOR)
 			break;
@@ -4488,7 +2357,7 @@ athn_start(struct ifnet *ifp)
 		if (ic->ic_rawbpf != NULL)
 			bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT);
 #endif
-		if (athn_tx(sc, m, ni) != 0) {
+		if (sc->ops.tx(sc, m, ni) != 0) {
 			ieee80211_release_node(ic, ni);
 			ifp->if_oerrors++;
 			continue;
@@ -4640,6 +2509,7 @@ int
 athn_init(struct ifnet *ifp)
 {
 	struct athn_softc *sc = ifp->if_softc;
+	struct athn_ops *ops = &sc->ops;
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ieee80211_channel *c, *extc;
 	int i, error;
@@ -4672,8 +2542,7 @@ athn_init(struct ifnet *ifp)
 	for (i = 0; i < sc->kc_entries; i++)
 		athn_reset_key(sc, i);
 
-	AR_SETBITS(sc, AR_PHY_CCK_DETECT,
-	    AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
+	ops->enable_antenna_diversity(sc);
 
 #ifdef ATHN_BT_COEXISTENCE
 	/* Configure bluetooth coexistence for combo chips. */
@@ -4686,7 +2555,7 @@ athn_init(struct ifnet *ifp)
 
 	/* Configure hardware radio switch. */
 	if (sc->flags & ATHN_FLAG_RFSILENT)
-		athn_rfsilent_init(sc);
+		ops->rfsilent_init(sc);
 
 	if ((error = athn_hw_reset(sc, c, extc)) != 0) {
 		printf("%s: unable to reset hardware; reset status %d\n",
diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h
index e5849863802..eea0f56dff6 100644
--- a/sys/dev/ic/athnreg.h
+++ b/sys/dev/ic/athnreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: athnreg.h,v 1.7 2010/04/07 16:19:33 damien Exp $	*/
+/*	$OpenBSD: athnreg.h,v 1.8 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -17,9 +17,13 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
+/*
+ * MAC registers.
+ */
 #define AR_CR				0x0008
 #define AR_RXDP				0x000c
 #define AR_CFG				0x0014
+#define AR_RXBP_THRESH			0x0018
 #define AR_MIRT				0x0020
 #define AR_IER				0x0024
 #define AR_TIMT				0x0028
@@ -33,9 +37,12 @@
 #define AR_RPGTO			0x0050
 #define AR_RPCNT			0x0054
 #define AR_MACMISC			0x0058
+#define AR_DATABUF_SIZE			0x0060
 #define AR_GTXTO			0x0064
 #define AR_GTTM				0x0068
 #define AR_CST				0x006c
+#define AR_HP_RXDP			0x0074
+#define AR_LP_RXDP			0x0078
 #define AR_ISR				0x0080
 #define AR_ISR_S0			0x0084
 #define AR_ISR_S1			0x0088
@@ -53,12 +60,10 @@
 #define AR_ISR_RAC			0x00c0
 #define AR_ISR_S0_S			0x00c4
 #define AR_ISR_S1_S			0x00c8
-#define AR_ISR_S2_S			0x00cc
-#define AR_ISR_S3_S			0x00d0
-#define AR_ISR_S4_S			0x00d4
-#define AR_ISR_S5_S			0x00d8
 #define AR_DMADBG(i)			(0x00e0 + (i) * 4)
 #define AR_QTXDP(i)			(0x0800 + (i) * 4)
+#define AR_Q_STATUS_RING_START		0x0830
+#define AR_Q_STATUS_RING_END		0x0834
 #define AR_Q_TXE			0x0840
 #define AR_Q_TXD			0x0880
 #define AR_QCBRCFG(i)			(0x08c0 + (i) * 4)
@@ -68,6 +73,7 @@
 #define AR_QMISC(i)			(0x09c0 + (i) * 4)
 #define AR_QSTS(i)			(0x0a00 + (i) * 4)
 #define AR_Q_RDYTIMESHDN		0x0a40
+#define AR_Q_DESC_CRCCHK		0x0a44
 #define AR_DQCUMASK(i)			(0x1000 + (i) * 4)
 #define AR_D_GBL_IFS_SIFS		0x1030
 #define AR_D_TXBLK_CMD			0x1038
@@ -101,19 +107,14 @@
 #define AR_INTR_ASYNC_ENABLE		0x403c
 #define AR_PCIE_SERDES			0x4040
 #define AR_PCIE_SERDES2			0x4044
-#define AR_GPIO_IN_OUT			0x4048
-#define AR_GPIO_OE_OUT			0x404c
-#define AR_GPIO_INTR_POL		0x4050
-#define AR_GPIO_INPUT_EN_VAL		0x4054
-#define AR_GPIO_INPUT_MUX1		0x4058
-#define AR_GPIO_INPUT_MUX2		0x405c
-#define AR_GPIO_OUTPUT_MUX(i)		(0x4060 + (i) * 4)
-#define AR_INPUT_STATE			0x406c
-#define AR_EEPROM_STATUS_DATA		0x407c
-#define AR_OBS				0x4080
-#define AR_GPIO_PDPU			0x4088
-#define AR_PCIE_MSI			0x4094
+#define AR_INTR_PRIO_SYNC_ENABLE	0x40c4
+#define AR_INTR_PRIO_ASYNC_MASK		0x40c8
+#define AR_INTR_PRIO_SYNC_MASK		0x40cc
+#define AR_INTR_PRIO_ASYNC_ENABLE	0x40d4
 #define AR_RTC_RC			0x7000
+#define AR_RTC_XTAL_CONTROL		0x7004
+#define AR_RTC_REG_CONTROL0		0x7008
+#define AR_RTC_REG_CONTROL1		0x700c
 #define AR_RTC_PLL_CONTROL		0x7014
 #define AR_RTC_RESET			0x7040
 #define AR_RTC_STATUS 			0x7044
@@ -122,14 +123,6 @@
 #define AR_RTC_INTR_CAUSE		0x7050
 #define AR_RTC_INTR_ENABLE		0x7054
 #define AR_RTC_INTR_MASK		0x7058
-#define AR_IS_ANALOG_REG(reg)		((reg) >= 0x7800 && (reg) <= 0x78b4)
-#define AR_AN_RF2G1_CH0			0x7810
-#define AR_AN_RF5G1_CH0			0x7818
-#define AR_AN_RF2G1_CH1			0x7834
-#define AR_AN_RF5G1_CH1			0x783c
-#define AR_AN_SYNTH9			0x7868
-#define AR_AN_TOP1			0x7890
-#define AR_AN_TOP2			0x7894
 #define AR_STA_ID0			0x8000
 #define AR_STA_ID1			0x8004
 #define AR_BSS_ID0			0x8008
@@ -185,6 +178,7 @@
 #define AR_PHY_ERR_2			0x8134
 #define AR_PHY_ERR_MASK_2		0x8138
 #define AR_TSFOOR_THRESHOLD		0x813c
+#define AR_PHY_ERR_EIFS_MASK		0x8144
 #define AR_PHY_ERR_3			0x8168
 #define AR_PHY_ERR_MASK_3		0x816c
 #define AR_BT_COEX_MODE			0x8170
@@ -199,22 +193,23 @@
 #define AR_TXOP_4_7			0x81f4
 #define AR_TXOP_8_11			0x81f8
 #define AR_TXOP_12_15			0x81fc
-#define AR_NEXT_TBTT_TIMER		0x8200
-#define AR_NEXT_DMA_BEACON_ALERT	0x8204
-#define AR_NEXT_CFP			0x8208
-#define AR_NEXT_HCF			0x820c
-#define AR_NEXT_TIM			0x8210
-#define AR_NEXT_DTIM			0x8214
-#define AR_NEXT_QUIET_TIMER		0x8218
-#define AR_NEXT_NDP_TIMER		0x821c
-#define AR_BEACON_PERIOD		0x8220
-#define AR_DMA_BEACON_PERIOD		0x8224
-#define AR_SWBA_PERIOD			0x8228
-#define AR_HCF_PERIOD			0x822c
-#define AR_TIM_PERIOD			0x8230
-#define AR_DTIM_PERIOD			0x8234
-#define AR_QUIET_PERIOD			0x8238
-#define AR_NDP_PERIOD			0x823c
+#define AR_GEN_TIMER(i)			(0x8200 + (i) * 4)
+#define AR_NEXT_TBTT_TIMER		AR_GEN_TIMER(0)
+#define AR_NEXT_DMA_BEACON_ALERT	AR_GEN_TIMER(1)
+#define AR_NEXT_CFP			AR_GEN_TIMER(2)
+#define AR_NEXT_HCF			AR_GEN_TIMER(3)
+#define AR_NEXT_TIM			AR_GEN_TIMER(4)
+#define AR_NEXT_DTIM			AR_GEN_TIMER(5)
+#define AR_NEXT_QUIET_TIMER		AR_GEN_TIMER(6)
+#define AR_NEXT_NDP_TIMER		AR_GEN_TIMER(7)
+#define AR_BEACON_PERIOD		AR_GEN_TIMER(8)
+#define AR_DMA_BEACON_PERIOD		AR_GEN_TIMER(9)
+#define AR_SWBA_PERIOD			AR_GEN_TIMER(10)
+#define AR_HCF_PERIOD			AR_GEN_TIMER(11)
+#define AR_TIM_PERIOD			AR_GEN_TIMER(12)
+#define AR_DTIM_PERIOD			AR_GEN_TIMER(13)
+#define AR_QUIET_PERIOD			AR_GEN_TIMER(14)
+#define AR_NDP_PERIOD			AR_GEN_TIMER(15)
 #define AR_TIMER_MODE			0x8240
 #define AR_SLP32_MODE			0x8244
 #define AR_SLP32_WAKE			0x8248
@@ -255,138 +250,6 @@
 #define AR_KEYTABLE_MAC0(i)		(AR_KEYTABLE(i) + 24)
 #define AR_KEYTABLE_MAC1(i)		(AR_KEYTABLE(i) + 28)
 
-/*
- * PHY registers.
- */
-#define AR_PHY_BASE			0x9800
-#define AR_PHY(i)			(AR_PHY_BASE + (i) * 4)
-#define AR_PHY_TEST			0x9800
-#define AR_PHY_TURBO			0x9804
-#define AR_PHY_TEST2			0x9808
-#define AR_PHY_TIMING2			0x9810
-#define AR_PHY_TIMING3			0x9814
-#define AR_PHY_CHIP_ID			0x9818
-#define AR_PHY_ACTIVE			0x981c
-#define AR_PHY_RF_CTL2			0x9824
-#define AR_PHY_RF_CTL3			0x9828
-#define AR_PHY_ADC_CTL			0x982c
-#define AR_PHY_ADC_SERIAL_CTL		0x9830
-#define AR_PHY_RF_CTL4			0x9834
-#define AR_PHY_TSTDAC_CONST		0x983c
-#define AR_PHY_SETTLING			0x9844
-#define AR_PHY_RXGAIN			0x9848
-#define AR_PHY_DESIRED_SZ		0x9850
-#define AR_PHY_FIND_SIG			0x9858
-#define AR_PHY_AGC_CTL1			0x985c
-#define AR_PHY_AGC_CONTROL		0x9860
-#define AR_PHY_CCA(i)			(0x9864 + (i) * 0x1000)
-#define AR_PHY_SFCORR			0x9868
-#define AR_PHY_SFCORR_LOW		0x986c
-#define AR_PHY_SLEEP_CTR_CONTROL	0x9870
-#define AR_PHY_SLEEP_CTR_LIMIT		0x9874
-#define AR_PHY_SLEEP_SCAL		0x9878
-#define AR_PHY_PLL_CTL			0x987c
-#define	AR_PHY_BIN_MASK_1		0x9900
-#define	AR_PHY_BIN_MASK_2		0x9904
-#define	AR_PHY_BIN_MASK_3		0x9908
-#define	AR_PHY_MASK_CTL			0x990c
-#define AR_PHY_RX_DELAY			0x9914
-#define AR_PHY_SEARCH_START_DELAY	0x9918
-#define AR_PHY_TIMING_CTRL4_0		0x9920
-#define AR_PHY_TIMING_CTRL4(i)		(0x9920 + (i) * 0x1000)
-#define AR_PHY_TIMING5			0x9924
-#define AR_PHY_POWER_TX_RATE1		0x9934
-#define AR_PHY_POWER_TX_RATE2		0x9938
-#define AR_PHY_POWER_TX_RATE_MAX	0x993c
-#define AR_PHY_RADAR_EXT		0x9940
-#define AR_PHY_FRAME_CTL		0x9944
-#define AR_PHY_SPUR_REG			0x994c
-#define AR_PHY_RADAR_0			0x9954
-#define AR_PHY_RADAR_1			0x9958
-#define AR_PHY_SWITCH_CHAIN_0		0x9960
-#define AR_PHY_SWITCH_COM		0x9964
-#define AR_PHY_SIGMA_DELTA		0x996c
-#define AR_PHY_RESTART			0x9970
-#define AR_PHY_RFBUS_REQ		0x997c
-#define	AR_PHY_TIMING7			0x9980
-#define	AR_PHY_TIMING8			0x9984
-#define	AR_PHY_BIN_MASK2_1		0x9988
-#define	AR_PHY_BIN_MASK2_2		0x998c
-#define	AR_PHY_BIN_MASK2_3		0x9990
-#define	AR_PHY_BIN_MASK2_4		0x9994
-#define	AR_PHY_TIMING9			0x9998
-#define	AR_PHY_TIMING10			0x999c
-#define	AR_PHY_TIMING11			0x99a0
-#define AR_PHY_RX_CHAINMASK		0x99a4
-#define AR_PHY_MULTICHAIN_GAIN_CTL	0x99ac
-#define AR_PHY_NEW_ADC_DC_GAIN_CORR(i)	(0x99b4 + (i) * 0x1000)
-#define AR_PHY_EXT_CCA0			0x99b8
-#define AR_PHY_EXT_CCA(i)		(0x99bc + (i) * 0x1000)
-#define AR_PHY_SFCORR_EXT		0x99c0
-#define AR_PHY_HALFGI			0x99d0
-#define AR_PHY_CHANNEL_MASK_01_30	0x99d4
-#define AR_PHY_CHANNEL_MASK_31_60	0x99d8
-#define AR_PHY_CHAN_INFO_MEMORY		0x99dc
-#define AR_PHY_HEAVY_CLIP_ENABLE	0x99e0
-#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS	0x99ec
-#define AR_PHY_CALMODE			0x99f0
-#define AR_PHY_REFCLKDLY		0x99f4
-#define AR_PHY_REFCLKPD			0x99f8
-#define AR_PHY_BB_RFGAIN(i)		(0x9a00 + (i) * 4)
-#define AR_PHY_CAL_MEAS_0(i)		(0x9c10 + (i) * 0x1000)
-#define AR_PHY_CAL_MEAS_1(i)		(0x9c14 + (i) * 0x1000)
-#define AR_PHY_CAL_MEAS_2(i)		(0x9c18 + (i) * 0x1000)
-#define AR_PHY_CAL_MEAS_3(i)		(0x9c1c + (i) * 0x1000)
-#define AR_PHY_CURRENT_RSSI		0x9c1c
-#define AR_PHY_RFBUS_GRANT		0x9c20
-#define AR9280_PHY_CURRENT_RSSI		0x9c3c
-#define AR_PHY_CHAN_INFO_GAIN_DIFF	0x9cf4
-#define AR_PHY_CHAN_INFO_GAIN		0x9cfc
-#define AR_PHY_MODE			0xa200
-#define AR_PHY_CCK_TX_CTRL		0xa204
-#define AR_PHY_CCK_DETECT		0xa208
-#define AR_PHY_GAIN_2GHZ		0xa20c
-#define AR_PHY_CCK_RXCTRL4		0xa21c
-#define AR_PHY_DAG_CTRLCCK		0xa228
-#define AR_PHY_FORCE_CLKEN_CCK		0xa22c
-#define AR_PHY_POWER_TX_RATE3		0xa234
-#define AR_PHY_POWER_TX_RATE4		0xa238
-#define AR_PHY_SCRM_SEQ_XR		0xa23c
-#define AR_PHY_HEADER_DETECT_XR		0xa240
-#define AR_PHY_CHIRP_DETECTED_XR	0xa244
-#define AR_PHY_BLUETOOTH		0xa254
-#define AR_PHY_TPCRG1			0xa258
-#define AR_PHY_TX_PWRCTRL4		0xa264
-#define AR_PHY_ANALOG_SWAP		0xa268
-#define AR_PHY_TPCRG5			0xa26c
-#define AR_PHY_TX_PWRCTRL6_0		0xa270
-#define AR_PHY_TX_PWRCTRL7		0xa274
-#define AR_PHY_TX_PWRCTRL9		0xa27c
-#define AR_PHY_PDADC_TBL_BASE		0xa280
-#define AR_PHY_TX_GAIN_TBL(i)		(0xa300 + (i) * 4)
-#define AR_PHY_CL_CAL_CTL		0xa358
-#define AR_PHY_CLC_TBL(i)		(0xa35c + (i) * 4)
-#define AR_PHY_POWER_TX_RATE5		0xa38c
-#define AR_PHY_POWER_TX_RATE6		0xa390
-#define AR_PHY_CH0_TX_PWRCTRL11		0xa398
-#define AR_PHY_CAL_CHAINMASK		0xa39c
-#define AR_PHY_VIT_MASK2_M_46_61	0xa3a0
-#define AR_PHY_VIT_MASK2_M_31_45	0xa3a4
-#define AR_PHY_VIT_MASK2_M_16_30	0xa3a8
-#define AR_PHY_VIT_MASK2_M_00_15	0xa3ac
-#define AR_PHY_PILOT_MASK_01_30		0xa3b0
-#define AR_PHY_PILOT_MASK_31_60		0xa3b4
-#define AR_PHY_VIT_MASK2_P_15_01	0xa3b8
-#define AR_PHY_VIT_MASK2_P_30_16	0xa3bc
-#define AR_PHY_VIT_MASK2_P_45_31	0xa3c0
-#define AR_PHY_VIT_MASK2_P_61_46	0xa3c4
-#define AR_PHY_POWER_TX_SUB		0xa3c8
-#define AR_PHY_POWER_TX_RATE7		0xa3cc
-#define AR_PHY_POWER_TX_RATE8		0xa3d0
-#define AR_PHY_POWER_TX_RATE9		0xa3d4
-#define AR_PHY_XPA_CFG			0xa3d8
-#define AR_PHY_TX_PWRCTRL6_1		0xb270
-#define AR_PHY_CH1_TX_PWRCTRL11		0xb398
 
 /* Bits for AR_CR. */
 #define AR_CR_RXE	0x00000004
@@ -406,6 +269,12 @@
 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M	0x00060000
 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S	17
 
+/* Bits for AR_RXBP_THRESH. */
+#define AR_RXBP_THRESH_HP_M	0x0000000f
+#define AR_RXBP_THRESH_HP_S	0
+#define AR_RXBP_THRESH_LP_M	0x00003f00
+#define AR_RXBP_THRESH_LP_S	8
+
 /* Bits for AR_IER. */
 #define AR_IER_ENABLE	0x00000001
 
@@ -503,7 +372,9 @@
 
 /* Bits for AR_ISR. */
 #define AR_ISR_RXOK	0x00000001
+#define AR_ISR_HP_RXOK	0x00000001
 #define AR_ISR_RXDESC	0x00000002
+#define AR_ISR_LP_RXOK	0x00000002
 #define AR_ISR_RXERR	0x00000004
 #define AR_ISR_RXNOPKT	0x00000008
 #define AR_ISR_RXEOL	0x00000010
@@ -584,7 +455,9 @@
 
 /* Bits for AR_IMR. */
 #define AR_IMR_RXOK	0x00000001
+#define AR_IMR_HP_RXOK	0x00000001
 #define AR_IMR_RXDESC	0x00000002
+#define AR_IMR_LP_RXOK	0x00000002
 #define AR_IMR_RXERR	0x00000004
 #define AR_IMR_RXNOPKT	0x00000008
 #define AR_IMR_RXEOL	0x00000010
@@ -673,12 +546,12 @@
 #define AR_Q_CBRCFG_OVF_THRESH_M	0xff000000
 #define AR_Q_CBRCFG_OVF_THRESH_S	24
 
-/* Bits for AR_Q_RDYTIMECFG_*. */
+/* Bits for AR_QRDYTIMECFG_*. */
 #define AR_Q_RDYTIMECFG_DURATION_M	0x00ffffff
 #define AR_Q_RDYTIMECFG_DURATION_S	0
 #define AR_Q_RDYTIMECFG_EN		0x01000000
 
-/* Bits for AR_Q_MISC_*. */
+/* Bits for AR_QMISC_*. */
 #define AR_Q_MISC_FSP_M			0x0000000f
 #define AR_Q_MISC_FSP_S			0
 #define AR_Q_MISC_FSP_ASAP		0
@@ -696,12 +569,15 @@
 #define AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400
 #define AR_Q_MISC_DCU_EARLY_TERM_REQ	0x00000800
 
-/* Bits for AR_Q_STS_*. */
+/* Bits for AR_QSTS_*. */
 #define AR_Q_STS_PEND_FR_CNT_M	0x00000003
 #define AR_Q_STS_PEND_FR_CNT_S	0
 #define AR_Q_STS_CBR_EXP_CNT_M	0x0000ff00
 #define AR_Q_STS_CBR_EXP_CNT_S	8
 
+/* Bits for AR_Q_DESC_CRCCHK. */
+#define AR_Q_DESC_CRCCHK_EN	0x00000001
+
 #define AR_NUM_DCU	10
 #define AR_DCU(x)	(1 << (x))
 
@@ -903,6 +779,9 @@
 #define AR_SREV_REVISION_9287_10	0
 #define AR_SREV_REVISION_9287_11	1
 #define AR_SREV_REVISION_9287_12	2
+#define AR_SREV_VERSION_9380		0x1c0
+#define AR_SREV_REVISION_9380_10	0
+#define AR_SREV_REVISION_9380_20	2
 
 /* Bits for AR_AHB_MODE. */
 #define AR_AHB_EXACT_WR_EN			0x00000000
@@ -1021,6 +900,9 @@
 #define AR_RTC_RC_COLD_RESET	0x00000004
 #define AR_RTC_RC_WARM_RESET	0x00000008
 
+/* Bits for AR_RTC_REG_CONTROL1. */
+#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM	0x00000001
+
 /* Bits for AR_RTC_PLL_CONTROL. */
 #define AR_RTC_PLL_DIV_M		0x0000001f
 #define AR_RTC_PLL_DIV_S		0
@@ -1048,52 +930,12 @@
 
 /* Bits for AR_RTC_SLEEP_CLK. */
 #define AR_RTC_FORCE_DERIVED_CLK	0x00000002
+#define AR_RTC_FORCE_SWREG_PRD		0x00000004
 
 /* Bits for AR_RTC_FORCE_WAKE. */
 #define AR_RTC_FORCE_WAKE_EN		0x00000001
 #define AR_RTC_FORCE_WAKE_ON_INT	0x00000002
 
-/*
- * Analog registers.
- */
-/* Bits for AR_AN_RF2G1_CH0. */
-#define AR_AN_RF2G1_CH0_OB_M	0x03800000
-#define AR_AN_RF2G1_CH0_OB_S	23
-#define AR_AN_RF2G1_CH0_DB_M	0x1c000000
-#define AR_AN_RF2G1_CH0_DB_S	26
-
-/* Bits for AR_AN_RF5G1_CH0. */
-#define AR_AN_RF5G1_CH0_OB5_M	0x00070000
-#define AR_AN_RF5G1_CH0_OB5_S	16
-#define AR_AN_RF5G1_CH0_DB5_M	0x00380000
-#define AR_AN_RF5G1_CH0_DB5_S	19
-
-/* Bits for AR_AN_RF2G1_CH1. */
-#define AR_AN_RF2G1_CH1_OB_M	0x03800000
-#define AR_AN_RF2G1_CH1_OB_S	23
-#define AR_AN_RF2G1_CH1_DB_M	0x1c000000
-#define AR_AN_RF2G1_CH1_DB_S	26
-
-/* Bits for AR_AN_RF5G1_CH1. */
-#define AR_AN_RF5G1_CH1_OB5_M	0x00070000
-#define AR_AN_RF5G1_CH1_OB5_S	16
-#define AR_AN_RF5G1_CH1_DB5_M	0x00380000
-#define AR_AN_RF5G1_CH1_DB5_S	19
-
-/* Bits for AR_AN_SYNTH9. */
-#define AR_AN_SYNTH9_REFDIVA_M	0xf8000000
-#define AR_AN_SYNTH9_REFDIVA_S	27
-
-/* Bits for AR_AN_TOP1. */
-#define AR_AN_TOP1_DACLPMODE	0x00040000
-
-/* Bits for AR_AN_TOP2. */
-#define AR_AN_TOP2_XPABIAS_LVL_M	0xc0000000
-#define AR_AN_TOP2_XPABIAS_LVL_S	30
-#define AR_AN_TOP2_LOCALBIAS		0x00200000
-#define AR_AN_TOP2_PWDCLKIND		0x00400000
-
-
 /* Bits for AR_STA_ID1. */
 #define AR_STA_ID1_SADH_M		0x0000ffff
 #define AR_STA_ID1_SADH_S		0
@@ -1343,6 +1185,7 @@
 /* Bits for AR_PCU_MISC_MODE2. */
 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE		0x00000002
 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT	0x00000004
+#define AR_PCU_MISC_MODE2_AGG_WEP_ENABLE_FIX		0x00000008
 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE	0x00000040
 #define AR_PCU_MISC_MODE2_CFP_IGNORE			0x00000080
 #define AR_PCU_MISC_MODE2_MGMT_QOS_M			0x0000ff00
@@ -1423,438 +1266,6 @@
 #define AR_KEYTABLE_VALID	0x00008000
 
 
-
-/* Bits for AR_PHY_TEST. */
-#define AR_PHY_TEST_RFSILENT_BB	0x00002000
-#define AR_PHY_TEST_AGC_CLR	0x10000000
-
-/* Bits for AR_PHY_TURBO. */
-#define AR_PHY_FC_TURBO_MODE		0x00000001
-#define AR_PHY_FC_TURBO_SHORT		0x00000002
-#define AR_PHY_FC_DYN2040_EN		0x00000004
-#define AR_PHY_FC_DYN2040_PRI_ONLY	0x00000008
-#define AR_PHY_FC_DYN2040_PRI_CH	0x00000010
-#define AR_PHY_FC_DYN2040_EXT_CH	0x00000020
-#define AR_PHY_FC_HT_EN			0x00000040
-#define AR_PHY_FC_SHORT_GI_40		0x00000080
-#define AR_PHY_FC_WALSH			0x00000100
-#define AR_PHY_FC_SINGLE_HT_LTF1	0x00000200
-#define AR_PHY_FC_ENABLE_DAC_FIFO	0x00000800
-
-/* Bits for AR_PHY_TIMING3. */
-#define AR_PHY_TIMING3_DSC_MAN_M	0xfffe0000
-#define AR_PHY_TIMING3_DSC_MAN_S	17
-#define AR_PHY_TIMING3_DSC_EXP_M	0x0001e000
-#define AR_PHY_TIMING3_DSC_EXP_S	13
-
-/* Bits for AR_PHY_CHIP_ID. */
-#define AR_PHY_CHIP_ID_REV_0		0x80
-#define AR_PHY_CHIP_ID_REV_1		0x81
-#define AR_PHY_CHIP_ID_9160_REV_0	0xb0
-
-/* Bits for AR_PHY_ACTIVE. */
-#define AR_PHY_ACTIVE_EN	0x00000001
-#define AR_PHY_ACTIVE_DIS	0x00000000
-
-/* Bits for AR_PHY_RF_CTL2. */
-#define AR_PHY_TX_END_DATA_START_M	0x000000ff
-#define AR_PHY_TX_END_DATA_START_S	0
-#define AR_PHY_TX_END_PA_ON_M		0x0000ff00
-#define AR_PHY_TX_END_PA_ON_S		8
-
-/* Bits for AR_PHY_RF_CTL3. */
-#define AR_PHY_TX_END_TO_A2_RX_ON_M	0x00ff0000
-#define AR_PHY_TX_END_TO_A2_RX_ON_S	16
-
-/* Bits for AR_PHY_ADC_CTL. */
-#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_M	0x00000003
-#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S	0
-#define AR_PHY_ADC_CTL_OFF_PWDDAC	0x00002000
-#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP	0x00004000
-#define AR_PHY_ADC_CTL_OFF_PWDADC	0x00008000
-#define AR_PHY_ADC_CTL_ON_INBUFGAIN_M	0x00030000
-#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S	16
-
-/* Bits for AR_PHY_ADC_SERIAL_CTL. */
-#define AR_PHY_SEL_INTERNAL_ADDAC	0x00000000
-#define AR_PHY_SEL_EXTERNAL_RADIO	0x00000001
-
-/* Bits for AR_PHY_RF_CTL4. */
-#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_M	0xff000000
-#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S	24
-#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_M	0x00ff0000
-#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S	16
-#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_M		0x0000ff00
-#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S		8
-#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_M		0x000000ff
-#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S		0
-
-/* Bits for AR_PHY_SETTLING. */
-#define AR_PHY_SETTLING_SWITCH_M	0x00003f80
-#define AR_PHY_SETTLING_SWITCH_S	7
-
-/* Bits for AR_PHY_RXGAIN. */
-#define AR_PHY_RXGAIN_TXRX_ATTEN_M	0x0003f000
-#define AR_PHY_RXGAIN_TXRX_ATTEN_S	12
-#define AR_PHY_RXGAIN_TXRX_RF_MAX_M	0x007c0000
-#define AR_PHY_RXGAIN_TXRX_RF_MAX_S	18
-#define AR9280_PHY_RXGAIN_TXRX_ATTEN_M	0x00003f80
-#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S	7
-#define AR9280_PHY_RXGAIN_TXRX_MARGIN_M	0x001fc000
-#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S	14
-
-/* Bits for AR_PHY_DESIRED_SZ. */
-#define AR_PHY_DESIRED_SZ_ADC_M		0x000000ff
-#define AR_PHY_DESIRED_SZ_ADC_S		0
-#define AR_PHY_DESIRED_SZ_PGA_M		0x0000ff00
-#define AR_PHY_DESIRED_SZ_PGA_S		8
-#define AR_PHY_DESIRED_SZ_TOT_DES_M	0x0ff00000
-#define AR_PHY_DESIRED_SZ_TOT_DES_S	20
-
-/* Bits for AR_PHY_FIND_SIG. */
-#define AR_PHY_FIND_SIG_FIRSTEP_M	0x0003f000
-#define AR_PHY_FIND_SIG_FIRSTEP_S	12
-#define AR_PHY_FIND_SIG_FIRPWR_M	0x03fc0000
-#define AR_PHY_FIND_SIG_FIRPWR_S	18
-
-/* Bits for AR_PHY_AGC_CTL1. */
-#define AR_PHY_AGC_CTL1_COARSE_LOW_M	0x00007f80
-#define AR_PHY_AGC_CTL1_COARSE_LOW_S	7
-#define AR_PHY_AGC_CTL1_COARSE_HIGH_M	0x003f8000
-#define AR_PHY_AGC_CTL1_COARSE_HIGH_S	15
-
-/* Bits for AR_PHY_AGC_CONTROL. */
-#define AR_PHY_AGC_CONTROL_CAL		0x00000001
-#define AR_PHY_AGC_CONTROL_NF		0x00000002
-#define AR_PHY_AGC_CONTROL_ENABLE_NF	0x00008000
-#define AR_PHY_AGC_CONTROL_FLTR_CAL	0x00010000
-#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF	0x00020000
-
-/* Bits for AR_PHY_CCA. */
-#define AR_PHY_MAXCCA_PWR_M		0x000001ff
-#define AR_PHY_MAXCCA_PWR_S		0
-#define AR_PHY_MINCCA_PWR_M		0x0ff80000
-#define AR_PHY_MINCCA_PWR_S		19
-#define AR_PHY_CCA_THRESH62_M		0x0007f000
-#define AR_PHY_CCA_THRESH62_S		12
-#define AR9280_PHY_MINCCA_PWR_M		0x1ff00000
-#define AR9280_PHY_MINCCA_PWR_S		20
-#define AR9280_PHY_CCA_THRESH62_M	0x000ff000
-#define AR9280_PHY_CCA_THRESH62_S	12
-
-/* Bits for AR_PHY_SFCORR_LOW. */
-#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW	0x00000001
-#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_M	0x00003f00
-#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S	8
-#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_M	0x001fc000
-#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S	14
-#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_M	0x0fe00000
-#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S	21
-
-/* Bits for AR_PHY_SFCORR. */
-#define AR_PHY_SFCORR_M2COUNT_THR_M	0x0000001f
-#define AR_PHY_SFCORR_M2COUNT_THR_S	0
-#define AR_PHY_SFCORR_M1_THRESH_M	0x00fe0000
-#define AR_PHY_SFCORR_M1_THRESH_S	17
-#define AR_PHY_SFCORR_M2_THRESH_M	0x7f000000
-#define AR_PHY_SFCORR_M2_THRESH_S	24
-
-/* Bits for AR_PHY_PLL_CTL. */
-#define AR_PHY_PLL_CTL_40	0xaa
-#define AR_PHY_PLL_CTL_40_5413	0x04
-#define AR_PHY_PLL_CTL_44	0xab
-#define AR_PHY_PLL_CTL_44_2133	0xeb
-#define AR_PHY_PLL_CTL_40_2133	0xea
-
-/* Bits for AR_PHY_RX_DELAY. */
-#define AR_PHY_RX_DELAY_DELAY_M	0x00003fff
-#define AR_PHY_RX_DELAY_DELAY_S	0
-
-/* Bits for AR_PHY_TIMING_CTRL4_0. */
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M		0x0000001f
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S		0
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M		0x000007e0
-#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S		5
-#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE		0x00000800
-#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M	0x0000f000
-#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S	12
-#define AR_PHY_TIMING_CTRL4_DO_CAL			0x00010000
-#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI		0x80000000
-#define	AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER		0x40000000
-#define	AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK		0x20000000
-#define	AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK		0x10000000
-
-/* Bits for AR_PHY_TIMING5. */
-#define AR_PHY_TIMING5_CYCPWR_THR1_M	0x000000fe
-#define AR_PHY_TIMING5_CYCPWR_THR1_S	1
-
-/* Bits for AR_PHY_POWER_TX_RATE_MAX. */
-#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE	0x00000040
-
-/* Bits for AR_PHY_FRAME_CTL. */
-#define AR_PHY_FRAME_CTL_TX_CLIP_M	0x00000038
-#define AR_PHY_FRAME_CTL_TX_CLIP_S	3
-
-/* Bits for AR_PHY_TXPWRADJ. */
-#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_M	0x00000fc0
-#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S	6
-#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_M	0x00fc0000
-#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S	18
-
-/* Bits for AR_PHY_RADAR_EXT. */
-#define AR_PHY_RADAR_EXT_ENA		0x00004000
-
-/* Bits for AR_PHY_RADAR_0. */
-#define AR_PHY_RADAR_0_ENA		0x00000001
-#define AR_PHY_RADAR_0_FFT_ENA		0x80000000
-#define AR_PHY_RADAR_0_INBAND_M		0x0000003e
-#define AR_PHY_RADAR_0_INBAND_S		1
-#define AR_PHY_RADAR_0_PRSSI_M		0x00000fc0
-#define AR_PHY_RADAR_0_PRSSI_S		6
-#define AR_PHY_RADAR_0_HEIGHT_M		0x0003f000
-#define AR_PHY_RADAR_0_HEIGHT_S		12
-#define AR_PHY_RADAR_0_RRSSI_M		0x00fc0000
-#define AR_PHY_RADAR_0_RRSSI_S		18
-#define AR_PHY_RADAR_0_FIRPWR_M		0x7f000000
-#define AR_PHY_RADAR_0_FIRPWR_S		24
-
-/* Bits for AR_PHY_RADAR_1. */
-#define AR_PHY_RADAR_1_RELPWR_ENA	0x00800000
-#define AR_PHY_RADAR_1_USE_FIR128	0x00400000
-#define AR_PHY_RADAR_1_RELPWR_THRESH_M	0x003f0000
-#define AR_PHY_RADAR_1_RELPWR_THRESH_S	16
-#define AR_PHY_RADAR_1_BLOCK_CHECK	0x00008000
-#define AR_PHY_RADAR_1_MAX_RRSSI	0x00004000
-#define AR_PHY_RADAR_1_RELSTEP_CHECK	0x00002000
-#define AR_PHY_RADAR_1_RELSTEP_THRESH_M	0x00001f00
-#define AR_PHY_RADAR_1_RELSTEP_THRESH_S	8
-#define AR_PHY_RADAR_1_MAXLEN_M		0x000000ff
-#define AR_PHY_RADAR_1_MAXLEN_S		0
-
-/* Bits for AR_PHY_SIGMA_DELTA. */
-#define AR_PHY_SIGMA_DELTA_ADC_SEL_M	0x00000003
-#define AR_PHY_SIGMA_DELTA_ADC_SEL_S	0
-#define AR_PHY_SIGMA_DELTA_FILT2_M	0x000000f8
-#define AR_PHY_SIGMA_DELTA_FILT2_S	3
-#define AR_PHY_SIGMA_DELTA_FILT1_M	0x00001f00
-#define AR_PHY_SIGMA_DELTA_FILT1_S	8
-#define AR_PHY_SIGMA_DELTA_ADC_CLIP_M	0x01ffe000
-#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S	13
-
-/* Bits for AR_PHY_RESTART. */
-#define AR_PHY_RESTART_DIV_GC_M	0x001c0000
-#define AR_PHY_RESTART_DIV_GC_S	18
-
-/* Bits for AR_PHY_RFBUS_REQ. */
-#define AR_PHY_RFBUS_REQ_EN	0x00000001
-
-/* Bits for AR_PHY_TIMING11. */
-#define	AR_PHY_TIMING11_SPUR_DELTA_PHASE_M	0x000fffff
-#define	AR_PHY_TIMING11_SPUR_DELTA_PHASE_S	0
-#define	AR_PHY_TIMING11_SPUR_FREQ_SD_M		0x3ff00000
-#define	AR_PHY_TIMING11_SPUR_FREQ_SD_S		20
-#define AR_PHY_TIMING11_USE_SPUR_IN_AGC		0x40000000
-#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR	0x80000000
-
-/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR(). */
-#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE		0x40000000
-#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE	0x80000000
-
-/* Bits for AR_PHY_EXT_CCA0. */
-#define AR_PHY_EXT_CCA0_THRESH62_M	0x000000ff
-#define AR_PHY_EXT_CCA0_THRESH62_S	0
-
-/* Bits for AR_PHY_EXT_CCA. */
-#define AR_PHY_EXT_MAXCCA_PWR_M		0x000001ff
-#define AR_PHY_EXT_MAXCCA_PWR_S		0
-#define AR_PHY_EXT_CCA_CYCPWR_THR1_M	0x0000fe00
-#define AR_PHY_EXT_CCA_CYCPWR_THR1_S	9
-#define AR_PHY_EXT_CCA_THRESH62_M	0x007f0000
-#define AR_PHY_EXT_CCA_THRESH62_S	16
-#define AR_PHY_EXT_MINCCA_PWR_M		0xff800000
-#define AR_PHY_EXT_MINCCA_PWR_S		23
-#define AR9280_PHY_EXT_MINCCA_PWR_M	0x01ff0000
-#define AR9280_PHY_EXT_MINCCA_PWR_S	16
-
-/* Bits for AR_PHY_SFCORR_EXT. */
-#define AR_PHY_SFCORR_EXT_M1_THRESH_M		0x0000007f
-#define AR_PHY_SFCORR_EXT_M1_THRESH_S		0
-#define AR_PHY_SFCORR_EXT_M2_THRESH_M		0x00003f80
-#define AR_PHY_SFCORR_EXT_M2_THRESH_S		7
-#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_M	0x001fc000
-#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S	14
-#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_M	0x0fe00000
-#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S	21
-#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_M		0xf0000000
-#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S		28
-
-/* Bits for AR_PHY_HALFGI. */
-#define AR_PHY_HALFGI_DSC_EXP_M	0x0000000f
-#define AR_PHY_HALFGI_DSC_EXP_S	0
-#define AR_PHY_HALFGI_DSC_MAN_M	0x0007fff0
-#define AR_PHY_HALFGI_DSC_MAN_S	4
-
-/* Bits for AR_PHY_CHAN_INFO_MEMORY. */
-#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK	0x0001
-
-/* Bits for AR_PHY_HEAVY_CLIP_FACTOR_RIFS. */
-#define AR_PHY_RIFS_INIT_DELAY_M	0x03ff0000
-#define AR_PHY_RIFS_INIT_DELAY_S	16
-
-/* Bits for AR_PHY_CALMODE. */
-#define AR_PHY_CALMODE_IQ		0x00000000
-#define AR_PHY_CALMODE_ADC_GAIN		0x00000001
-#define AR_PHY_CALMODE_ADC_DC_PER	0x00000002
-#define AR_PHY_CALMODE_ADC_DC_INIT	0x00000003
-
-/* Bits for AR_PHY_RFBUS_GRANT. */
-#define AR_PHY_RFBUS_GRANT_EN	0x00000001
-
-/* Bits for AR_PHY_CHAN_INFO_GAIN_DIFF. */
-#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT	320
-
-/* Bits for AR_PHY_MODE. */
-#define AR_PHY_MODE_ASYNCFIFO		0x00000080
-#define AR_PHY_MODE_AR2133		0x00000008
-#define AR_PHY_MODE_AR5111		0x00000000
-#define AR_PHY_MODE_AR5112		0x00000008
-#define AR_PHY_MODE_DYNAMIC		0x00000004
-#define AR_PHY_MODE_RF2GHZ		0x00000002
-#define AR_PHY_MODE_RF5GHZ		0x00000000
-#define AR_PHY_MODE_CCK			0x00000001
-#define AR_PHY_MODE_OFDM		0x00000000
-#define AR_PHY_MODE_DYN_CCK_DISABLE	0x00000100
-
-/* Bits for AR_PHY_CCK_TX_CTRL. */
-#define AR_PHY_CCK_TX_CTRL_JAPAN		0x00000010
-#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_M	0x0000000c
-#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S	2
-
-/* Bits for AR_PHY_CCK_DETECT. */
-#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_M		0x0000003f
-#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S		0
-#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_M		0x00001fc0
-#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S		6
-#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x00002000
-
-/* Bits for AR_PHY_GAIN_2GHZ. */
-#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_M		0x00fc0000
-#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S		18
-#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_M		0x00003c00
-#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S		10
-#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_M		0x0000001f
-#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S		0
-#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_M	0x003e0000
-#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S	17
-#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_M	0x0001f000
-#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S	12
-#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_M		0x00000fc0
-#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S		6
-#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_M		0x0000003f
-#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S		0
-
-/* Bit for AR_PHY_CCK_RXCTRL4. */
-#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_M	0x01f80000
-#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S	19
-
-/* Bits for AR_PHY_DAG_CTRLCCK. */
-#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR	0x00000200
-#define AR_PHY_DAG_CTRLCCK_RSSI_THR_M	0x0001fc00
-#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S	10
-
-/* Bits for AR_PHY_FORCE_CLKEN_CCK. */
-#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX	0x00000040
-
-/* Bits for AR_PHY_TPCRG1. */
-#define AR_PHY_TPCRG1_NUM_PD_GAIN_M	0x0000c000
-#define AR_PHY_TPCRG1_NUM_PD_GAIN_S	14
-#define AR_PHY_TPCRG1_PD_GAIN_1_M	0x00030000
-#define AR_PHY_TPCRG1_PD_GAIN_1_S	16
-#define AR_PHY_TPCRG1_PD_GAIN_2_M	0x000c0000
-#define AR_PHY_TPCRG1_PD_GAIN_2_S	18
-#define AR_PHY_TPCRG1_PD_GAIN_3_M	0x00300000
-#define AR_PHY_TPCRG1_PD_GAIN_3_S	20
-#define AR_PHY_TPCRG1_PD_CAL_ENABLE	0x00400000
-
-/* Bits for AR_PHY_TX_PWRCTRL4. */
-#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID	0x00000001
-#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_M	0x000001fe
-#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S	1
-
-/* Bits for AR_PHY_TX_PWRCTRL6_[01]. */
-#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_M	0x03000000
-#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S	24
-
-/* Bits for AR_PHY_TX_PWRCTRL7. */
-#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_M	0x0007e000
-#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S	13
-#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_M	0x01f80000
-#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S	19
-
-/* Bits for AR_PHY_TX_PWRCTRL9. */
-#define AR_PHY_TX_DESIRED_SCALE_CCK_M		0x00007c00
-#define AR_PHY_TX_DESIRED_SCALE_CCK_S		10	/* XXX should be 9? */
-#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL	0x80000000
-
-/* Bits for AR_PHY_TX_GAIN_TBL. */
-#define AR_PHY_TX_GAIN_CLC_M	0x0000001e
-#define AR_PHY_TX_GAIN_CLC_S	1
-#define AR_PHY_TX_GAIN_M	0x0007f000
-#define AR_PHY_TX_GAIN_S	12
-
-/* Bits for AR_PHY_SPUR_REG. */
-#define AR_PHY_SPUR_REG_MASK_RATE_CNTL		0x03fc0000
-#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM		0x00020000
-#define AR_PHY_SPUR_REG_MASK_RATE_SELECT	0x0001fe00
-#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI	0x00000100
-#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_M	0x0000007f
-#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S	0
-#define AR_SPUR_RSSI_THRESH			40
-
-/* Bits for AR_PHY_ANALOG_SWAP. */
-#define AR_PHY_SWAP_ALT_CHAIN	0x00000040
-
-/* Bits for AR_PHY_TPCRG5. */
-#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_M		0x0000000f
-#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S		0
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_M	0x000003f0
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S	4
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_M	0x0000fc00
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S	10
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_M	0x003f0000
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S	16
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_M	0x0fc00000
-#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S	22
-
-/* Bits for AR_PHY_CL_CAL_CTL. */
-#define AR_PHY_PARALLEL_CAL_ENABLE	0x00000001
-#define AR_PHY_CL_CAL_ENABLE		0x00000002
-
-/* Bits for AR_PHY_CLC_TBL. */
-#define AR_PHY_CLC_Q0_M		0x0000ffd0
-#define AR_PHY_CLC_Q0_S		5
-#define AR_PHY_CLC_I0_M		0x07ff0000
-#define AR_PHY_CLC_I0_S		16
-
-/* Bits for AR_PHY_XPA_CFG. */
-#define AR_PHY_FORCE_XPA_CFG	0x000000001
-
-/* Bits for AR_PHY_CH[01]_TX_PWRCTRL11. */
-#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_M	0x0000fc00
-#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S	10
-#define AR_PHY_TX_PWRCTRL_OLPC_PWR_M		0x00ff0000
-#define AR_PHY_TX_PWRCTRL_OLPC_PWR_S		16
-
-/* Bits for AR_PHY_NEW_ADC_DC_GAIN_CORR. */
-#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_M	0x0000003f
-#define AR_PHY_NEW_ADC_DC_GAIN_QGAIN_S	0
-#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_M	0x00000fc0
-#define AR_PHY_NEW_ADC_DC_GAIN_IGAIN_S	6
-#define AR_PHY_NEW_ADC_DC_GAIN_QDC_M	0x001ff000
-#define AR_PHY_NEW_ADC_DC_GAIN_QDC_S	12
-#define AR_PHY_NEW_ADC_DC_GAIN_IDC_M	0x3fe00000
-#define AR_PHY_NEW_ADC_DC_GAIN_IDC_S	21
-
 #define AR_BASE_PHY_ACTIVE_DELAY	100
 
 #define AR_CLOCK_RATE_CCK	22
@@ -1877,261 +1288,6 @@
 #define AR_CAL_SAMPLES	64	/* XXX AR9280? */
 #define AR_MAX_LOG_CAL	2	/* XXX AR9280? */
 
-/*
- * Tx DMA descriptor.
- */
-struct ar_tx_desc {
-	uint32_t	ds_link;
-	uint32_t	ds_data;
-	uint32_t	ds_ctl0;
-	uint32_t	ds_ctl1;
-	uint32_t	ds_ctl2;
-	uint32_t	ds_ctl3;
-	uint32_t	ds_ctl4;
-	uint32_t	ds_ctl5;
-	uint32_t	ds_ctl6;
-	uint32_t	ds_ctl7;
-	uint32_t	ds_ctl8;
-	uint32_t	ds_ctl9;
-	uint32_t	ds_ctl10;
-	uint32_t	ds_ctl11;
-	uint32_t	ds_status0;
-	uint32_t	ds_status1;
-	uint32_t	ds_tstamp;
-	uint32_t	ds_ba_bitmap_lo;
-	uint32_t	ds_ba_bitmap_hi;
-	uint32_t	ds_evm0;
-	uint32_t	ds_evm1;
-	uint32_t	ds_evm2;
-	uint32_t	ds_status8;
-	uint32_t	ds_status9;
-	/*
-	 * Padding to make Tx descriptors 128 bytes such that they will
-	 * not cross a 4KB boundary.
-	 */
-	uint32_t	pad[8];
-} __packed;
-
-/* Bits for ds_ctl0. */
-#define AR_TXC0_FRAME_LEN_M		0x00000fff
-#define AR_TXC0_FRAME_LEN_S		0
-#define AR_TXC0_VIRT_MORE_FRAG		0x00001000
-#define AR_TXC0_XMIT_POWER_M		0x003f0000
-#define AR_TXC0_XMIT_POWER_S		16
-#define AR_TXC0_RTS_ENABLE		0x00400000
-#define AR_TXC0_VEOL			0x00800000
-#define AR_TXC0_CLR_DEST_MASK		0x01000000
-#define AR_TXC0_INTR_REQ		0x20000000
-#define AR_TXC0_DEST_IDX_VALID		0x40000000
-#define AR_TXC0_CTS_ENABLE		0x80000000
-
-/* Bits for ds_ctl1. */
-#define AR_TXC1_BUF_LEN_M		0x00000fff
-#define AR_TXC1_BUF_LEN_S		0
-#define AR_TXC1_MORE			0x00001000
-#define AR_TXC1_DEST_IDX_M		0x000fe000
-#define AR_TXC1_DEST_IDX_S		13
-#define AR_TXC1_FRAME_TYPE_M		0x00f00000
-#define AR_TXC1_FRAME_TYPE_S		20
-#define AR_FRAME_TYPE_NORMAL		0
-#define AR_FRAME_TYPE_ATIM		1
-#define AR_FRAME_TYPE_PSPOLL		2
-#define AR_FRAME_TYPE_BEACON		3
-#define AR_FRAME_TYPE_PROBE_RESP	4
-#define AR_TXC1_NO_ACK			0x01000000
-#define AR_TXC1_INSERT_TS		0x02000000
-#define AR_TXC1_EXT_ONLY		0x08000000
-#define AR_TXC1_EXT_AND_CTL		0x10000000
-#define AR_TXC1_MORE_AGGR		0x20000000
-#define AR_TXC1_IS_AGGR			0x40000000
-
-/* Bits for ds_ctl2. */
-#define AR_TXC2_BURST_DUR_M		0x00007fff
-#define AR_TXC2_BURST_DUR_S		0
-#define AR_TXC2_DUR_UPDATE_ENA		0x00008000
-#define AR_TXC2_XMIT_DATA_TRIES0_M	0x000f0000
-#define AR_TXC2_XMIT_DATA_TRIES0_S	16
-#define AR_TXC2_XMIT_DATA_TRIES1_M	0x00f00000
-#define AR_TXC2_XMIT_DATA_TRIES1_S	20
-#define AR_TXC2_XMIT_DATA_TRIES2_M	0x0f000000
-#define AR_TXC2_XMIT_DATA_TRIES2_S	24
-#define AR_TXC2_XMIT_DATA_TRIES3_M	0xf0000000
-#define AR_TXC2_XMIT_DATA_TRIES3_S	28
-
-/* Bits for ds_ctl3. */
-#define AR_TXC3_XMIT_RATE0_M		0x000000ff
-#define AR_TXC3_XMIT_RATE0_S		0
-#define AR_TXC3_XMIT_RATE1_M		0x0000ff00
-#define AR_TXC3_XMIT_RATE1_S		8
-#define AR_TXC3_XMIT_RATE2_M		0x00ff0000
-#define AR_TXC3_XMIT_RATE2_S		16
-#define AR_TXC3_XMIT_RATE3_M		0xff000000
-#define AR_TXC3_XMIT_RATE3_S		24
-
-/* Bits for ds_ctl4. */
-#define AR_TXC4_PACKET_DUR0_M		0x00007fff
-#define AR_TXC4_PACKET_DUR0_S		0
-#define AR_TXC4_RTSCTS_QUAL0		0x00008000
-#define AR_TXC4_PACKET_DUR1_M		0x7fff0000
-#define AR_TXC4_PACKET_DUR1_S		16
-#define AR_TXC4_RTSCTS_QUAL1		0x80000000
-/* Shortcut. */
-#define AR_TXC4_RTSCTS_QUAL01	\
-	(AR_TXC4_RTSCTS_QUAL0 | AR_TXC4_RTSCTS_QUAL1)
-
-/* Bits for ds_ctl5. */
-#define AR_TXC5_PACKET_DUR2_M		0x00007fff
-#define AR_TXC5_PACKET_DUR2_S		0
-#define AR_TXC5_RTSCTS_QUAL2		0x00008000
-#define AR_TXC5_PACKET_DUR3_M		0x7fff0000
-#define AR_TXC5_PACKET_DUR3_S		16
-#define AR_TXC5_RTSCTS_QUAL3		0x80000000
-/* Shortcut. */
-#define AR_TXC5_RTSCTS_QUAL23	\
-	(AR_TXC5_RTSCTS_QUAL2 | AR_TXC5_RTSCTS_QUAL3)
-
-/* Bits for ds_ctl6. */
-#define AR_TXC6_AGGR_LEN_M		0x0000ffff
-#define AR_TXC6_AGGR_LEN_S		0
-#define AR_TXC6_PAD_DELIM_M		0x03fc0000
-#define AR_TXC6_PAD_DELIM_S		18
-#define AR_TXC6_ENCR_TYPE_M		0x0c000000
-#define AR_TXC6_ENCR_TYPE_S		26
-#define AR_ENCR_TYPE_CLEAR		0
-#define AR_ENCR_TYPE_WEP		1
-#define AR_ENCR_TYPE_AES		2
-#define AR_ENCR_TYPE_TKIP		3
-
-/* Bits for ds_ctl7. */
-#define AR_TXC7_2040_0			0x00000001
-#define AR_TXC7_GI0			0x00000002
-#define AR_TXC7_CHAIN_SEL0_M		0x0000001c
-#define AR_TXC7_CHAIN_SEL0_S		2
-#define AR_TXC7_2040_1			0x00000020
-#define AR_TXC7_GI1			0x00000040
-#define AR_TXC7_CHAIN_SEL1_M		0x00000380
-#define AR_TXC7_CHAIN_SEL1_S		7
-#define AR_TXC7_2040_2			0x00000400
-#define AR_TXC7_GI2			0x00000800
-#define AR_TXC7_CHAIN_SEL2_M		0x00007000
-#define AR_TXC7_CHAIN_SEL2_S		12
-#define AR_TXC7_2040_3			0x00008000
-#define AR_TXC7_GI3			0x00010000
-#define AR_TXC7_CHAIN_SEL3_M		0x000e0000
-#define AR_TXC7_CHAIN_SEL3_S		17
-#define AR_TXC7_RTSCTS_RATE_M		0x0ff00000
-#define AR_TXC7_RTSCTS_RATE_S		20
-/* Shortcuts. */
-#define AR_TXC7_2040_0123	\
-	(AR_TXC7_2040_0 | AR_TXC7_2040_1 | AR_TXC7_2040_2 | AR_TXC7_2040_3)
-#define AR_TXC7_GI0123		\
-	(AR_TXC7_GI0 | AR_TXC7_GI1 | AR_TXC7_GI2 | AR_TXC7_GI3)
-
-/* Bits for ds_status0. */
-#define AR_TXS0_RSSI_ANT0(i)		(((x) >> ((i) * 8)) & 0xff)
-#define AR_TXS0_BA_STATUS		0x40000000
-
-/* Bits for ds_status1. */
-#define AR_TXS1_FRM_XMIT_OK		0x00000001
-#define AR_TXS1_EXCESSIVE_RETRIES	0x00000002
-#define AR_TXS1_FIFO_UNDERRUN		0x00000004
-#define AR_TXS1_FILTERED		0x00000008
-#define AR_TXS1_RTS_FAIL_CNT_M		0x000000f0
-#define AR_TXS1_RTS_FAIL_CNT_S		4
-#define AR_TXS1_DATA_FAIL_CNT_M		0x00000f00
-#define AR_TXS1_DATA_FAIL_CNT_S		8
-#define AR_TXS1_VIRT_RETRY_CNT_M	0x0000f000
-#define AR_TXS1_VIRT_RETRY_CNT_S	12
-#define AR_TXS1_TX_DELIM_UNDERRUN	0x00010000
-#define AR_TXS1_TX_DATA_UNDERRUN	0x00020000
-#define AR_TXS1_DESC_CFG_ERR		0x00040000
-#define AR_TXS1_TX_TIMER_EXPIRED	0x00080000
-/* Shortcuts. */
-#define AR_TXS1_UNDERRUN		\
-	(AR_TXS1_FIFO_UNDERRUN |	\
-	 AR_TXS1_TX_DELIM_UNDERRUN |	\
-	 AR_TXS1_TX_DATA_UNDERRUN)
-
-/* Bits for ds_status9. */
-#define AR_TXS9_DONE			0x00000001
-#define AR_TXS9_SEQNUM_M		0x00001ffe
-#define AR_TXS9_SEQNUM_S		1
-#define AR_TXS9_TXOP_EXCEEDED		0x00020000
-#define AR_TXS9_FINAL_IDX_M		0x00600000
-#define AR_TXS9_FINAL_IDX_S		21
-#define AR_TXS9_POWER_MGMT		0x02000000
-
-/*
- * Rx DMA descriptor.
- */
-struct ar_rx_desc {
-	uint32_t	ds_link;
-	uint32_t	ds_data;
-	uint32_t	ds_ctl0;
-	uint32_t	ds_ctl1;
-	uint32_t	ds_status0;
-	uint32_t	ds_status1;
-	uint32_t	ds_status2;
-	uint32_t	ds_status3;
-	uint32_t	ds_status4;
-	uint32_t	ds_status5;
-	uint32_t	ds_status6;
-	uint32_t	ds_status7;
-	uint32_t	ds_status8;
-	/*
-	 * Padding to make Rx descriptors 64 bytes such that they will
-	 * not cross a 4KB boundary.
-	 */
-	uint32_t	pad[3];
-} __packed;
-
-/* Bits for ds_ctl1. */
-#define AR_RXC1_BUF_LEN_M		0x00000fff
-#define AR_RXC1_BUF_LEN_S		0
-#define AR_RXC1_INTR_REQ		0x00002000
-
-/* Bits for ds_ctl2. */
-#define AR_RXS0_RSSI_ANT00(x)		(((x) >>  0) & 0xff)
-#define AR_RXS0_RSSI_ANT01(x)		(((x) >>  8) & 0xff)
-#define AR_RXS0_RSSI_ANT02(x)		(((x) >> 16) & 0xff)
-#define AR_RXS0_RATE_M			0xff000000
-#define AR_RXS0_RATE_S			24
-
-/* Bits for ds_status1. */
-#define AR_RXS1_DATA_LEN_M		0x00000fff
-#define AR_RXS1_DATA_LEN_S		0
-#define AR_RXS1_MORE			0x00001000
-
-/* Bits for ds_status3. */
-#define AR_RXS3_GI			0x00000001
-#define AR_RXS3_2040			0x00000002
-#define AR_RXS3_PARALLEL_40		0x00000004
-#define AR_RXS3_ANTENNA_M		0xffffff00
-#define AR_RXS3_ANTENNA_S		8
-#define AR_RXS3_RATE_M			0x000003fc
-#define AR_RXS3_RATE_S			2
-
-/* Bits for ds_status4. */
-#define AR_RXS4_RSSI_COMBINED_M		0xff000000
-#define AR_RXS4_RSSI_COMBINED_S		24
-
-/* Bits for ds_status8. */
-#define AR_RXS8_DONE			0x00000001
-#define AR_RXS8_FRAME_OK		0x00000002
-#define AR_RXS8_CRC_ERR			0x00000004
-#define AR_RXS8_DECRYPT_CRC_ERR		0x00000008
-#define AR_RXS8_PHY_ERR			0x00000010
-#define AR_RXS8_MICHAEL_ERR		0x00000020
-#define AR_RXS8_PRE_DELIM_CRC_ERR	0x00000040
-#define AR_RXS8_PHY_ERR_CODE_M		0x0000ff00
-#define AR_RXS8_PHY_ERR_CODE_S		8
-#define AR_RXS8_KEY_IDX_VALID		0x00000100
-#define AR_RXS8_KEY_IDX_M		0x0000fe00
-#define AR_RXS8_KEY_IDX_S		9
-#define AR_RXS8_POST_DELIM_CRC_ERR	0x00040000
-#define AR_RXS8_DECRYPT_BUSY_ERR	0x40000000
-
-
 /* Maximum number of chains supported by any chipset. */
 #define AR_MAX_CHAINS	3
 
@@ -2143,7 +1299,6 @@ struct ar_rx_desc {
 #define AR_GPIO_BTACTIVE_PIN	6
 #define AR_GPIO_BTPRIORITY_PIN	7
 
-/* XXX need to cleanup that mess. */
 #define AR_SREV_5416(sc) \
 	((sc)->mac_ver == AR_SREV_VERSION_5416_PCI || \
 	 (sc)->mac_ver == AR_SREV_VERSION_5416_PCIE)
@@ -2215,6 +1370,14 @@ struct ar_rx_desc {
 	((sc)->mac_ver > AR_SREV_VERSION_9287 || \
 	 (AR_SREV_9287(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9287_12))
 
+#define AR_SREV_9380(sc) \
+	((sc)->mac_ver == AR_SREV_VERSION_9380)
+#define AR_SREV_9380_10_OR_LATER(sc) \
+	((sc)->mac_ver >= AR_SREV_VERSION_9380)
+#define AR_SREV_9380_20_OR_LATER(sc) \
+	((sc)->mac_ver > AR_SREV_VERSION_9380 || \
+	 (AR_SREV_9380(sc) && (sc)->mac_rev >= AR_SREV_REVISION_9380_20))
+
 #define AR_SINGLE_CHIP(sc)	AR_SREV_9280_10_OR_LATER(sc)
 
 #define AR_RADIO_SREV_MAJOR	0xf0
@@ -2223,131 +1386,16 @@ struct ar_rx_desc {
 #define AR_RAD5122_SREV_MAJOR	0xe0
 #define AR_RAD2122_SREV_MAJOR	0xf0
 
-/*
- * Common ROM structures.
- */
-#define AR_EEPROM_MAGIC_OFFSET	0x0000
-#if BYTE_ORDER == BIG_ENDIAN
-#define AR_EEPROM_MAGIC		0x5aa5
-#else
-#define AR_EEPROM_MAGIC		0xa55a
-#endif
-
 #define AR_BCHAN_UNUSED		0xff
-#define AR_NO_SPUR		0x8000
-
-#define AR_NUM_PDADC_VALUES	128
 #define AR_PD_GAINS_IN_MASK	4	/* NB: Max for all chips. */
-
-#define AR_MAX_PWR_RANGE_IN_HALF_DB	64
-
 #define AR_MAX_RATE_POWER	63
 
 #define AR_HT40_POWER_INC_FOR_PDADC	2
-
-#define AR_EEPROM_MODAL_SPURS	5
-
-#define AR_BASE_FREQ_2GHZ	2300
-#define AR_BASE_FREQ_5GHZ	4900
-
 #define AR_PWR_TABLE_OFFSET_DB		(-5)
-
-/* XXX does not belong here!!! */
-#define AR9285_PD_GAIN_BOUNDARY_DEFAULT	58
 #define AR9280_TX_GAIN_TABLE_SIZE	22
 
-#define AR_EEP_TXGAIN_ORIGINAL		0
-#define AR_EEP_TXGAIN_HIGH_POWER	1
-
-/*
- * ROM header that is common to all existing ROM layouts.
- */
-struct ar_base_eep_header {
-	uint16_t	length;
-	uint16_t	checksum;
-	uint16_t	version;
-#define AR_EEP_VER			0xe
-#define AR_EEP_VER_MINOR_MASK		0x0fff
-#define AR_EEP_MINOR_VER_2		2
-#define AR_EEP_MINOR_VER_3		3
-#define AR_EEP_MINOR_VER_7		7
-#define AR_EEP_MINOR_VER_9		9
-#define AR_EEP_MINOR_VER_10		10
-#define AR_EEP_MINOR_VER_16		16
-#define AR_EEP_MINOR_VER_17		17
-#define AR_EEP_MINOR_VER_19		19
-#define AR_EEP_MINOR_VER_20		20
-#define AR_EEP_MINOR_VER_21		21
-#define AR_EEP_MINOR_VER_22		22
-
-	uint8_t		opCapFlags;
-#define AR_OPFLAGS_11A			0x01
-#define AR_OPFLAGS_11G			0x02
-#define AR_OPFLAGS_11N_5G40		0x04
-#define AR_OPFLAGS_11N_2G40		0x08
-#define AR_OPFLAGS_11N_5G20		0x10
-#define AR_OPFLAGS_11N_2G20		0x20
-/* Shortcut. */
-#define AR_OPFLAGS_11N			0x3c
-
-	uint8_t		eepMisc;
-	uint16_t	regDmn[2];
-	uint8_t		macAddr[6];
-	uint8_t		rxMask;
-	uint8_t		txMask;
-	uint16_t	rfSilent;
-#define AR_EEP_RFSILENT_ENABLED		0x0001
-#define AR_EEP_RFSILENT_GPIO_SEL_M	0x001c
-#define AR_EEP_RFSILENT_GPIO_SEL_S	2
-#define AR_EEP_RFSILENT_POLARITY	0x0002
-
-	uint16_t	blueToothOptions;
-	uint16_t	deviceCap;
-#define AR_EEP_DEVCAP_COMPRESS_DIS	0x0001
-#define AR_EEP_DEVCAP_AES_DIS		0x0002
-#define AR_EEP_DEVCAP_FASTFRAME_DIS	0x0004
-#define AR_EEP_DEVCAP_BURST_DIS		0x0008
-#define AR_EEP_DEVCAP_MAXQCU_M		0x01f0
-#define AR_EEP_DEVCAP_MAXQCU_S		4
-#define AR_EEP_DEVCAP_HEAVY_CLIP_EN	0x0200
-#define AR_EEP_DEVCAP_KC_ENTRIES_M	0xf000
-#define AR_EEP_DEVCAP_KC_ENTRIES_S	12
-
-	uint32_t	binBuildNumber;
-	uint8_t		deviceType;
-} __packed;
-
-struct ar_spur_chan {
-	uint16_t	spurChan;
-	uint8_t		spurRangeLow;
-	uint8_t		spurRangeHigh;
-} __packed;
-
-struct ar_cal_data_per_freq_olpc {
-	uint8_t	pwrPdg[2][5];
-	uint8_t	vpdPdg[2][5];
-	uint8_t	pcdac[2][5];
-	uint8_t	empty[2][5];
-} __packed;
-
-struct ar_cal_target_power_leg {
-	uint8_t	bChannel;
-	uint8_t	tPow2x[4];
-} __packed;
-
-struct ar_cal_target_power_ht {
-	uint8_t	bChannel;
-	uint8_t	tPow2x[8];
-} __packed;
-
-struct ar_cal_ctl_edges {
-	uint8_t	bChannel;
-	uint8_t	tPowerFlag;
-#define AR_CAL_CTL_EDGES_POWER_M	0x3f
-#define AR_CAL_CTL_EDGES_POWER_S	0
-#define AR_CAL_CTL_EDGES_FLAG_M		0xc0
-#define AR_CAL_CTL_EDGES_FLAG_S		6
-} __packed;
+#define AR_BASE_FREQ_2GHZ	2300
+#define AR_BASE_FREQ_5GHZ	4900
 
 #define AR_SD_NO_CTL	0xe0
 #define AR_NO_CTL	0xff
diff --git a/sys/dev/ic/athnvar.h b/sys/dev/ic/athnvar.h
index cbdcbda30c2..6cbd6a255ec 100644
--- a/sys/dev/ic/athnvar.h
+++ b/sys/dev/ic/athnvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: athnvar.h,v 1.9 2010/05/05 19:28:15 damien Exp $	*/
+/*	$OpenBSD: athnvar.h,v 1.10 2010/05/10 17:44:21 damien Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -31,9 +31,8 @@ extern int athn_debug;
 #define ATHN_RXBUFSZ	3872
 #define ATHN_TXBUFSZ	4096
 
-#define ATHN_NRXBUFS		64
-#define ATHN_NTXBUFS		64	/* Shared between all Tx queues. */
-#define ATHN_MAX_SCATTER	16
+#define ATHN_NRXBUFS	64
+#define ATHN_NTXBUFS	64	/* Shared between all Tx queues. */
 
 struct athn_rx_radiotap_header {
 	struct ieee80211_radiotap_header wr_ihdr;
@@ -72,7 +71,7 @@ struct athn_tx_radiotap_header {
 struct athn_tx_buf {
 	SIMPLEQ_ENTRY(athn_tx_buf)	bf_list;
 
-	struct ar_tx_desc		*bf_descs;
+	void				*bf_descs;
 	bus_dmamap_t			bf_map;
 	bus_addr_t			bf_daddr;
 
@@ -82,13 +81,13 @@ struct athn_tx_buf {
 
 struct athn_txq {
 	SIMPLEQ_HEAD(, athn_tx_buf)	head;
-	struct ar_tx_desc		*lastds;
+	void				*lastds;
 };
 
 struct athn_rx_buf {
 	SIMPLEQ_ENTRY(athn_rx_buf)	bf_list;
 
-	struct ar_rx_desc		*bf_desc;
+	void				*bf_desc;
 	bus_dmamap_t			bf_map;
 
 	struct mbuf			*bf_m;
@@ -96,12 +95,13 @@ struct athn_rx_buf {
 };
 
 struct athn_rxq {
-	struct athn_rx_buf		bf[ATHN_NRXBUFS];
+	struct athn_rx_buf		*bf;
 
-	struct ar_rx_desc		*descs;
-	struct ar_rx_desc		*lastds;
+	void				*descs;
+	void				*lastds;
 	bus_dmamap_t			map;
 	bus_dma_segment_t		seg;
+	int				count;
 
 	SIMPLEQ_HEAD(, athn_rx_buf)	head;
 };
@@ -191,6 +191,10 @@ struct athn_addac {
 	const uint32_t	*vals;
 };
 
+/* Rx queue software indexes. */
+#define ATHN_QID_LP		0
+#define ATHN_QID_HP		0
+
 /* Tx queue software indexes. */
 #define ATHN_QID_AC_BE		0
 #define ATHN_QID_PSPOLL		1
@@ -260,12 +264,12 @@ static const uint16_t ar_mcs_ndbps[][2] = {
 #define ATHN_POWER_CCK11_SP	14
 #define ATHN_POWER_XR		15
 #define ATHN_POWER_HT20(mcs)	(16 + (mcs))
-#define ATHN_POWER_HT40(mcs)	(24 + (mcs))
-#define ATHN_POWER_CCK_DUP	32
-#define ATHN_POWER_OFDM_DUP	33
-#define ATHN_POWER_CCK_EXT	34
-#define ATHN_POWER_OFDM_EXT	35
-#define ATHN_POWER_COUNT	36
+#define ATHN_POWER_HT40(mcs)	(40 + (mcs))
+#define ATHN_POWER_CCK_DUP	64
+#define ATHN_POWER_OFDM_DUP	65
+#define ATHN_POWER_CCK_EXT	66
+#define ATHN_POWER_OFDM_EXT	67
+#define ATHN_POWER_COUNT	68
 
 struct athn_node {
 	struct ieee80211_node		ni;
@@ -274,6 +278,9 @@ struct athn_node {
 	uint8_t				fallback[IEEE80211_RATE_MAXSIZE];
 };
 
+/*
+ * Adaptive noise immunity state.
+ */
 #define ATHN_ANI_PERIOD		100
 #define ATHN_ANI_RSSI_THR_HIGH	40
 #define ATHN_ANI_RSSI_THR_LOW	7
@@ -296,7 +303,7 @@ struct athn_ani {
 	uint32_t	cck_phy_err_base;
 	uint32_t	ofdm_phy_err_count;
 	uint32_t	cck_phy_err_count;
-	
+
 	uint32_t	cyccnt;
 	uint32_t	txfcnt;
 	uint32_t	rxfcnt;
@@ -332,13 +339,52 @@ struct athn_ops {
 		    struct ieee80211_channel *);
 	void	(*spur_mitigate)(struct athn_softc *,
 		    struct ieee80211_channel *, struct ieee80211_channel *);
-	const struct ar_spur_chan *(*get_spur_chans)(struct athn_softc *, int);
+	const struct ar_spur_chan *
+		(*get_spur_chans)(struct athn_softc *, int);
 	void	(*init_from_rom)(struct athn_softc *,
 		    struct ieee80211_channel *, struct ieee80211_channel *);
 	int	(*set_synth)(struct athn_softc *, struct ieee80211_channel *,
 		    struct ieee80211_channel *);
 	void	(*swap_rom)(struct athn_softc *);
 	void	(*olpc_init)(struct athn_softc *);
+	/* GPIO callbacks. */
+	int	(*gpio_read)(struct athn_softc *, int);
+	void	(*gpio_write)(struct athn_softc *, int, int);
+	void	(*gpio_config_input)(struct athn_softc *, int);
+	void	(*gpio_config_output)(struct athn_softc *, int, int);
+	void	(*rfsilent_init)(struct athn_softc *);
+	/* DMA callbacks. */
+	int	(*dma_alloc)(struct athn_softc *);
+	void	(*dma_free)(struct athn_softc *);
+	void	(*rx_enable)(struct athn_softc *);
+	int	(*intr)(struct athn_softc *);
+	int	(*tx)(struct athn_softc *, struct mbuf *,
+		    struct ieee80211_node *);
+	/* PHY callbacks. */
+	void	(*set_rf_mode)(struct athn_softc *,
+		    struct ieee80211_channel *);
+	int	(*rf_bus_request)(struct athn_softc *);
+	void	(*rf_bus_release)(struct athn_softc *);
+	void	(*set_phy)(struct athn_softc *, struct ieee80211_channel *,
+		    struct ieee80211_channel *);
+	void	(*set_delta_slope)(struct athn_softc *,
+		    struct ieee80211_channel *, struct ieee80211_channel *);
+	void	(*enable_antenna_diversity)(struct athn_softc *);
+	void	(*init_baseband)(struct athn_softc *);
+	void	(*disable_phy)(struct athn_softc *);
+	void	(*set_rxchains)(struct athn_softc *);
+	void	(*noisefloor_calib)(struct athn_softc *);
+	void	(*do_calib)(struct athn_softc *);
+	void	(*next_calib)(struct athn_softc *);
+	void	(*hw_init)(struct athn_softc *, struct ieee80211_channel *,
+		    struct ieee80211_channel *);
+	/* ANI callbacks. */
+	void	(*set_noise_immunity_level)(struct athn_softc *, int);
+	void	(*enable_ofdm_weak_signal)(struct athn_softc *);
+	void	(*disable_ofdm_weak_signal)(struct athn_softc *);
+	void	(*set_cck_weak_signal)(struct athn_softc *, int);
+	void	(*set_firstep_level)(struct athn_softc *, int);
+	void	(*set_spur_immunity_level)(struct athn_softc *, int);
 };
 
 struct athn_softc {
@@ -365,12 +411,16 @@ struct athn_softc {
 #define ATHN_FLAG_PCIE			(1 << 0)
 #define ATHN_FLAG_OLPC			(1 << 1)
 #define ATHN_FLAG_SPLIT_MMIC		(1 << 2)
-#define ATHN_FLAG_RFSILENT		(1 << 3)
-#define ATHN_FLAG_RFSILENT_REVERSED	(1 << 4)
-#define ATHN_FLAG_BTCOEX2WIRE		(1 << 5)
-#define ATHN_FLAG_BTCOEX3WIRE		(1 << 6)
+#define ATHN_FLAG_FAST_PLL_CLOCK	(1 << 3)
+#define ATHN_FLAG_RFSILENT		(1 << 4)
+#define ATHN_FLAG_RFSILENT_REVERSED	(1 << 5)
+#define ATHN_FLAG_BTCOEX2WIRE		(1 << 6)
+#define ATHN_FLAG_BTCOEX3WIRE		(1 << 7)
 /* Shortcut. */
 #define ATHN_FLAG_BTCOEX	(ATHN_FLAG_BTCOEX2WIRE | ATHN_FLAG_BTCOEX3WIRE)
+#define ATHN_FLAG_11A			(1 << 8)
+#define ATHN_FLAG_11G			(1 << 9)
+#define ATHN_FLAG_11N			(1 << 10)
 
 	uint8_t				ngpiopins;
 	int				led_pin;
@@ -382,7 +432,6 @@ struct athn_softc {
 	uint8_t				mac_rev;
 	uint8_t				rf_rev;
 	uint16_t			eep_rev;
-	uint32_t			phy_rev;
 
 	uint8_t				txchainmask;
 	uint8_t				rxchainmask;
@@ -393,6 +442,7 @@ struct athn_softc {
 #define ATHN_CAL_IQ		(1 << 0)
 #define ATHN_CAL_ADC_GAIN	(1 << 1)
 #define ATHN_CAL_ADC_DC		(1 << 2)
+#define ATHN_CAL_TEMP		(1 << 3)
 
 	struct ieee80211_channel	*curchan;
 	struct ieee80211_channel	*curchanext;
@@ -407,18 +457,24 @@ struct athn_softc {
 	int				kc_entries;
 
 	void				*eep;
+	const void			*eep_def;
 	uint32_t			eep_base;
 	uint32_t			eep_size;
 
-	struct athn_rxq			rxq;
-	struct athn_txq			txq[31];	/* 0x1f ??? */
+	struct athn_rxq			rxq[2];
+	struct athn_txq			txq[31];
 
-	struct ar_tx_desc		*descs;
+	void				*descs;
 	bus_dmamap_t			map;
 	bus_dma_segment_t		seg;
 	SIMPLEQ_HEAD(, athn_tx_buf)	txbufs;
 	struct athn_tx_buf		txpool[ATHN_NTXBUFS];
 
+	bus_dmamap_t			txsmap;
+	bus_dma_segment_t		txsseg;
+	void				*txsring;
+	int				txscur;
+
 	int				sc_if_flags;
 	int				sc_tx_timer;
 
@@ -428,11 +484,17 @@ struct athn_softc {
 	const struct athn_addac		*addac;
 	const uint32_t			*serdes;
 	uint32_t			workaround;
+	uint32_t			obs_off;
+	uint32_t			gpio_input_en_off;
 
 	struct athn_ops			ops;
 
 	int				fixed_ridx;
 
+	int16_t				cca_min_2g;
+	int16_t				cca_max_2g;
+	int16_t				cca_min_5g;
+	int16_t				cca_max_5g;
 	int16_t				def_nf;
 	struct {
 		int16_t	nf[AR_MAX_CHAINS];
@@ -467,52 +529,3 @@ struct athn_softc {
 extern int	athn_attach(struct athn_softc *);
 extern void	athn_detach(struct athn_softc *);
 extern int	athn_intr(void *);
-extern int	ar5416_attach(struct athn_softc *);
-extern int	ar9280_attach(struct athn_softc *);
-extern int	ar9285_attach(struct athn_softc *);
-extern int	ar9287_attach(struct athn_softc *);
-extern uint8_t	athn_reverse_bits(uint8_t, int);
-extern uint8_t	athn_chan2fbin(struct ieee80211_channel *);
-extern void	athn_set_viterbi_mask(struct athn_softc *, int);
-extern void	athn_write_txpower(struct athn_softc *, int16_t[]);
-extern void	athn_get_lg_tpow(struct athn_softc *,
-		    struct ieee80211_channel *, uint8_t,
-		    const struct ar_cal_target_power_leg *, int, uint8_t[]);
-extern void	athn_get_ht_tpow(struct athn_softc *,
-		    struct ieee80211_channel *, uint8_t,
-		    const struct ar_cal_target_power_ht *, int, uint8_t[]);
-extern void	athn_get_pdadcs(struct athn_softc *, uint8_t,
-		    struct athn_pier *, struct athn_pier *, int, int, uint8_t,
-		    uint8_t *, uint8_t *);
-extern void	athn_get_pier_ival(uint8_t, const uint8_t *, int, int *,
-		    int *);
-/* XXX not here. */
-extern void	ar5416_set_txpower(struct athn_softc *,
-		    struct ieee80211_channel *, struct ieee80211_channel *);
-extern void	ar5416_swap_rom(struct athn_softc *);
-extern void	ar9280_2_0_olpc_get_pdadcs(struct athn_softc *,
-		    struct ieee80211_channel *, int, uint8_t[], uint8_t[],
-		    uint8_t *);
-extern int	ar9280_set_synth(struct athn_softc *,
-		    struct ieee80211_channel *, struct ieee80211_channel *);
-extern void	ar9280_spur_mitigate(struct athn_softc *,
-		    struct ieee80211_channel *, struct ieee80211_channel *);
-extern void	ar9287_1_2_enable_async_fifo(struct athn_softc *);
-extern void	ar9287_1_2_setup_async_fifo(struct athn_softc *);
-extern const	struct ar_spur_chan *ar5416_get_spur_chans(struct athn_softc *,
-		    int);
-extern int	ar5416_init_calib(struct athn_softc *,
-		    struct ieee80211_channel *, struct ieee80211_channel *);
-extern int	ar9285_1_2_init_calib(struct athn_softc *,
-		    struct ieee80211_channel *, struct ieee80211_channel *);
-extern void	ar9285_pa_calib(struct athn_softc *);
-extern void	ar9280_reset_rx_gain(struct athn_softc *,
-		    struct ieee80211_channel *);
-extern void	ar9280_reset_tx_gain(struct athn_softc *,
-		    struct ieee80211_channel *);
-extern void	ar5416_reset_addac(struct athn_softc *,
-		    struct ieee80211_channel *);
-extern void	ar5416_reset_bb_gain(struct athn_softc *,
-		    struct ieee80211_channel *);
-extern void	ar5416_rf_reset(struct athn_softc *,
-		    struct ieee80211_channel *);