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authorJonathan Gray <jsg@cvs.openbsd.org>2021-09-27 04:14:10 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2021-09-27 04:14:10 +0000
commita00dac61b7ea1abeb9fd565eaeba169d031be3c0 (patch)
tree958818fdac77ad8238ddf1b1c58e752dae608a34 /sys/dev
parent6f6c43118250b9828b7c72d81932df82bcc83f63 (diff)
drm/amd/display: Update number of DCN3 clock states
From Aurabindo Pillai 583c4f3d09c3e980a683b59febbb0c775bdff1db in linux 5.10.y/5.10.67 0bbf06d888734041e813b916d7821acd4f72005a in mainline linux
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
index e5f4f93317c..fcb2e1f02a5 100644
--- a/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -2522,6 +2522,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
+ dcn3_0_soc.num_states = num_states;
for (i = 0; i < dcn3_0_soc.num_states; i++) {
dcn3_0_soc.clock_limits[i].state = i;
dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];