Change I915_GPU_WRITE into a bitfield and adjust related code to be similar

to what Linux does.

4 files changed, 8 insertions, 11 deletions

diff --git a/sys/dev/pci/drm/i915_drv.c b/sys/dev/pci/drm/i915_drv.c
index a64e27d0d6d..fe0fa97556b 100644
--- a/sys/dev/pci/drm/i915_drv.c
+++ b/sys/dev/pci/drm/i915_drv.c
@@ -2054,8 +2054,6 @@ inteldrm_hung(void *arg, void *reset_type)
 		drm_lock_obj(&obj_priv->base);
 		if (obj_priv->base.write_domain & I915_GEM_GPU_DOMAINS) {
 			list_del_init(&obj_priv->gpu_write_list);
-			atomic_clearbits_int(&obj_priv->base.do_flags,
-			    I915_GPU_WRITE);
 			obj_priv->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
 		}
 		/* unlocks object and list */
diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h
index 50ae5746267..0796edbacad 100644
--- a/sys/dev/pci/drm/i915_drv.h
+++ b/sys/dev/pci/drm/i915_drv.h
@@ -836,7 +836,6 @@ struct inteldrm_file {
 /* flags we use in drm_obj's do_flags */
 #define I915_IN_EXEC		0x0020	/* being processed in execbuffer */
 #define I915_USER_PINNED	0x0040	/* BO has been pinned from userland */
-#define I915_GPU_WRITE		0x0080	/* BO has been not flushed */
 #define I915_EXEC_NEEDS_FENCE	0x0800	/* being processed but will need fence*/
 
 /** driver private structure attached to each drm_gem_object */
@@ -886,6 +885,12 @@ struct drm_i915_gem_object {
 	unsigned int dirty:1;
 
 	/**
+	 * This is set if the object has been written to since the last
+	 * GPU flush.
+	 */
+	unsigned int pending_gpu_write:1;
+
+	/**
 	 * Advice: are the backing pages purgeable?
 	 */
 	unsigned int madv:2;
diff --git a/sys/dev/pci/drm/i915_gem.c b/sys/dev/pci/drm/i915_gem.c
index d801c1b73e6..8431aae4869 100644
--- a/sys/dev/pci/drm/i915_gem.c
+++ b/sys/dev/pci/drm/i915_gem.c
@@ -877,10 +877,10 @@ i915_gem_object_move_to_inactive_locked(struct drm_i915_gem_object *obj)
 	i915_gem_object_move_off_active(obj);
 	obj->fenced_gpu_access = false;
 
-	KASSERT((obj->base.do_flags & I915_GPU_WRITE) == 0);
 	/* unlock because this unref could recurse */
 	if (obj->active) {
 		obj->active = 0;
+		obj->pending_gpu_write = false;
 		drm_unref_locked(&obj->base.uobj);
 	} else {
 		drm_unlock_obj(&obj->base);
diff --git a/sys/dev/pci/drm/i915_gem_execbuffer.c b/sys/dev/pci/drm/i915_gem_execbuffer.c
index 6beccb35596..ad42c36c5e3 100644
--- a/sys/dev/pci/drm/i915_gem_execbuffer.c
+++ b/sys/dev/pci/drm/i915_gem_execbuffer.c
@@ -492,17 +492,11 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data,
 		obj_priv->fenced_gpu_access = obj_priv->pending_fenced_gpu_access;
 		/*
 		 * if we have a write domain, add us to the gpu write list
-		 * else we can remove the bit because it has been flushed.
 		 */
-		if (obj->do_flags & I915_GPU_WRITE)
-			list_del_init(&obj_priv->gpu_write_list);
 		if (obj->write_domain) {
+			obj_priv->pending_gpu_write = true;
 			list_move_tail(&obj_priv->gpu_write_list,
 				       &ring->gpu_write_list);
-			atomic_setbits_int(&obj->do_flags, I915_GPU_WRITE);
-		} else {
-			atomic_clearbits_int(&obj->do_flags,
-			     I915_GPU_WRITE);
 		}
 
 		i915_gem_object_move_to_active(to_intel_bo(object_list[i]), ring);