- Capitalize hex constants.

- Add OHCI_BITSET, the counterpart of OHCI_BITVAL.
- Make all the defined value fields have the _MASK/_BITPOS form.

1 files changed, 73 insertions, 71 deletions

diff --git a/sys/dev/ieee1394/fwohcireg.h b/sys/dev/ieee1394/fwohcireg.h
index d3fdf1f8f4e..65d087b5c9e 100644
--- a/sys/dev/ieee1394/fwohcireg.h
+++ b/sys/dev/ieee1394/fwohcireg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fwohcireg.h,v 1.2 2002/12/13 02:52:04 tdeval Exp $	*/
+/*	$OpenBSD: fwohcireg.h,v 1.3 2003/01/12 12:04:29 tdeval Exp $	*/
 /*	$NetBSD: fwohcireg.h,v 1.11 2002/01/26 16:34:27 ichiro Exp $	*/
 
 /*
@@ -78,99 +78,99 @@
 #define	OHCI_REG_Version			0x000
 #define	OHCI_REG_Guid_Rom			0x004
 #define	OHCI_REG_ATRetries			0x008
-#define	OHCI_REG_CsrReadData			0x00c
+#define	OHCI_REG_CsrReadData			0x00C
 #define	OHCI_REG_CsrCompareData			0x010
 #define	OHCI_REG_CsrControl			0x014
 #define	OHCI_REG_ConfigROMhdr			0x018
-#define	OHCI_REG_BusId				0x01c
+#define	OHCI_REG_BusId				0x01C
 #define	OHCI_REG_BusOptions			0x020
 #define	OHCI_REG_GUIDHi				0x024
 #define	OHCI_REG_GUIDLo				0x028
-#define	OHCI_REG_reserved_02c			0x02c
+#define	OHCI_REG_reserved_02c			0x02C
 #define	OHCI_REG_reserved_030			0x030
 #define	OHCI_REG_ConfigROMmap			0x034
 #define	OHCI_REG_PostedWriteAddressLo		0x038
-#define	OHCI_REG_PostedWriteAddressHi		0x03c
+#define	OHCI_REG_PostedWriteAddressHi		0x03C
 #define	OHCI_REG_VendorId			0x040
 #define	OHCI_REG_reserved_044			0x044
 #define	OHCI_REG_reserved_048			0x048
-#define	OHCI_REG_reserved_04c			0x04c
+#define	OHCI_REG_reserved_04c			0x04C
 #define	OHCI_REG_HCControlSet			0x050
 #define	OHCI_REG_HCControlClear			0x054
 #define	OHCI_REG_reserved_058			0x058
-#define	OHCI_REG_reserved_05c			0x05c
+#define	OHCI_REG_reserved_05c			0x05C
 #define	OHCI_REG_reserved_060			0x060
 #define	OHCI_REG_SelfIDBuffer			0x064
 #define	OHCI_REG_SelfIDCount			0x068
-#define	OHCI_REG_reserved_06c			0x06c
+#define	OHCI_REG_reserved_06c			0x06C
 #define	OHCI_REG_IRMultiChanMaskHiSet		0x070
 #define	OHCI_REG_IRMultiChanMaskHiClear		0x074
 #define	OHCI_REG_IRMultiChanMaskLoSet		0x078
-#define	OHCI_REG_IRMultiChanMaskLoClear		0x07c
+#define	OHCI_REG_IRMultiChanMaskLoClear		0x07C
 #define	OHCI_REG_IntEventSet			0x080
 #define	OHCI_REG_IntEventClear			0x084
 #define	OHCI_REG_IntMaskSet			0x088
-#define	OHCI_REG_IntMaskClear			0x08c
+#define	OHCI_REG_IntMaskClear			0x08C
 #define	OHCI_REG_IsoXmitIntEventSet		0x090
 #define	OHCI_REG_IsoXmitIntEventClear		0x094
 #define	OHCI_REG_IsoXmitIntMaskSet		0x098
-#define	OHCI_REG_IsoXmitIntMaskClear		0x09c
-#define	OHCI_REG_IsoRecvIntEventSet		0x0a0
-#define	OHCI_REG_IsoRecvIntEventClear		0x0a4
-#define	OHCI_REG_IsoRecvIntMaskSet		0x0a8
-#define	OHCI_REG_IsoRecvIntMaskClear		0x0ac
-#define	OHCI_REG_InitialBandwidthAvailable	0x0b0
-#define	OHCI_REG_InitialChannelsAvailableHi	0x0b4
-#define	OHCI_REG_InitialChannelsAvailableLo	0x0b8
-#define	OHCI_REG_reserved_0bc			0x0bc
-#define	OHCI_REG_reserved_0c0			0x0c0
-#define	OHCI_REG_reserved_0c4			0x0c4
-#define	OHCI_REG_reserved_0c8			0x0c8
-#define	OHCI_REG_reserved_0cc			0x0cc
-#define	OHCI_REG_reserved_0d0			0x0d0
-#define	OHCI_REG_reserved_0d4			0x0d4
-#define	OHCI_REG_reserved_0d8			0x0d8
-#define	OHCI_REG_FairnessConctrol		0x0dc
-#define	OHCI_REG_LinkControlSet			0x0e0
-#define	OHCI_REG_LinkControlClear		0x0e4
-#define	OHCI_REG_NodeId				0x0e8
-#define	OHCI_REG_PhyControl			0x0ec
-#define	OHCI_REG_IsochronousCycleTimer		0x0f0
-#define	OHCI_REG_reserved_0f0			0x0f4
-#define	OHCI_REG_reserved_0f8			0x0f8
-#define	OHCI_REG_reserved_0fc			0x0fc
+#define	OHCI_REG_IsoXmitIntMaskClear		0x09C
+#define	OHCI_REG_IsoRecvIntEventSet		0x0A0
+#define	OHCI_REG_IsoRecvIntEventClear		0x0A4
+#define	OHCI_REG_IsoRecvIntMaskSet		0x0A8
+#define	OHCI_REG_IsoRecvIntMaskClear		0x0AC
+#define	OHCI_REG_InitialBandwidthAvailable	0x0B0
+#define	OHCI_REG_InitialChannelsAvailableHi	0x0B4
+#define	OHCI_REG_InitialChannelsAvailableLo	0x0B8
+#define	OHCI_REG_reserved_0bc			0x0BC
+#define	OHCI_REG_reserved_0c0			0x0C0
+#define	OHCI_REG_reserved_0c4			0x0C4
+#define	OHCI_REG_reserved_0c8			0x0C8
+#define	OHCI_REG_reserved_0cc			0x0CC
+#define	OHCI_REG_reserved_0d0			0x0D0
+#define	OHCI_REG_reserved_0d4			0x0D4
+#define	OHCI_REG_reserved_0d8			0x0D8
+#define	OHCI_REG_FairnessConctrol		0x0DC
+#define	OHCI_REG_LinkControlSet			0x0E0
+#define	OHCI_REG_LinkControlClear		0x0E4
+#define	OHCI_REG_NodeId				0x0E8
+#define	OHCI_REG_PhyControl			0x0EC
+#define	OHCI_REG_IsochronousCycleTimer		0x0F0
+#define	OHCI_REG_reserved_0f0			0x0F4
+#define	OHCI_REG_reserved_0f8			0x0F8
+#define	OHCI_REG_reserved_0fc			0x0FC
 #define	OHCI_REG_AsynchronousRequestFilterHiSet	0x100
 #define	OHCI_REG_AsynchronousRequestFilterHiClear 0x104
 #define	OHCI_REG_AsynchronousRequestFilterLoSet	0x108
-#define	OHCI_REG_AsynchronousRequestFilterLoClear 0x10c
+#define	OHCI_REG_AsynchronousRequestFilterLoClear 0x10C
 #define	OHCI_REG_PhysicalRequestFilterHiSet	0x110
 #define	OHCI_REG_PhysicalRequestFilterHiClear	0x114
 #define	OHCI_REG_PhysicalRequestFilterLoSet	0x118
-#define	OHCI_REG_PhysicalRequestFilterLoClear	0x11c
+#define	OHCI_REG_PhysicalRequestFilterLoClear	0x11C
 #define	OHCI_REG_PhysicalUpperBound		0x120
 #define	OHCI_REG_reserved_124			0x124
 #define	OHCI_REG_reserved_128			0x128
-#define	OHCI_REG_reserved_12c			0x12c
+#define	OHCI_REG_reserved_12c			0x12C
 #define	OHCI_REG_reserved_130			0x130
 #define	OHCI_REG_reserved_134			0x134
 #define	OHCI_REG_reserved_138			0x138
-#define	OHCI_REG_reserved_13c			0x13c
+#define	OHCI_REG_reserved_13c			0x13C
 #define	OHCI_REG_reserved_140			0x140
 #define	OHCI_REG_reserved_144			0x144
 #define	OHCI_REG_reserved_148			0x148
-#define	OHCI_REG_reserved_14c			0x14c
+#define	OHCI_REG_reserved_14c			0x14C
 #define	OHCI_REG_reserved_150			0x150
 #define	OHCI_REG_reserved_154			0x154
 #define	OHCI_REG_reserved_158			0x158
-#define	OHCI_REG_reserved_15c			0x15c
+#define	OHCI_REG_reserved_15c			0x15C
 #define	OHCI_REG_reserved_160			0x160
 #define	OHCI_REG_reserved_164			0x164
 #define	OHCI_REG_reserved_168			0x168
-#define	OHCI_REG_reserved_16c			0x16c
+#define	OHCI_REG_reserved_16c			0x16C
 #define	OHCI_REG_reserved_170			0x170
 #define	OHCI_REG_reserved_174			0x174
 #define	OHCI_REG_reserved_178			0x178
-#define	OHCI_REG_reserved_17c			0x17c
+#define	OHCI_REG_reserved_17c			0x17C
 
 
 #define	OHCI_REG_ASYNC_DMA_BASE			0x180
@@ -181,11 +181,11 @@
 #define	OHCI_SUBREG_ContextControlSet		0x000
 #define	OHCI_SUBREG_ContextControlClear		0x004
 #define	OHCI_SUBREG_reserved_008		0x008
-#define	OHCI_SUBREG_CommandPtr			0x00c
+#define	OHCI_SUBREG_CommandPtr			0x00C
 #define	OHCI_SUBREG_ContextMatch		0x010
 #define	OHCI_SUBREG_reserved_014		0x014
 #define	OHCI_SUBREG_reserved_018		0x018
-#define	OHCI_SUBREG_reserved_01c		0x01c
+#define	OHCI_SUBREG_reserved_01c		0x01C
 #define	OHCI_ASYNC_DMA_WRITE(sc, ctx, reg, val) \
 	OHCI_CSR_WRITE(sc, OHCI_REG_ASYNC_DMA_BASE + 32*(ctx) + (reg), val)
 #define	OHCI_ASYNC_DMA_READ(sc, ctx, reg) \
@@ -205,22 +205,24 @@
 
 #define	OHCI_BITVAL(val, name) \
 	((((val) & name##_MASK) >> name##_BITPOS))
+#define	OHCI_BITSET(val, name) \
+	((((val) << name##_BITPOS) & name##_MASK))
 
 /* OHCI_REG_Version
  */
 #define	OHCI_Version_GUID_ROM			0x01000000
 #define	OHCI_Version_GET_Version(x) \
-	((((x) >> 16) & 0xf) + (((x) >> 20) & 0xf) * 10)
+	((((x) >> 16) & 0xF) + (((x) >> 20) & 0xF) * 10)
 #define	OHCI_Version_GET_Revision(x) \
-	((((x) >> 4) & 0xf) + ((x) & 0xf) * 10)
+	((((x) >> 4) & 0xF) + ((x) & 0xF) * 10)
 
 /* OHCI_REG_Guid_Rom
  */
 #define	OHCI_Guid_AddrReset			0x80000000
 #define	OHCI_Guid_RdStart			0x02000000
-#define	OHCI_Guid_RdData_MASK			0x00ff0000
+#define	OHCI_Guid_RdData_MASK			0x00FF0000
 #define	OHCI_Guid_RdData_BITPOS			16
-#define	OHCI_Guid_MiniROM_MASK			0x000000ff
+#define	OHCI_Guid_MiniROM_MASK			0x000000FF
 #define	OHCI_Guid_MiniROM_BITPOS		0
 
 /* OHCI_REG_GUIDxx
@@ -239,18 +241,18 @@
  */
 #define	OHCI_BusOptions_LinkSpd_MASK		0x00000007
 #define	OHCI_BusOptions_LinkSpd_BITPOS		0
-#define	OHCI_BusOptions_G_MASK			0x000000c0
+#define	OHCI_BusOptions_G_MASK			0x000000C0
 #define	OHCI_BusOptions_G_BITPOS		6
-#define	OHCI_BusOptions_MaxRec_MASK		0x0000f000
+#define	OHCI_BusOptions_MaxRec_MASK		0x0000F000
 #define	OHCI_BusOptions_MaxRec_BITPOS		12
-#define	OHCI_BusOptions_CycClkAcc_MASK		0x00ff0000
+#define	OHCI_BusOptions_CycClkAcc_MASK		0x00FF0000
 #define	OHCI_BusOptions_CycClkAcc_BITPOS	16
 #define	OHCI_BusOptions_PMC			0x08000000
 #define	OHCI_BusOptions_BMC			0x10000000
 #define	OHCI_BusOptions_ISC			0x20000000
 #define	OHCI_BusOptions_CMC			0x40000000
 #define	OHCI_BusOptions_IRMC			0x80000000
-#define	OHCI_BusOptions_reserved		0x07000f38
+#define	OHCI_BusOptions_reserved		0x07000F38
 
 /* OHCI_REG_HCControl
  */
@@ -267,9 +269,9 @@
 /* OHCI_REG_SelfID
  */
 #define	OHCI_SelfID_Error			0x80000000
-#define	OHCI_SelfID_Gen_MASK			0x00ff0000
+#define	OHCI_SelfID_Gen_MASK			0x00FF0000
 #define	OHCI_SelfID_Gen_BITPOS			16
-#define	OHCI_SelfID_Size_MASK			0x000007fc
+#define	OHCI_SelfID_Size_MASK			0x000007FC
 #define	OHCI_SelfID_Size_BITPOS			2
 
 /* OHCI_REG_Int{Event|Mask}*
@@ -315,21 +317,21 @@
 #define	OHCI_NodeId_IDValid			0x80000000
 #define	OHCI_NodeId_ROOT			0x40000000
 #define	OHCI_NodeId_CPS				0x08000000
-#define	OHCI_NodeId_BusNumber			0x0000ffc0
-#define	OHCI_NodeId_NodeNumber			0x0000003f
+#define	OHCI_NodeId_BusNumber			0x0000FFC0
+#define	OHCI_NodeId_NodeNumber			0x0000003F
 
 /* OHCI_REG_PhyControl
  */
 #define	OHCI_PhyControl_RdDone			0x80000000
-#define	OHCI_PhyControl_RdAddr			0x0f000000
+#define	OHCI_PhyControl_RdAddr_MASK		0x0F000000
 #define	OHCI_PhyControl_RdAddr_BITPOS		24
-#define	OHCI_PhyControl_RdData			0x00ff0000
+#define	OHCI_PhyControl_RdData_MASK		0x00FF0000
 #define	OHCI_PhyControl_RdData_BITPOS		16
 #define	OHCI_PhyControl_RdReg			0x00008000
 #define	OHCI_PhyControl_WrReg			0x00004000
-#define	OHCI_PhyControl_RegAddr			0x00000f00
+#define	OHCI_PhyControl_RegAddr_MASK		0x00000F00
 #define	OHCI_PhyControl_RegAddr_BITPOS		8
-#define	OHCI_PhyControl_WrData			0x000000ff
+#define	OHCI_PhyControl_WrData_MASK		0x000000FF
 #define	OHCI_PhyControl_WrData_BITPOS		0
 
 /*
@@ -342,14 +344,14 @@
 #define	OHCI_CTXCTL_DEAD			0x00000800
 #define	OHCI_CTXCTL_ACTIVE			0x00000400
 
-#define	OHCI_CTXCTL_SPD_BITLEN			3
-#define	OHCI_CTXCTL_SPD_BITPOS			5
+#define	OHCI_CTXCTL_SPD_MASK			0x00E00000
+#define	OHCI_CTXCTL_SPD_BITPOS			21
 
 #define	OHCI_CTXCTL_SPD_100			0
 #define	OHCI_CTXCTL_SPD_200			1
 #define	OHCI_CTXCTL_SPD_400			2
 
-#define	OHCI_CTXCTL_EVENT_BITLEN		5
+#define	OHCI_CTXCTL_EVENT_MASK			0x0000001F
 #define	OHCI_CTXCTL_EVENT_BITPOS		0
 
 /* Events from 0 to 15 are generated by the OpenHCI controller.
@@ -482,7 +484,7 @@
 /* Context Control for isochronous transmit context
  */
 #define	OHCI_CTXCTL_TX_CYCLE_MATCH_ENABLE	0x80000000
-#define	OHCI_CTXCTL_TX_CYCLE_MATCH_BITLEN	0x7fff0000
+#define	OHCI_CTXCTL_TX_CYCLE_MATCH_MASK		0x7FFF0000
 #define	OHCI_CTXCTL_TX_CYCLE_MATCH_BITPOS	16
 
 #define	OHCI_CTXCTL_RX_BUFFER_FILL		0x80000000
@@ -497,19 +499,19 @@
 #define	OHCI_CTXMATCH_TAG2			0x40000000
 #define	OHCI_CTXMATCH_TAG1			0x20000000
 #define	OHCI_CTXMATCH_TAG0			0x10000000
-#define	OHCI_CTXMATCH_CYCLE_MATCH_MASK		0x07fff000
+#define	OHCI_CTXMATCH_CYCLE_MATCH_MASK		0x07FFF000
 #define	OHCI_CTXMATCH_CYCLE_MATCH_BITPOS	12
-#define	OHCI_CTXMATCH_SYNC_MASK			0x00000f00
+#define	OHCI_CTXMATCH_SYNC_MASK			0x00000F00
 #define	OHCI_CTXMATCH_SYNC_BITPOS		8
 #define	OHCI_CTXMATCH_TAG1_SYNC_FILTER		0x00000040
-#define	OHCI_CTXMATCH_CHANNEL_NUMBER_MASK	0x0000003f
+#define	OHCI_CTXMATCH_CHANNEL_NUMBER_MASK	0x0000003F
 #define	OHCI_CTXMATCH_CHANNEL_NUMBER_BITPOS	0
 
 /*
  * Miscellaneous definitions.
  */
 
-#define	OHCI_TCODE_PHY				0xe
+#define	OHCI_TCODE_PHY				0xE
 
 #if BYTE_ORDER == BIG_ENDIAN
 typedef struct fwohci_desc {
@@ -546,13 +548,13 @@ typedef struct fwohci_desc {
 #define	OHCI_DESC_PING				0x0080
 #define	OHCI_DESC_INTR_ALWAYS			0x0030
 #define	OHCI_DESC_INTR_ERR			0x0010
-#define	OHCI_DESC_BRANCH			0x000c
+#define	OHCI_DESC_BRANCH			0x000C
 #define	OHCI_DESC_WAIT				0x0003
 
 #define	OHCI_DESC_MAX				8
 
 /* Some constants for passing ACK values around with from status reg's */
 
-#define	OHCI_DESC_STATUS_ACK_MASK		0x1f
+#define	OHCI_DESC_STATUS_ACK_MASK		0x1F
 
 #endif	/* _DEV_IEEE1394_FWOHCIREG_ */