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authorJonathan Gray <jsg@cvs.openbsd.org>2019-07-11 01:48:44 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2019-07-11 01:48:44 +0000
commite1d1e775a33a475dcd3ae77f7760fbec38d9143e (patch)
tree0c241b16ae383bf17f4e0937751612660b3ef1dd /sys/dev
parent320167d60ded46578f4aa42f3a6bb22fa3fdbd3e (diff)
drm/amdgpu/gfx9: use reset default for PA_SC_FIFO_SIZE
From Alex Deucher ec5d99e18d306bed13935b0f0634bd00caa26a42 in linux 4.19.y/4.19.58 25f09f858835b0e9a06213811031190a17d8ab78 in mainline linux
Diffstat (limited to 'sys/dev')
-rw-r--r--sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c19
1 files changed, 0 insertions, 19 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
index 9054ac43b7d..7d3beabef7c 100644
--- a/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
+++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v9_0.c
@@ -1811,25 +1811,6 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
mutex_unlock(&adev->srbm_mutex);
gfx_v9_0_init_compute_vmid(adev);
-
- mutex_lock(&adev->grbm_idx_mutex);
- /*
- * making sure that the following register writes will be broadcasted
- * to all the shaders
- */
- gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
-
- WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
- (adev->gfx.config.sc_prim_fifo_size_frontend <<
- PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
- (adev->gfx.config.sc_prim_fifo_size_backend <<
- PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
- (adev->gfx.config.sc_hiz_tile_fifo_size <<
- PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
- (adev->gfx.config.sc_earlyz_tile_fifo_size <<
- PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
- mutex_unlock(&adev->grbm_idx_mutex);
-
}
static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)