remove a useless timeout after tx (decrease nasty delays while

scanning) and fix various other minor things in the ath(4) driver.

9 files changed, 155 insertions, 90 deletions

diff --git a/sys/dev/ic/ar5211.c b/sys/dev/ic/ar5211.c
index f54da0006fc..41800bc4bdc 100644
--- a/sys/dev/ic/ar5211.c
+++ b/sys/dev/ic/ar5211.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5211.c,v 1.18 2005/06/17 12:51:08 reyk Exp $	*/
+/*	$OpenBSD: ar5211.c,v 1.19 2005/07/30 17:13:17 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -509,6 +509,15 @@ ar5k_ar5211_reset(hal, op_mode, channel, change_channel, status)
 	 * Configure additional registers
 	 */
 
+	if (hal->ah_radio == AR5K_AR5111) {
+		if (channel->c_channel_flags & IEEE80211_CHAN_B)
+			AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG,
+			    AR5K_AR5211_TXCFG_B_MODE);
+		else
+			AR5K_REG_DISABLE_BITS(AR5K_AR5211_TXCFG,
+			    AR5K_AR5211_TXCFG_B_MODE);
+	}
+
 	/* Set antenna mode */
 	AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44),
 	    hal->ah_antenna[ee_mode][0], 0xfffffc06);
@@ -579,6 +588,14 @@ ar5k_ar5211_reset(hal, op_mode, channel, change_channel, status)
 	AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES);
 
 	/*
+	 * Set Rx/Tx DMA Configuration
+	 */
+	AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_SDMAMR,
+	    AR5K_AR5211_DMASIZE_512B | AR5K_AR5211_TXCFG_DMASIZE);
+	AR5K_REG_WRITE_BITS(AR5K_AR5211_RXCFG, AR5K_AR5211_RXCFG_SDMAMW,
+	    AR5K_AR5211_DMASIZE_512B);
+
+	/*
 	 * Set channel and calibrate the PHY
 	 */
 	if (ar5k_channel(hal, channel) == AH_FALSE)
@@ -1081,6 +1098,8 @@ ar5k_ar5211_stop_tx_dma(hal, queue)
 	struct ath_hal *hal;
 	u_int queue;
 {
+	int i = 100, pending;
+
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
 
 	/*
@@ -1088,11 +1107,11 @@ ar5k_ar5211_stop_tx_dma(hal, queue)
 	 */
 	AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue);
 
-	ar5k_register_timeout(hal, AR5K_AR5211_QCU_STS(queue),
-	    AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE);
-
-	if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue))
-		return (AH_FALSE);
+	do {
+		pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) &
+		     AR5K_AR5211_QCU_STS_FRMPENDCNT;
+		delay(100);
+	} while (--i && pending);
 
 	/* Clear register */
 	AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0);
@@ -1896,8 +1915,7 @@ ar5k_ar5211_set_slot_time(hal, slot_time)
 	if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX)
 		return (AH_FALSE);
 
-	AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT,
-	    ar5k_htoclock(slot_time, hal->ah_turbo));
+	AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time);
 
 	return (AH_TRUE);
 }
@@ -1906,8 +1924,7 @@ u_int
 ar5k_ar5211_get_slot_time(hal)
 	struct ath_hal *hal;
 {
-	return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) &
-	    0xffff, hal->ah_turbo));
+	return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff);
 }
 
 HAL_BOOL
diff --git a/sys/dev/ic/ar5211reg.h b/sys/dev/ic/ar5211reg.h
index 01eb75339d4..d4d2d9cb8dc 100644
--- a/sys/dev/ic/ar5211reg.h
+++ b/sys/dev/ic/ar5211reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5211reg.h,v 1.5 2005/05/08 14:46:50 reyk Exp $	*/
+/*	$OpenBSD: ar5211reg.h,v 1.6 2005/07/30 17:13:17 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -91,6 +91,7 @@
  */
 #define AR5K_AR5211_TXCFG		0x0030
 #define AR5K_AR5211_TXCFG_SDMAMR	0x00000007
+#define AR5K_AR5211_TXCFG_SDMAMR_S	0
 #define AR5K_AR5211_TXCFG_B_MODE	0x00000008
 #define AR5K_AR5211_TXCFG_TXFULL	0x000003f0
 #define AR5K_AR5211_TXCFG_TXFULL_S	4
@@ -100,6 +101,7 @@
 #define AR5K_AR5211_TXCFG_TXFULL_192B	0x00000030
 #define AR5K_AR5211_TXCFG_TXFULL_256B	0x00000040
 #define AR5K_AR5211_TXCFG_TXCONT_ENABLE	0x00000080
+#define AR5K_AR5211_TXCFG_DMASIZE	0x00000100
 #define AR5K_AR5211_TXCFG_JUMBO_TXE	0x00000400
 #define AR5K_AR5211_TXCFG_RTSRND	0x00001000
 #define AR5K_AR5211_TXCFG_FRMPAD_DIS	0x00002000
@@ -110,6 +112,7 @@
  */
 #define AR5K_AR5211_RXCFG			0x0034
 #define AR5K_AR5211_RXCFG_SDMAMW		0x00000007
+#define AR5K_AR5211_RXCFG_SDMAMW_S		0
 #define	AR5K_AR5311_RXCFG_DEFAULT_ANTENNA	0x00000008
 #define AR5K_AR5211_RXCFG_ZLFDMA		0x00000010
 #define AR5K_AR5211_RXCFG_JUMBO_RXE		0x00000020
@@ -524,13 +527,13 @@
  */
 typedef enum {
 	AR5K_AR5211_DMASIZE_4B = 0,
-	AR5K_AR5211_DMASIZE_8B,
-	AR5K_AR5211_DMASIZE_16B,
-	AR5K_AR5211_DMASIZE_32B,
-	AR5K_AR5211_DMASIZE_64B,
-	AR5K_AR5211_DMASIZE_128B,
-	AR5K_AR5211_DMASIZE_256B,
-	AR5K_AR5211_DMASIZE_512B
+	AR5K_AR5211_DMASIZE_8B = 1,
+	AR5K_AR5211_DMASIZE_16B = 2,
+	AR5K_AR5211_DMASIZE_32B = 3,
+	AR5K_AR5211_DMASIZE_64B = 4,
+	AR5K_AR5211_DMASIZE_128B = 5,
+	AR5K_AR5211_DMASIZE_256B = 6,
+	AR5K_AR5211_DMASIZE_512B = 7
 } ar5k_ar5211_dmasize_t;
 
 /*
diff --git a/sys/dev/ic/ar5211var.h b/sys/dev/ic/ar5211var.h
index c4cd4b45c5b..cd4fdf2b904 100644
--- a/sys/dev/ic/ar5211var.h
+++ b/sys/dev/ic/ar5211var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5211var.h,v 1.5 2005/04/20 01:46:02 reyk Exp $	*/
+/*	$OpenBSD: ar5211var.h,v 1.6 2005/07/30 17:13:17 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -362,7 +362,7 @@ struct ar5k_ar5211_ini_mode {
 };
 
 #define AR5K_AR5211_INI_MODE {						\
-	{ 0x0030, { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },	\
+	{ 0x0030, { 0x00000017, 0x00000017, 0x00000017, 0x00000017 } },	\
 	{ 0x1040, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
 	{ 0x1044, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
 	{ 0x1048, { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },	\
diff --git a/sys/dev/ic/ar5212.c b/sys/dev/ic/ar5212.c
index 2caf3f13470..6b47ef2187d 100644
--- a/sys/dev/ic/ar5212.c
+++ b/sys/dev/ic/ar5212.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212.c,v 1.22 2005/06/17 12:51:08 reyk Exp $	*/
+/*	$OpenBSD: ar5212.c,v 1.23 2005/07/30 17:13:17 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -620,6 +620,15 @@ ar5k_ar5212_reset(hal, op_mode, channel, change_channel, status)
 		    AR5K_AR5212_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
 	}
 
+	if (hal->ah_radio == AR5K_AR5111) {
+		if (channel->c_channel_flags & IEEE80211_CHAN_B)
+			AR5K_REG_ENABLE_BITS(AR5K_AR5212_TXCFG,
+			    AR5K_AR5212_TXCFG_B_MODE);
+		else
+			AR5K_REG_DISABLE_BITS(AR5K_AR5212_TXCFG,
+			    AR5K_AR5212_TXCFG_B_MODE);
+	}
+
 	/* Set antenna mode */
 	AR5K_REG_MASKED_BITS(AR5K_AR5212_PHY(0x44),
 	    hal->ah_antenna[ee_mode][0], 0xfffffc06);
@@ -697,6 +706,14 @@ ar5k_ar5212_reset(hal, op_mode, channel, change_channel, status)
 	AR5K_REG_WRITE(AR5K_AR5212_RSSI_THR, AR5K_TUNE_RSSI_THRES);
 
 	/*
+	 * Set Rx/Tx DMA Configuration
+	 */
+	AR5K_REG_WRITE_BITS(AR5K_AR5212_TXCFG, AR5K_AR5212_TXCFG_SDMAMR,
+	    AR5K_AR5212_DMASIZE_512B | AR5K_AR5212_TXCFG_DMASIZE);
+	AR5K_REG_WRITE_BITS(AR5K_AR5212_RXCFG, AR5K_AR5212_RXCFG_SDMAMW,
+	    AR5K_AR5212_DMASIZE_512B);
+
+	/*
 	 * Set channel and calibrate the PHY
 	 */
 	if (ar5k_channel(hal, channel) == AH_FALSE)
@@ -1223,6 +1240,8 @@ ar5k_ar5212_stop_tx_dma(hal, queue)
 	struct ath_hal *hal;
 	u_int queue;
 {
+	int i = 100, pending;
+
 	AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
 
 	/*
@@ -1230,15 +1249,15 @@ ar5k_ar5212_stop_tx_dma(hal, queue)
 	 */
 	AR5K_REG_WRITE_Q(AR5K_AR5212_QCU_TXD, queue);
 
-	ar5k_register_timeout(hal, AR5K_AR5212_QCU_STS(queue),
-	    AR5K_AR5212_QCU_STS_FRMPENDCNT, 0, AH_FALSE);
+	do {
+		pending = AR5K_REG_READ(AR5K_AR5212_QCU_STS(queue)) &
+		     AR5K_AR5212_QCU_STS_FRMPENDCNT;
+		delay(100);
+	} while (--i && pending);
 
 	/* Clear register */
 	AR5K_REG_WRITE(AR5K_AR5212_QCU_TXD, 0);
 
-	if (AR5K_REG_READ_Q(AR5K_AR5212_QCU_TXE, queue))
-		return (AH_FALSE);
-
 	return (AH_TRUE);
 }
 
@@ -1280,7 +1299,8 @@ ar5k_ar5212_setup_tx_desc(hal, desc, packet_length, header_length, type,
 	tx_desc->tx_control_1 =
 	    AR5K_REG_SM(type, AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE);
 	tx_desc->tx_control_2 =
-	    AR5K_REG_SM(tx_tries0, AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0);
+	    AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
+	    AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0);
 	tx_desc->tx_control_3 =
 	    tx_rate0 & AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0;
 
@@ -2204,8 +2224,7 @@ ar5k_ar5212_set_slot_time(hal, slot_time)
 	if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX)
 		return (AH_FALSE);
 
-	AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT,
-	    ar5k_htoclock(slot_time, hal->ah_turbo));
+	AR5K_REG_WRITE(AR5K_AR5212_DCU_GBL_IFS_SLOT, slot_time);
 
 	return (AH_TRUE);
 }
@@ -2214,8 +2233,7 @@ u_int
 ar5k_ar5212_get_slot_time(hal)
 	struct ath_hal *hal;
 {
-	return (ar5k_clocktoh(AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) &
-	    0xffff, hal->ah_turbo));
+	return (AR5K_REG_READ(AR5K_AR5212_DCU_GBL_IFS_SLOT) & 0xffff);
 }
 
 HAL_BOOL
diff --git a/sys/dev/ic/ar5212reg.h b/sys/dev/ic/ar5212reg.h
index 5893f248984..f049a14885b 100644
--- a/sys/dev/ic/ar5212reg.h
+++ b/sys/dev/ic/ar5212reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212reg.h,v 1.5 2005/05/08 14:46:50 reyk Exp $	*/
+/*	$OpenBSD: ar5212reg.h,v 1.6 2005/07/30 17:13:17 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -65,6 +65,7 @@
  */
 #define AR5K_AR5212_TXCFG		0x0030
 #define AR5K_AR5212_TXCFG_SDMAMR	0x00000007
+#define AR5K_AR5212_TXCFG_SDMAMR_S	0
 #define AR5K_AR5212_TXCFG_B_MODE	0x00000008
 #define AR5K_AR5212_TXCFG_TXFULL	0x000003f0
 #define AR5K_AR5212_TXCFG_TXFULL_S	4
@@ -74,6 +75,7 @@
 #define AR5K_AR5212_TXCFG_TXFULL_192B	0x00000030
 #define AR5K_AR5212_TXCFG_TXFULL_256B	0x00000040
 #define AR5K_AR5212_TXCFG_TXCONT_ENABLE	0x00000080
+#define AR5K_AR5212_TXCFG_DMASIZE	0x00000100
 #define AR5K_AR5212_TXCFG_JUMBO_TXE	0x00000400
 #define AR5K_AR5212_TXCFG_RTSRND	0x00001000
 #define AR5K_AR5212_TXCFG_FRMPAD_DIS	0x00002000
@@ -84,6 +86,7 @@
  */
 #define AR5K_AR5212_RXCFG			0x0034
 #define AR5K_AR5212_RXCFG_SDMAMW		0x00000007
+#define AR5K_AR5212_RXCFG_SDMAMW_S		0
 #define	AR5K_AR5311_RXCFG_DEFAULT_ANTENNA	0x00000008
 #define AR5K_AR5212_RXCFG_ZLFDMA		0x00000010
 #define AR5K_AR5212_RXCFG_JUMBO_RXE		0x00000020
@@ -539,13 +542,13 @@
  */
 typedef enum {
 	AR5K_AR5212_DMASIZE_4B = 0,
-	AR5K_AR5212_DMASIZE_8B,
-	AR5K_AR5212_DMASIZE_16B,
-	AR5K_AR5212_DMASIZE_32B,
-	AR5K_AR5212_DMASIZE_64B,
-	AR5K_AR5212_DMASIZE_128B,
-	AR5K_AR5212_DMASIZE_256B,
-	AR5K_AR5212_DMASIZE_512B
+	AR5K_AR5212_DMASIZE_8B = 1,
+	AR5K_AR5212_DMASIZE_16B = 2,
+	AR5K_AR5212_DMASIZE_32B = 3,
+	AR5K_AR5212_DMASIZE_64B = 4,
+	AR5K_AR5212_DMASIZE_128B = 5,
+	AR5K_AR5212_DMASIZE_256B = 6,
+	AR5K_AR5212_DMASIZE_512B = 7
 } ar5k_ar5212_dmasize_t;
 
 /*
diff --git a/sys/dev/ic/ar5212var.h b/sys/dev/ic/ar5212var.h
index c2f0f544b30..34cdf309a55 100644
--- a/sys/dev/ic/ar5212var.h
+++ b/sys/dev/ic/ar5212var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212var.h,v 1.7 2005/04/18 18:42:55 reyk Exp $	*/
+/*	$OpenBSD: ar5212var.h,v 1.8 2005/07/30 17:13:17 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -630,7 +630,7 @@ struct ar5k_ar5212_ini_mode {
 #define AR5K_AR5212_INI_MODE {							\
 	{ 0x0030, AR5K_INI_FLAG_511X, {						\
 		{ 0, },								\
-		{ 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 }	\
+		{ 0x00008107, 0x00008107, 0x00008107, 0x00008107, 0x00008107 }	\
 	} },									\
 	{ 0x1040, AR5K_INI_FLAG_511X, {						\
 		{ 0, },								\
diff --git a/sys/dev/ic/ar5xxx.h b/sys/dev/ic/ar5xxx.h
index fd64d5ea405..3b58175477b 100644
--- a/sys/dev/ic/ar5xxx.h
+++ b/sys/dev/ic/ar5xxx.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5xxx.h,v 1.22 2005/05/27 04:10:06 reyk Exp $	*/
+/*	$OpenBSD: ar5xxx.h,v 1.23 2005/07/30 17:13:17 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
@@ -379,19 +379,19 @@ typedef struct {
 	255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,	\
 	3, 2, 1, 0, 255, 255, 255, 255 }, {				\
 	{ 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 },			\
-	{ 1, IEEE80211_T_CCK, 2000, 26, 0x00, 132, 1 },			\
-	{ 1, IEEE80211_T_CCK, 5500, 25, 0x00, 139, 1 },			\
-	{ 1, IEEE80211_T_CCK, 11000, 24, 0x00, 150, 1 } }		\
+	{ 1, IEEE80211_T_CCK, 2000, 26, 0x04, 132, 1 },			\
+	{ 1, IEEE80211_T_CCK, 5500, 25, 0x04, 139, 1 },			\
+	{ 1, IEEE80211_T_CCK, 11000, 24, 0x04, 150, 1 } }		\
 }
 
 #define AR5K_RATES_11G { 12, {						\
 	255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4,		\
 	11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,		\
 	3, 2, 1, 0, 255, 255, 255, 255 }, {				\
-	{ 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 },			\
-	{ 1, IEEE80211_T_CCK, 2000, 26, 0x00, 132, 1 },			\
-	{ 1, IEEE80211_T_CCK, 5500, 25, 0x00, 139, 1 },			\
-	{ 1, IEEE80211_T_CCK, 11000, 24, 0x00, 150, 1 },		\
+	{ 1, IEEE80211_T_CCK, 1000, 27, 0x00, 2, 0 },			\
+	{ 1, IEEE80211_T_CCK, 2000, 26, 0x04, 4, 1 },			\
+	{ 1, IEEE80211_T_CCK, 5500, 25, 0x04, 11, 1 },			\
+	{ 1, IEEE80211_T_CCK, 11000, 24, 0x04, 22, 1 },			\
 	{ 0, IEEE80211_T_OFDM, 6000, 11, 0, 12, 4 },			\
 	{ 0, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 },			\
 	{ 1, IEEE80211_T_OFDM, 12000, 10, 0, 24, 6 },			\
@@ -449,9 +449,9 @@ typedef struct {
 
 } HAL_CHANNEL;
 
-#define HAL_SLOT_TIME_9		9
-#define HAL_SLOT_TIME_20	20
-#define HAL_SLOT_TIME_MAX	ar5k_clocktoh(0xffff, hal->ah_turbo)
+#define HAL_SLOT_TIME_9		396
+#define HAL_SLOT_TIME_20	880
+#define HAL_SLOT_TIME_MAX	0xffff
 
 #define CHANNEL_A	(IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
 #define CHANNEL_B	(IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK)
@@ -1277,6 +1277,7 @@ typedef HAL_BOOL (ar5k_rfgain_t)
 #define AR5K_TUNE_DEFAULT_TXPOWER		30
 #define AR5K_TUNE_TPC_TXPOWER			AH_TRUE
 #define AR5K_TUNE_ANT_DIVERSITY			AH_TRUE
+#define AR5K_TUNE_HWTXTRIES			4
 
 /* Default regulation domain if stored value EEPROM value is invalid */
 #define AR5K_TUNE_REGDOMAIN	DMN_FCC1_FCCA
@@ -1298,7 +1299,7 @@ typedef HAL_BOOL (ar5k_rfgain_t)
 #define AR5K_INIT_PROG_IFS_TURBO		960
 #define AR5K_INIT_EIFS				3440
 #define AR5K_INIT_EIFS_TURBO			6880
-#define AR5K_INIT_SLOT_TIME			360
+#define AR5K_INIT_SLOT_TIME			396
 #define AR5K_INIT_SLOT_TIME_TURBO		480
 #define AR5K_INIT_ACK_CTS_TIMEOUT		1024
 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO		0x08000800
diff --git a/sys/dev/ic/ath.c b/sys/dev/ic/ath.c
index 17bc87e7411..66517321c27 100644
--- a/sys/dev/ic/ath.c
+++ b/sys/dev/ic/ath.c
@@ -1,4 +1,4 @@
-/*      $OpenBSD: ath.c,v 1.31 2005/07/19 23:04:37 reyk Exp $  */
+/*      $OpenBSD: ath.c,v 1.32 2005/07/30 17:13:17 reyk Exp $  */
 /*	$NetBSD: ath.c,v 1.37 2004/08/18 21:59:39 dyoung Exp $	*/
 
 /*-
@@ -88,7 +88,7 @@ int	ath_init1(struct ath_softc *);
 int	ath_intr1(struct ath_softc *);
 void	ath_stop(struct ifnet *);
 void	ath_start(struct ifnet *);
-void	ath_reset(struct ath_softc *);
+void	ath_reset(struct ath_softc *, int);
 int	ath_media_change(struct ifnet *);
 void	ath_watchdog(struct ifnet *);
 int	ath_ioctl(struct ifnet *, u_long, caddr_t);
@@ -124,6 +124,7 @@ void	ath_draintxq(struct ath_softc *);
 void	ath_stoprecv(struct ath_softc *);
 int	ath_startrecv(struct ath_softc *);
 void	ath_next_scan(void *);
+int	ath_set_slot_time(struct ath_softc *);
 void	ath_calibrate(void *);
 HAL_LED_STATE ath_state_to_led(enum ieee80211_state);
 int	ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
@@ -215,7 +216,7 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 	struct ath_hal *ah;
 	HAL_STATUS status;
 	HAL_TXQ_INFO qinfo;
-	int error = 0;
+	int error = 0, i;
 
 	DPRINTF(ATH_DEBUG_ANY, ("%s: devid 0x%x\n", __func__, devid));
 
@@ -311,12 +312,14 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 		goto bad2;
 	}
 
-	bzero(&qinfo, sizeof(qinfo));
-	qinfo.tqi_subtype = HAL_WME_AC_BE;
-	sc->sc_txhalq = ath_hal_setup_tx_queue(ah, HAL_TX_QUEUE_DATA, &qinfo);
-	if (sc->sc_txhalq == (u_int) -1) {
-		if_printf(ifp, "unable to setup a data xmit queue!\n");
-		goto bad2;
+	for (i = 0; i <= HAL_TX_QUEUE_ID_DATA_MAX; i++) {
+		bzero(&qinfo, sizeof(qinfo));
+		qinfo.tqi_subtype = i; /* should be mapped to WME types */
+		sc->sc_txhalq[i] = ath_hal_setup_tx_queue(ah, HAL_TX_QUEUE_DATA, &qinfo);
+		if (sc->sc_txhalq[i] == (u_int) -1) {
+			if_printf(ifp, "unable to setup a data xmit queue %u!\n", i);
+			goto bad2;
+		}
 	}
 
 	ifp->if_softc = sc;
@@ -342,6 +345,8 @@ ath_attach(u_int16_t devid, struct ath_softc *sc)
 	    | IEEE80211_C_IBSS		/* ibss, nee adhoc, mode */
 	    | IEEE80211_C_HOSTAP	/* hostap mode */
 	    | IEEE80211_C_MONITOR	/* monitor mode */
+	    | IEEE80211_C_SHSLOT	/* short slot time supported */
+	    | IEEE80211_C_SCANALL	/* scan all channels */
 	    | IEEE80211_C_SHPREAMBLE;	/* short preamble supported */
 
 	/*
@@ -603,8 +608,9 @@ ath_fatal_proc(void *arg, int pending)
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &ic->ic_if;
 
-	if_printf(ifp, "hardware error; resetting\n");
-	ath_reset(sc);
+	if (ifp->if_flags & IFF_DEBUG)
+		if_printf(ifp, "hardware error; resetting\n");
+	ath_reset(sc, 1);
 }
 
 void
@@ -614,8 +620,9 @@ ath_rxorn_proc(void *arg, int pending)
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &ic->ic_if;
 
-	if_printf(ifp, "rx FIFO overrun; resetting\n");
-	ath_reset(sc);
+	if (ifp->if_flags & IFF_DEBUG)
+		if_printf(ifp, "rx FIFO overrun; resetting\n");
+	ath_reset(sc, 1);
 }
 
 void
@@ -706,7 +713,7 @@ ath_init1(struct ath_softc *sc)
 		error = EIO;
 		goto done;
 	}
-
+	ath_set_slot_time(sc);
 	/*
 	 * Setup the hardware after reset: the key cache
 	 * is filled as needed and the receive engine is
@@ -814,7 +821,7 @@ ath_stop(struct ifnet *ifp)
  * and to reset the hardware when rf gain settings must be reset.
  */
 void
-ath_reset(struct ath_softc *sc)
+ath_reset(struct ath_softc *sc, int full)
 {
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &ic->ic_if;
@@ -835,10 +842,11 @@ ath_reset(struct ath_softc *sc)
 	ath_draintxq(sc);		/* stop xmit side */
 	ath_stoprecv(sc);		/* stop recv side */
 	/* NB: indicate channel change so we do a full reset */
-	if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) {
+	if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, full ? AH_TRUE : AH_FALSE, &status)) {
 		if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
 			__func__, status);
 	}
+	ath_set_slot_time(sc);
 	/* In case channel changed, save as a node channel */
 	ic->ic_bss->ni_chan = ic->ic_ibss_chan;
 	ath_hal_set_intr(ah, sc->sc_imask);
@@ -998,7 +1006,7 @@ ath_watchdog(struct ifnet *ifp)
 	if (sc->sc_tx_timer) {
 		if (--sc->sc_tx_timer == 0) {
 			if_printf(ifp, "device timeout\n");
-			ath_reset(sc);
+			ath_reset(sc, 1);
 			ifp->if_oerrors++;
 			sc->sc_stats.ast_watchdog++;
 			return;
@@ -1097,7 +1105,7 @@ ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 				if (ic->ic_opmode != IEEE80211_M_MONITOR)
 					ath_init(ifp);	/* XXX lose error */
 				else
-					ath_reset(sc);
+					ath_reset(sc, 1);
 			}
 			error = 0;
 		}
@@ -2088,6 +2096,7 @@ ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
 	const HAL_RATE_TABLE *rt;
 	HAL_BOOL shortPreamble;
 	struct ath_node *an;
+	u_int8_t hwqueue = HAL_TX_QUEUE_ID_DATA_MIN;
 
 	wh = mtod(m0, struct ieee80211_frame *);
 	iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
@@ -2359,6 +2368,7 @@ ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
 		    IEEE80211_RATE_VAL;
 		sc->sc_txtap.wt_txpower = 30;
 		sc->sc_txtap.wt_antenna = antenna;
+		sc->sc_txtap.wt_hwqueue = hwqueue;
 
 		M_DUP_PKTHDR(&mb, m0);
 		mb.m_data = (caddr_t)&sc->sc_txtap;
@@ -2421,7 +2431,7 @@ ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
 	s = splnet();
 	TAILQ_INSERT_TAIL(&sc->sc_txq, bf, bf_list);
 	if (sc->sc_txlink == NULL) {
-		ath_hal_put_tx_buf(ah, sc->sc_txhalq, bf->bf_daddr);
+		ath_hal_put_tx_buf(ah, sc->sc_txhalq[hwqueue], bf->bf_daddr);
 		DPRINTF(ATH_DEBUG_XMIT, ("%s: TXDP0 = %p (%p)\n", __func__,
 		    (caddr_t)bf->bf_daddr, bf->bf_desc));
 	} else {
@@ -2432,7 +2442,7 @@ ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
 	sc->sc_txlink = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
 	splx(s);
 
-	ath_hal_tx_start(ah, sc->sc_txhalq);
+	ath_hal_tx_start(ah, sc->sc_txhalq[hwqueue]);
 	return 0;
 }
 
@@ -2450,10 +2460,6 @@ ath_tx_proc(void *arg, int npending)
 	int sr, lr, s;
 	HAL_STATUS status;
 
-	DPRINTF(ATH_DEBUG_TX_PROC, ("%s: pending %u tx queue %p, "
-	    "link %p\n", __func__, npending,
-	    (caddr_t)(u_intptr_t) ath_hal_get_tx_buf(sc->sc_ah,
-	    sc->sc_txhalq), sc->sc_txlink));
 	for (;;) {
 		s = splnet();
 		bf = TAILQ_FIRST(&sc->sc_txq);
@@ -2536,19 +2542,21 @@ ath_draintxq(struct ath_softc *sc)
 	struct ifnet *ifp = &ic->ic_if;
 	struct ieee80211_node *ni;
 	struct ath_buf *bf;
-	int s;
+	int s, i;
 
 	/* XXX return value */
 	if (!sc->sc_invalid) {
-		/* don't touch the hardware if marked invalid */
-		(void) ath_hal_stop_tx_dma(ah, sc->sc_txhalq);
-		DPRINTF(ATH_DEBUG_RESET,
-		    ("%s: tx queue %p, link %p\n", __func__,
-		    (caddr_t)(u_intptr_t) ath_hal_get_tx_buf(ah, sc->sc_txhalq),
-		    sc->sc_txlink));
+		for (i = 0; i <= HAL_TX_QUEUE_ID_DATA_MAX; i++) {
+			/* don't touch the hardware if marked invalid */
+			(void) ath_hal_stop_tx_dma(ah, sc->sc_txhalq[i]);
+			DPRINTF(ATH_DEBUG_RESET,
+			    ("%s: tx queue %d (%p), link %p\n", __func__, i,
+			    (caddr_t)(u_intptr_t) ath_hal_get_tx_buf(ah, sc->sc_txhalq[i]),
+			    sc->sc_txlink));
+		}
 		(void) ath_hal_stop_tx_dma(ah, sc->sc_bhalq);
 		DPRINTF(ATH_DEBUG_RESET,
-		    ("%s: beacon queue %p\n", __func__,
+		    ("%s: beacon queue (%p)\n", __func__,
 		    (caddr_t)(u_intptr_t)ath_hal_get_tx_buf(ah, sc->sc_bhalq)));
 	}
 	for (;;) {
@@ -2690,6 +2698,7 @@ ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
 				ieee80211_chan2ieee(ic, chan), chan->ic_freq);
 			return EIO;
 		}
+		ath_set_slot_time(sc);
 		/*
 		 * Re-enable rx framework.
 		 */
@@ -2740,6 +2749,18 @@ ath_next_scan(void *arg)
 	splx(s);
 }
 
+int
+ath_set_slot_time(struct ath_softc *sc)
+{
+	struct ath_hal *ah = sc->sc_ah;
+	struct ieee80211com *ic = &sc->sc_ic;
+
+	if (ic->ic_flags & IEEE80211_F_SHSLOT)
+		return (ath_hal_set_slot_time(ah, HAL_SLOT_TIME_9));
+
+	return (0);
+}
+
 /*
  * Periodically recalibrate the PHY to account
  * for temperature/environment changes.
@@ -2774,7 +2795,7 @@ ath_calibrate(void *arg)
 		 * to load new gain values.
 		 */
 		sc->sc_stats.ast_per_rfgain++;
-		ath_reset(sc);
+		ath_reset(sc, 1);
 	}
 	if (!ath_hal_calibrate(ah, &hchan)) {
 		DPRINTF(ATH_DEBUG_ANY,
diff --git a/sys/dev/ic/athvar.h b/sys/dev/ic/athvar.h
index 7f86cc6bef6..f0f5d7119a8 100644
--- a/sys/dev/ic/athvar.h
+++ b/sys/dev/ic/athvar.h
@@ -1,4 +1,4 @@
-/*      $OpenBSD: athvar.h,v 1.12 2005/05/28 23:45:10 reyk Exp $  */
+/*      $OpenBSD: athvar.h,v 1.13 2005/07/30 17:13:17 reyk Exp $  */
 /*	$NetBSD: athvar.h,v 1.10 2004/08/10 01:03:53 dyoung Exp $	*/
 
 /*-
@@ -150,6 +150,7 @@ struct ath_rx_radiotap_header {
 	(1 << IEEE80211_RADIOTAP_CHANNEL)	| \
 	(1 << IEEE80211_RADIOTAP_DBM_TX_POWER)	| \
 	(1 << IEEE80211_RADIOTAP_ANTENNA)	| \
+	(1 << IEEE80211_RADIOTAP_HWQUEUE)	| \
 	0)
 
 struct ath_tx_radiotap_header {
@@ -160,6 +161,7 @@ struct ath_tx_radiotap_header {
 	u_int16_t	wt_chan_flags;
 	u_int8_t	wt_txpower;
 	u_int8_t	wt_antenna;
+	u_int8_t	wt_hwqueue;
 } __packed;
 
 /* 
@@ -273,7 +275,7 @@ struct ath_softc {
 	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
 	ath_task_t		sc_rxtask;	/* rx int processing */
 
-	u_int			sc_txhalq;	/* HAL q for outgoing frames */
+	u_int			sc_txhalq[HAL_NUM_TX_QUEUES];	/* HAL q for outgoing frames */
 	u_int32_t		*sc_txlink;	/* link ptr in last TX desc */
 	int			sc_tx_timer;	/* transmit timeout */
 	TAILQ_HEAD(, ath_buf)	sc_txbuf;	/* transmit buffer */
@@ -325,7 +327,6 @@ struct ath_softc {
 	 ((((u_int8_t *)(p))[0]      ) | (((u_int8_t *)(p))[1] <<  8) |	\
 	 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
 
-#define AR_DEBUG
 #ifdef AR_DEBUG
 enum {
 	ATH_DEBUG_XMIT		= 0x00000001,	/* basic xmit operation */
@@ -495,7 +496,8 @@ int	ath_enable(struct ath_softc *);
 	(*(_pcc) = (_ah)->ah_getcountrycode)
 #define	ath_hal_detach(_ah) \
 	((*(_ah)->ah_detach)(_ah))
-
+#define ath_hal_set_slot_time(_ah, _t) \
+	((*(_ah)->ah_set_slot_time)(_ah, _t))
 #define ath_hal_set_gpio_output(_ah, _gpio) \
 	((*(_ah)->ah_set_gpio_output)((_ah), (_gpio)))
 #define ath_hal_set_gpio_input(_ah, _gpio) \