real register definitions for the brooktree 451/457/458 on the cgsix and

cgthree.  ok miod.

3 files changed, 116 insertions, 31 deletions

diff --git a/sys/dev/ic/bt458reg.h b/sys/dev/ic/bt458reg.h
new file mode 100644
index 00000000000..645adb22ce2
--- /dev/null
+++ b/sys/dev/ic/bt458reg.h
@@ -0,0 +1,61 @@
+/*	$OpenBSD: bt458reg.h,v 1.1 2003/05/31 21:01:59 jason Exp $	*/
+
+/*
+ * Copyright (c) 2003 Jason L. Wright (jason@thought.net)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Brooktree Bt451, Bt457, Bt458 register definitions
+ */
+#define	BT_OV0	0x00		/* overlay 0 */
+#define	BT_OV1	0x01		/* overlay 1 */
+#define	BT_OV2	0x02		/* overlay 2 */
+#define	BT_OV3	0x03		/* overlay 3 */
+#define	BT_RMR	0x04		/* read mask */
+#define	BT_BMR	0x05		/* blink mask */
+#define	BT_CR	0x06		/* control */
+#define	BT_CTR	0x07		/* control/test */
+
+#define	BTCR_MPLX_5		0x80	/* multiplex select, 5:1 */
+#define	BTCR_MPLX_4		0x00	/* multiplex select, 4:1 */
+#define	BTCR_RAMENA		0x40	/* use color palette RAM */
+#define	BTCR_BLINK_M		0x30	/* blink mask */
+#define	BTCR_BLINK_1648		0x00	/*  16 on, 48 off */
+#define	BTCR_BLINK_1616		0x10	/*  16 on, 16 off */
+#define	BTCR_BLINK_3232		0x20	/*  32 on, 32 off */
+#define	BTCR_BLINK_6464		0x30	/*  64 on, 64 off */
+#define	BTCR_BLINKENA_OV1	0x08	/* OV1 blink enable */
+#define	BTCR_BLINKENA_OV0	0x04	/* OV0 blink enable */
+#define	BTCR_DISPENA_OV1	0x02	/* OV1 display enable */
+#define	BTCR_DISPENA_OV0	0x01	/* OV0 display enable */
+
+#define	BTCTR_R_ENA		0x01	/* red channel enable */
+#define	BTCTR_G_ENA		0x02	/* green channel enable */
+#define	BTCTR_B_ENA		0x04	/* blue channel enable */
+#define	BTCTR_NIB_M		0x08	/* nibble mask: */
+#define	BTCTR_NIB_LOW		0x08	/*  low */
+#define	BTCTR_NIB_HIGH		0x00	/*  high */
diff --git a/sys/dev/sbus/cgsix.c b/sys/dev/sbus/cgsix.c
index d5ebb8c8311..30010189562 100644
--- a/sys/dev/sbus/cgsix.c
+++ b/sys/dev/sbus/cgsix.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cgsix.c,v 1.39 2003/03/28 15:03:41 jason Exp $	*/
+/*	$OpenBSD: cgsix.c,v 1.40 2003/05/31 21:01:59 jason Exp $	*/
 
 /*
  * Copyright (c) 2001 Jason L. Wright (jason@thought.net)
@@ -55,6 +55,7 @@
 #include <dev/wscons/wscons_raster.h>
 #include <dev/rasops/rasops.h>
 #include <dev/sbus/cgsixreg.h>
+#include <dev/ic/bt458reg.h>
 
 struct wsscreen_descr cgsix_stdscreen = {
 	"std",
@@ -529,15 +530,21 @@ int
 cgsix_updatecursor(struct cgsix_softc *sc, u_int which)
 {
 	if (which & WSDISPLAY_CURSOR_DOCMAP) {
-		BT_WRITE(sc, BT_ADDR, 1 << 24);
-		BT_WRITE(sc, BT_OMAP, ((sc->sc_curs_fg & 0x00ff0000)>> 16) << 24);
-		BT_WRITE(sc, BT_OMAP, ((sc->sc_curs_fg & 0x0000ff00)>> 8) << 24);
-		BT_WRITE(sc, BT_OMAP, ((sc->sc_curs_fg & 0x000000ff)>> 0) << 24);
-
-		BT_WRITE(sc, BT_ADDR, 3 << 24);
-		BT_WRITE(sc, BT_OMAP, ((sc->sc_curs_bg & 0x00ff0000)>> 16) << 24);
-		BT_WRITE(sc, BT_OMAP, ((sc->sc_curs_bg & 0x0000ff00)>> 8) << 24);
-		BT_WRITE(sc, BT_OMAP, ((sc->sc_curs_bg & 0x000000ff)>> 0) << 24);
+		BT_WRITE(sc, BT_ADDR, BT_OV1 << 24);
+		BT_WRITE(sc, BT_OMAP,
+		    ((sc->sc_curs_fg & 0x00ff0000) >> 16) << 24);
+		BT_WRITE(sc, BT_OMAP,
+		    ((sc->sc_curs_fg & 0x0000ff00) >> 8) << 24);
+		BT_WRITE(sc, BT_OMAP,
+		    ((sc->sc_curs_fg & 0x000000ff) >> 0) << 24);
+
+		BT_WRITE(sc, BT_ADDR, BT_OV3 << 24);
+		BT_WRITE(sc, BT_OMAP,
+		    ((sc->sc_curs_bg & 0x00ff0000) >> 16) << 24);
+		BT_WRITE(sc, BT_OMAP,
+		    ((sc->sc_curs_bg & 0x0000ff00) >> 8) << 24);
+		BT_WRITE(sc, BT_OMAP,
+		    ((sc->sc_curs_bg & 0x000000ff) >> 0) << 24);
 	}
 
 	if (which & (WSDISPLAY_CURSOR_DOPOS | WSDISPLAY_CURSOR_DOHOT)) {
@@ -552,15 +559,16 @@ cgsix_updatecursor(struct cgsix_softc *sc, u_int which)
 	if (which & WSDISPLAY_CURSOR_DOCUR) {
 		u_int32_t c;
 
+		/* Enable or disable the cursor overlay planes */
 		if (sc->sc_curs_enabled) {
-			BT_WRITE(sc, BT_ADDR, 6 << 24);
+			BT_WRITE(sc, BT_ADDR, BT_CR << 24);
 			c = BT_READ(sc, BT_CTRL);
-			c |= 3 << 24;
+			c |= (BTCR_DISPENA_OV0 | BTCR_DISPENA_OV1) << 24;
 			BT_WRITE(sc, BT_CTRL, c);
 		} else {
-			BT_WRITE(sc, BT_ADDR, 6 << 24);
+			BT_WRITE(sc, BT_ADDR, BT_CR << 24);
 			c = BT_READ(sc, BT_CTRL);
-			c &= ~(3 << 24);
+			c &= ~((BTCR_DISPENA_OV0 | BTCR_DISPENA_OV1) << 24);
 			BT_WRITE(sc, BT_CTRL, c);
 			THC_WRITE(sc, CG6_THC_CURSXY, THC_CURSOFF);
 		}
@@ -821,9 +829,10 @@ cgsix_reset(sc, fhcrev)
 		FHC_WRITE(sc, fhc);
 	}
 
-	/* enable cursor in brooktree DAC */
-	BT_WRITE(sc, BT_ADDR, 0x6 << 24);
-	BT_WRITE(sc, BT_CTRL, BT_READ(sc, BT_CTRL) | (0x3 << 24));
+	/* enable cursor overlays in brooktree DAC */
+	BT_WRITE(sc, BT_ADDR, BT_CR << 24);
+	BT_WRITE(sc, BT_CTRL, BT_READ(sc, BT_CTRL) |
+	    ((BTCR_DISPENA_OV1 | BTCR_DISPENA_OV0) << 24));
 }
 
 void
@@ -832,28 +841,34 @@ cgsix_hardreset(sc)
 {
 	u_int32_t fhc, rev;
 
-	/* setup brooktree */
-	BT_WRITE(sc, BT_ADDR, 0x04 << 24);
+	/* enable all of the bit planes */
+	BT_WRITE(sc, BT_ADDR, BT_RMR << 24);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
 	BT_WRITE(sc, BT_CTRL, 0xff << 24);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 
-	BT_WRITE(sc, BT_ADDR, 0x05 << 24);
+	/* no bit planes should blink */
+	BT_WRITE(sc, BT_ADDR, BT_BMR << 24);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
 	BT_WRITE(sc, BT_CTRL, 0x00 << 24);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 
-	BT_WRITE(sc, BT_ADDR, 0x06 << 24);
+	/*
+	 * enable the RAMDAC, disable blink, disable overlay 0 and 1,
+	 * use 4:1 multiplexor.
+	 */
+	BT_WRITE(sc, BT_ADDR, BT_CR << 24);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
-	BT_WRITE(sc, BT_CTRL, 0x70 << 24);
+	BT_WRITE(sc, BT_CTRL,
+	    (BTCR_MPLX_4 | BTCR_RAMENA | BTCR_BLINK_6464) << 24);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 
-	BT_WRITE(sc, BT_ADDR, 0x07 << 24);
+	/* disable the D/A read pins */
+	BT_WRITE(sc, BT_ADDR, BT_CTR << 24);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
 	BT_WRITE(sc, BT_CTRL, 0x00 << 24);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 
-
 	/* configure thc */
 	THC_WRITE(sc, CG6_THC_MISC, THC_MISC_RESET | THC_MISC_INTR |
 	    THC_MISC_CYCLS);
diff --git a/sys/dev/sbus/cgthree.c b/sys/dev/sbus/cgthree.c
index e70f0344b59..37a34a50b56 100644
--- a/sys/dev/sbus/cgthree.c
+++ b/sys/dev/sbus/cgthree.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cgthree.c,v 1.28 2003/03/28 03:18:03 jason Exp $	*/
+/*	$OpenBSD: cgthree.c,v 1.29 2003/05/31 21:01:59 jason Exp $	*/
 
 /*
  * Copyright (c) 2001 Jason L. Wright (jason@thought.net)
@@ -54,6 +54,7 @@
 #include <dev/wscons/wsdisplayvar.h>
 #include <dev/wscons/wscons_raster.h>
 #include <dev/rasops/rasops.h>
+#include <dev/ic/bt458reg.h>
 
 #define	CGTHREE_CTRL_OFFSET	0x400000
 #define	CGTHREE_CTRL_SIZE	(sizeof(u_int32_t) * 8)
@@ -618,24 +619,32 @@ cgthree_reset(sc)
 		}
 	}
 
-	BT_WRITE(sc, BT_ADDR, 0x04);
+	/* enable all the bit planes */
+	BT_WRITE(sc, BT_ADDR, BT_RMR);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
 	BT_WRITE(sc, BT_CTRL, 0xff);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 
-	BT_WRITE(sc, BT_ADDR, 0x05);
+	/* no plane should blink */
+	BT_WRITE(sc, BT_ADDR, BT_BMR);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
 	BT_WRITE(sc, BT_CTRL, 0x00);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 
-	BT_WRITE(sc, BT_ADDR, 0x06);
+	/*
+	 * enable the RAMDAC, disable blink, disable overlay 0 and 1,
+	 * use 4:1 multiplexor.
+	 */
+	BT_WRITE(sc, BT_ADDR, BT_CR);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
-	BT_WRITE(sc, BT_CTRL, 0x70);
+	BT_WRITE(sc, BT_CTRL,
+	    (BTCR_MPLX_4 | BTCR_RAMENA | BTCR_BLINK_6464) << 24);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 
-	BT_WRITE(sc, BT_ADDR, 0x07);
+	/* disable the D/A read pins */
+	BT_WRITE(sc, BT_ADDR, BT_CTR << 24);
 	BT_BARRIER(sc, BT_ADDR, BUS_SPACE_BARRIER_WRITE);
-	BT_WRITE(sc, BT_CTRL, 0x00);
+	BT_WRITE(sc, BT_CTRL, 0x00 << 24);
 	BT_BARRIER(sc, BT_CTRL, BUS_SPACE_BARRIER_WRITE);
 }