sync i915_gem_object_fence_ok with linux

3 files changed, 39 insertions, 20 deletions

diff --git a/sys/dev/pci/drm/i915_drv.h b/sys/dev/pci/drm/i915_drv.h
index 71c1b716e0d..5d6b81839b5 100644
--- a/sys/dev/pci/drm/i915_drv.h
+++ b/sys/dev/pci/drm/i915_drv.h
@@ -1164,7 +1164,7 @@ void	i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *);
 void	i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *);
 int	i915_gem_swizzle_page(struct vm_page *page);
 int	i915_tiling_ok(struct drm_device *, int, int, int);
-int	i915_gem_object_fence_ok(struct drm_obj *, int);
+bool	i915_gem_object_fence_ok(struct drm_i915_gem_object *, int);
 
 /* i915_suspend.c */
 
diff --git a/sys/dev/pci/drm/i915_gem.c b/sys/dev/pci/drm/i915_gem.c
index 188a834eb9f..f482385335b 100644
--- a/sys/dev/pci/drm/i915_gem.c
+++ b/sys/dev/pci/drm/i915_gem.c
@@ -595,7 +595,7 @@ i915_gem_fault(struct drm_obj *gem_obj, struct uvm_faultinfo *ufi,
 
 	if (obj->dmamap != NULL &&
 	    (obj->gtt_offset & (i915_gem_get_gtt_alignment(&obj->base) - 1) ||
-	    (!i915_gem_object_fence_ok(&obj->base, obj->tiling_mode)))) {
+	    (!i915_gem_object_fence_ok(obj, obj->tiling_mode)))) {
 		/*
 		 * pinned objects are defined to have a sane alignment which can
 		 * not change.
@@ -2187,7 +2187,7 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
 	if (obj->dmamap != NULL &&
 	    ((alignment && obj->gtt_offset & (alignment - 1)) ||
 	    obj->gtt_offset & (i915_gem_get_gtt_alignment(&obj->base) - 1) ||
-	    !i915_gem_object_fence_ok(&obj->base, obj->tiling_mode))) {
+	    !i915_gem_object_fence_ok(obj, obj->tiling_mode))) {
 		/* if it is already pinned we sanitised the alignment then */
 		KASSERT(obj->pin_count == 0);
 		if ((ret = i915_gem_object_unbind(obj)))
diff --git a/sys/dev/pci/drm/i915_gem_tiling.c b/sys/dev/pci/drm/i915_gem_tiling.c
index 8a23d1506ad..7360e28c890 100644
--- a/sys/dev/pci/drm/i915_gem_tiling.c
+++ b/sys/dev/pci/drm/i915_gem_tiling.c
@@ -275,27 +275,46 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
 	return (1);
 }
 
-int
-i915_gem_object_fence_ok(struct drm_obj *obj, int tiling_mode)
+bool
+i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
 {
-	struct drm_device	*dev = obj->dev;
-	struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
+	u32 size;
 
-	if (obj_priv->dmamap == NULL || tiling_mode == I915_TILING_NONE)
-		return (1);
+	if (tiling_mode == I915_TILING_NONE)
+		return true;
 
-	if (INTEL_INFO(dev)->gen < 4) {
-		if (obj_priv->gtt_offset & (obj->size -1))
-			return (0);
-		if (IS_I9XX(dev)) {
-			if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
-				return (0);
-		} else {
-			if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
-				return (0);
-		}
+	if (INTEL_INFO(obj->base.dev)->gen >= 4)
+		return true;
+
+	if (INTEL_INFO(obj->base.dev)->gen == 3) {
+		if (obj->gtt_offset & ~I915_FENCE_START_MASK)
+			return false;
+	} else {
+		if (obj->gtt_offset & ~I830_FENCE_START_MASK)
+			return false;
 	}
-	return (1);
+
+	/*
+	 * Previous chips need to be aligned to the size of the smallest
+	 * fence register that can contain the object.
+	 */
+	if (INTEL_INFO(obj->base.dev)->gen == 3)
+		size = 1024*1024;
+	else
+		size = 512*1024;
+
+	while (size < obj->base.size)
+		size <<= 1;
+
+#if 0
+	if (obj->gtt_space->size != size)
+		return false;
+#endif
+
+	if (obj->gtt_offset & (size - 1))
+		return false;
+
+	return true;
 }
 
 /**