Add support for the hardware random number generator on the octeons.

Works on my DSR-500 and on the edge router as reported on the mailing lists.

Finished sometime in August/September, needs more testing/polishing.

Similar diff from William Orr on tech@.
Prodded by deraadt@, okay jasper@.

3 files changed, 123 insertions, 4 deletions

diff --git a/sys/arch/octeon/dev/octeon_iobus.c b/sys/arch/octeon/dev/octeon_iobus.c
index 65bcbb099dc..8c65d987b7d 100644
--- a/sys/arch/octeon/dev/octeon_iobus.c
+++ b/sys/arch/octeon/dev/octeon_iobus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octeon_iobus.c,v 1.4 2013/06/02 20:29:36 jasper Exp $ */
+/*	$OpenBSD: octeon_iobus.c,v 1.5 2013/10/24 20:45:03 pirofti Exp $ */
 
 /*
  * Copyright (c) 2000-2004 Opsycon AB  (www.opsycon.se)
@@ -154,12 +154,14 @@ struct machine_bus_dma_tag iobus_bus_dma_tag = {
 const struct iobus_unit iobus_units[] = {
 	{ OCTEON_CF_BASE, 0 },			/* octcf */
 	{ 0, 0 },				/* pcibus */
-	{ GMX0_BASE_PORT0, CIU_INT_GMX_DRP0 }	/* cn30xxgmx */
+	{ GMX0_BASE_PORT0, CIU_INT_GMX_DRP0 },	/* cn30xxgmx */
+	{ OCTEON_RNG_BASE, 0 },			/* octrng */
 };
 struct iobus_attach_args iobus_children[] = {
 	IOBUSDEV("octcf", 0, &iobus_units[0]),
 	IOBUSDEV("pcibus", 0, &iobus_units[1]),
-	IOBUSDEV("cn30xxgmx", 0, &iobus_units[2])
+	IOBUSDEV("cn30xxgmx", 0, &iobus_units[2]),
+	IOBUSDEV("octrng", 0, &iobus_units[3])
 };
 #undef	IOBUSDEV
 
diff --git a/sys/arch/octeon/dev/octrng.c b/sys/arch/octeon/dev/octrng.c
new file mode 100644
index 00000000000..98a3aa4bc43
--- /dev/null
+++ b/sys/arch/octeon/dev/octrng.c
@@ -0,0 +1,116 @@
+/*	$OpenBSD: octrng.c,v 1.1 2013/10/24 20:45:03 pirofti Exp $	*/
+/*
+ * Copyright (c) 2013 Paul Irofti <pirofti@openbsd.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/timeout.h>
+
+#include <dev/rndvar.h>
+
+#include <machine/octeonvar.h>
+#include <machine/octeonreg.h>
+#include <octeon/dev/iobusvar.h>
+
+int	octrng_match(struct device *, void *, void *);
+void	octrng_attach(struct device *, struct device *, void *);
+void	octrng_rnd(void *arg);
+
+#define OCTRNG_DEBUG
+#ifdef OCTRNG_DEBUG
+#define DPRINTF(x)	printf x
+#else
+#define DPRINTF(x)
+#endif
+
+#define OCTRNG_MAP_SIZE 8ULL
+
+/* OCTRNG_ENTROPY_ADDR 0x8001400000000000ULL */
+#define OCTRNG_MAJORDID 8ULL
+#define OCTRNG_ENTROPY_ADDR (((uint64_t)1 << 48) | \
+		((uint64_t)(OCTRNG_MAJORDID & 0x1f) << 43))
+#define OCTRNG_ENTROPY_REG	0
+
+#define OCTRNG_CONTROL_ADDR 0x0001180040000000ULL
+
+#define OCTRNG_RESET (1ULL << 60)
+#define OCTRNG_ENABLE_OUTPUT (1ULL << 62)
+#define OCTRNG_ENABLE_ENTROPY (1ULL << 63)
+
+struct octrng_softc {
+	struct device sc_dev;
+	struct timeout sc_to;
+	struct iobus_attach_args *sc_io;
+
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+};
+
+struct cfattach octrng_ca = {
+	sizeof(struct octrng_softc), octrng_match, octrng_attach
+};
+
+struct cfdriver octrng_cd = {
+	NULL, "octrng", DV_DULL
+};
+
+int
+octrng_match(struct device *parent, void *match, void *aux)
+{
+	/* XXX: check for board type */
+	return (1);
+}
+
+void
+octrng_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct octrng_softc *sc = (void *)self;
+	sc->sc_io = aux;
+
+	uint64_t control_reg;
+
+	sc->sc_iot = sc->sc_io->aa_bust;
+
+	if (bus_space_map(sc->sc_iot, OCTEON_RNG_BASE, OCTRNG_MAP_SIZE, 0,
+	    &sc->sc_ioh)) {
+		printf(": can't map registers");
+	}
+
+ 	control_reg = octeon_xkphys_read_8(OCTRNG_CONTROL_ADDR);
+	control_reg |= (OCTRNG_ENABLE_OUTPUT | OCTRNG_ENABLE_ENTROPY);
+	octeon_xkphys_write_8(OCTRNG_CONTROL_ADDR, control_reg);
+
+	timeout_set(&sc->sc_to, octrng_rnd, sc);
+
+	timeout_add_sec(&sc->sc_to, 5);
+
+	printf("\n");
+}
+
+void
+octrng_rnd(void *arg)
+{
+	struct octrng_softc *sc = arg;
+	uint64_t value;
+
+	value = bus_space_read_8(sc->sc_iot, sc->sc_ioh, OCTRNG_ENTROPY_REG);
+
+ 	DPRINTF(("%#llX ", value));	/* WARNING: very verbose */
+
+ 	add_true_randomness(value);
+	timeout_add_msec(&sc->sc_to, 10);
+}
diff --git a/sys/arch/octeon/include/octeonreg.h b/sys/arch/octeon/include/octeonreg.h
index d490f134fa7..fab692cf753 100644
--- a/sys/arch/octeon/include/octeonreg.h
+++ b/sys/arch/octeon/include/octeonreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: octeonreg.h,v 1.2 2013/06/09 20:20:11 deraadt Exp $	*/
+/*	$OpenBSD: octeonreg.h,v 1.3 2013/10/24 20:45:03 pirofti Exp $	*/
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com).
@@ -35,6 +35,7 @@
 #define OCTEON_MIO_BOOT_BASE	0x1180000000000ULL
 #define OCTEON_UART0_BASE	0x1180000000800ULL
 #define OCTEON_UART1_BASE	0x1180000000C00ULL
+#define OCTEON_RNG_BASE		0x1400000000000ULL
 
 #define MIO_BOOT_REG_CFG0	0x0
 #define MIO_BOOT_REG_CFG(x)	(MIO_BOOT_REG_CFG0+((x)*8))