diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2016-05-16 15:13:51 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2016-05-16 15:13:51 +0000 |
| commit | 1846c0f2c58becf59288e3ac719fa1d1f3efcfdf (patch) | |
| tree | 411e103badbc992edb9f2735f5be12bc5afdd1a5 /sys | |
| parent | 4a373f94f09b88f998a5d4198ddf52d6d913bd8a (diff) | |
POSTREAD needs to flush the D-cache since speculative loads might (and do)
bring back cache lines after a PREREAD. Eliminates random data corruption
on my CuBox-i4Pro.
ok jsg@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/arm/arm/bus_dma.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/sys/arch/arm/arm/bus_dma.c b/sys/arch/arm/arm/bus_dma.c index 4290e5406b1..cdd7c21282b 100644 --- a/sys/arch/arm/arm/bus_dma.c +++ b/sys/arch/arm/arm/bus_dma.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bus_dma.c,v 1.29 2016/03/10 10:22:43 tobiasu Exp $ */ +/* $OpenBSD: bus_dma.c,v 1.30 2016/05/16 15:13:50 kettenis Exp $ */ /* $NetBSD: bus_dma.c,v 1.38 2003/10/30 08:44:13 scw Exp $ */ /*- @@ -421,6 +421,19 @@ _bus_dmamap_sync_segment(vaddr_t va, paddr_t pa, vsize_t len, int ops) cpu_dcache_wb_range(va, len); cpu_sdcache_wb_range(va, pa, len); break; + + /* + * Cortex CPUs can do speculative loads so we need to clean the cache + * after a DMA read to deal with any speculatively loaded cache lines. + * Since these can't be dirty, we can just invalidate them and don't + * have to worry about having to write back their contents. + */ + case BUS_DMASYNC_POSTREAD: + case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE: + membar_sync(); + cpu_dcache_inv_range(va, len); + cpu_sdcache_inv_range(va, pa, len); + break; } } |