diff options
| author | Jonathan Matthew <jmatthew@cvs.openbsd.org> | 2019-01-19 00:08:11 +0000 |
|---|---|---|
| committer | Jonathan Matthew <jmatthew@cvs.openbsd.org> | 2019-01-19 00:08:11 +0000 |
| commit | 1a8419e975acf565c1779c52042e49539be9848d (patch) | |
| tree | cd994d3fe47e01e1d78ec6a20e4983968d1af807 /sys | |
| parent | 4f85abcb1d3940615dafd0c0a3f37c8daf703044 (diff) | |
actually set CAUSE_ENA on the rx and tx queues, and re-enable interrupts
at the start of the interrupt handler. now it works well enough to commit
over.
ok dlg@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/pci/if_ixl.c | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/sys/dev/pci/if_ixl.c b/sys/dev/pci/if_ixl.c index cc845777d8c..80a40956126 100644 --- a/sys/dev/pci/if_ixl.c +++ b/sys/dev/pci/if_ixl.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_ixl.c,v 1.9 2019/01/18 23:14:44 jmatthew Exp $ */ +/* $OpenBSD: if_ixl.c,v 1.10 2019/01/19 00:08:10 jmatthew Exp $ */ /* * Copyright (c) 2013-2015, Intel Corporation @@ -1781,16 +1781,6 @@ ixl_up(struct ixl_softc *sc) SET(ifp->if_flags, IFF_RUNNING); -#if 0 - reg = ixl_rd(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE)); - SET(reg, I40E_QINT_RQCTL_CAUSE_ENA_MASK); - ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg); - - reg = ixl_rd(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE)); - SET(reg, I40E_QINT_TQCTL_CAUSE_ENA_MASK); - ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg); -#endif - ixl_wr(sc, I40E_PFINT_LNKLST0, (I40E_INTR_NOTX_QUEUE << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | (I40E_QUEUE_TYPE_RX << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); @@ -1800,14 +1790,16 @@ ixl_up(struct ixl_softc *sc) (I40E_ITR_INDEX_RX << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | (I40E_INTR_NOTX_RX_QUEUE << I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | (I40E_INTR_NOTX_QUEUE << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | - (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)); + (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | + I40E_QINT_RQCTL_CAUSE_ENA_MASK); ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), (I40E_INTR_NOTX_INTR << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | (I40E_ITR_INDEX_TX << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | (I40E_INTR_NOTX_TX_QUEUE << I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | (I40E_QUEUE_TYPE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | - (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)); + (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | + I40E_QINT_TQCTL_CAUSE_ENA_MASK); ixl_wr(sc, I40E_PFINT_ITR0(0), 0x7a); ixl_wr(sc, I40E_PFINT_ITR0(1), 0x7a); @@ -2702,6 +2694,7 @@ ixl_intr(void *xsc) uint32_t icr; int rv = 0; + ixl_intr_enable(sc); icr = ixl_rd(sc, I40E_PFINT_ICR0); if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { |