diff options
| author | Mike Larkin <mlarkin@cvs.openbsd.org> | 2017-08-09 21:23:39 +0000 |
|---|---|---|
| committer | Mike Larkin <mlarkin@cvs.openbsd.org> | 2017-08-09 21:23:39 +0000 |
| commit | 32ed9d4b9bb46deb85a09a36eae3a66d3af8f0fe (patch) | |
| tree | ee67804a28403dc4496d94caa4cf4b90b2f9ca21 /sys | |
| parent | 159ef2f3faefcfbdeb646aa8cdc7325945cc9a31 (diff) | |
Add IA32_MISC_ENABLE MSR and bitfield values, to be used shortly by
vmm(4)
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 25 | ||||
| -rw-r--r-- | sys/arch/i386/include/specialreg.h | 23 |
2 files changed, 46 insertions, 2 deletions
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 3556c9d383d..3dca06fe763 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.59 2017/08/09 20:22:08 mlarkin Exp $ */ +/* $OpenBSD: specialreg.h,v 1.60 2017/08/09 21:23:38 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -354,6 +354,29 @@ #define MSR_THERM_STATUS_VALID_BIT 0x80000000 #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f) #define MSR_THERM2_CTL 0x19d /* Pentium M */ +#define MSR_MISC_ENABLE 0x1a0 +/* + * MSR_MISC_ENABLE (0x1a0) + * + * Enable Fast Strings: enables fast REP MOVS/REP STORS (R/W) + * Enable TCC: Enable automatic thermal control circuit (R/W) + * Performance monitoring available: 1 if enabled (R/O) + * Branch trace storage unavailable: 1 if unsupported (R/O) + * Processor event based sampling unavailable: 1 if unsupported (R/O) + * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W) + * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W) + */ +#define MISC_ENABLE_FAST_STRINGS (1 << 0) +#define MISC_ENABLE_TCC (1 << 3) +#define MISC_ENABLE_PERF_MON_AVAILABLE (1 << 7) +#define MISC_ENABLE_BTS_UNAVAILABLE (1 << 11) +#define MISC_ENABLE_PEBS_UNAVAILABLE (1 << 12) +#define MISC_ENABLE_EIST_ENABLED (1 << 16) +#define MISC_ENABLE_ENABLE_MONITOR_FSM (1 << 18) +#define MISC_ENABLE_LIMIT_CPUID_MAXVAL (1 << 22) +#define MISC_ENABLE_xTPR_MESSAGE_DISABLE (1 << 23) +#define MISC_ENABLE_XD_BIT_DISABLE (1 << 34) + /* * for Core i Series and newer Xeons, see * http://www.intel.com/content/dam/www/public/us/en/ diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index 156be1dc35e..07b312a625e 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.62 2017/08/09 20:23:55 mlarkin Exp $ */ +/* $OpenBSD: specialreg.h,v 1.63 2017/08/09 21:23:38 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -349,6 +349,27 @@ #define MSR_THERM2_CTL 0x19d /* Pentium M */ #define MSR_MISC_ENABLE 0x1a0 /* + * MSR_MISC_ENABLE (0x1a0) + * + * Enable Fast Strings: enables fast REP MOVS/REP STORS (R/W) + * Enable TCC: Enable automatic thermal control circuit (R/W) + * Performance monitoring available: 1 if enabled (R/O) + * Branch trace storage unavailable: 1 if unsupported (R/O) + * Processor event based sampling unavailable: 1 if unsupported (R/O) + * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W) + * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W) + */ +#define MISC_ENABLE_FAST_STRINGS (1 << 0) +#define MISC_ENABLE_TCC (1 << 3) +#define MISC_ENABLE_PERF_MON_AVAILABLE (1 << 7) +#define MISC_ENABLE_BTS_UNAVAILABLE (1 << 11) +#define MISC_ENABLE_PEBS_UNAVAILABLE (1 << 12) +#define MISC_ENABLE_EIST_ENABLED (1 << 16) +#define MISC_ENABLE_ENABLE_MONITOR_FSM (1 << 18) +#define MISC_ENABLE_LIMIT_CPUID_MAXVAL (1 << 22) +#define MISC_ENABLE_xTPR_MESSAGE_DISABLE (1 << 23) +#define MISC_ENABLE_XD_BIT_DISABLE (1 << 34) +/* * for Core i Series and newer Xeons, see * http://www.intel.com/content/dam/www/public/us/en/ * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf |