Always force a pipeline flush after a PSR change, not before. How could

this have ever worked?

4 files changed, 17 insertions, 23 deletions

diff --git a/sys/arch/mvme88k/mvme88k/eh.S b/sys/arch/mvme88k/mvme88k/eh.S
index f0637af7eb6..294a28c4e43 100644
--- a/sys/arch/mvme88k/mvme88k/eh.S
+++ b/sys/arch/mvme88k/mvme88k/eh.S
@@ -1,4 +1,4 @@
-/*   $OpenBSD: eh.S,v 1.31 2003/08/11 20:45:17 miod Exp $   */
+/*   $OpenBSD: eh.S,v 1.32 2003/08/13 08:52:44 miod Exp $   */
 /*
  * Mach Operating System
  * Copyright (c) 1993-1991 Carnegie Mellon University
@@ -1017,8 +1017,8 @@ GLOBAL(badaddr)
 	 */
 	ldcr	r8, PSR
 	set	r4, r8, 1<PSR_INTERRUPT_DISABLE_BIT>
-	FLUSH_PIPELINE
 	stcr	r4, PSR
+	FLUSH_PIPELINE
 
 	ldcr	r5, SR1
 	set	r5, r5, 1<FLAG_IGNORE_DATA_EXCEPTION>
@@ -1103,8 +1103,8 @@ ASGLOBAL(badaddr__return)
 	 * we do not want to turn them on now, so we just restore from
 	 * where we saved it.
 	 */
-	FLUSH_PIPELINE
 	stcr	r8, PSR
+	FLUSH_PIPELINE
 	jmp	r1
 
 ASLOCAL(m88110_badaddr__return_nonzero)
@@ -1873,9 +1873,7 @@ ASLOCAL(fpu_enable)
 	 ldcr	r2,   PSR
 	clr	r2,   r2,   1<PSR_INTERRUPT_DISABLE_BIT>
 	stcr	r2,   PSR
-#ifdef DDB
 	FLUSH_PIPELINE
-#endif
 
 	/* service any outstanding data pipeline stuff
 	   - check dmt0 anything outstanding? */
@@ -2004,8 +2002,8 @@ ASLOCAL(return_from_exception_handler)
         bb1	PSR_INTERRUPT_DISABLE_BIT, r2, 1f	/* skip if disabled */
 	ldcr	r2, PSR
 	clr	r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT>	/* enable interrupts */
-	FLUSH_PIPELINE
         stcr	r2, PSR
+	FLUSH_PIPELINE
 1:
 	ld	r2, FPTR, REG_OFF(EF_DMT0)
 	bb0	DMT_VALID_BIT, r2, 2f
@@ -2047,8 +2045,8 @@ ASLOCAL(m88110_return_code)
 	bb1	PSR_INTERRUPT_DISABLE_BIT, r2, 1f	/* skip if disabled */
 	ldcr	r2, PSR
 	clr	r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT>	/* enable interrupts */
-	FLUSH_PIPELINE
 	stcr	r2, PSR
+	FLUSH_PIPELINE
 1:
 	br	2f	/* temp XXX smurph */
 	ld	r2, FPTR, REG_OFF(EF_VECTOR)
@@ -2125,8 +2123,8 @@ ASLOCAL(no_ast)
 	/* disable interrupts */
 	ldcr	r1, PSR
 	set	r1, r1, 1<PSR_INTERRUPT_DISABLE_BIT>
-	FLUSH_PIPELINE
 	stcr	r1, PSR
+	FLUSH_PIPELINE
 
 	/* now ready to return....*/
 	subu	r31, r31, 40
@@ -2159,8 +2157,8 @@ ASLOCAL(no_ast)
 	/* disable shadowing */
 	ldcr	r1, PSR
 	set	r1, r1, 1<PSR_SHADOW_FREEZE_BIT>
-	FLUSH_PIPELINE
 	stcr	r1, PSR
+	FLUSH_PIPELINE
 
 	/* reload the control regs*/
 #ifdef M88110
@@ -2964,9 +2962,7 @@ ASLOCAL(m88110_fpu_enable)
 	 ldcr	r2,   PSR
 	clr	r2,   r2,   1<PSR_INTERRUPT_DISABLE_BIT>
 	stcr	r2,   PSR
-#ifdef DDB
 	FLUSH_PIPELINE
-#endif
 #if 1 /* XXX test */
 	br	8f
 #else
diff --git a/sys/arch/mvme88k/mvme88k/locore.S b/sys/arch/mvme88k/mvme88k/locore.S
index 78a03963c13..56f9693d9c2 100644
--- a/sys/arch/mvme88k/mvme88k/locore.S
+++ b/sys/arch/mvme88k/mvme88k/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.28 2003/08/11 20:45:17 miod Exp $	*/
+/*	$OpenBSD: locore.S,v 1.29 2003/08/13 08:52:44 miod Exp $	*/
 /*
  * Copyright (c) 1998 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -215,6 +215,7 @@ GLOBAL(start_text)
 /*	set	r11, r11, 1<PSR_SERIAL_MODE_BIT> */
 	set	r11, r11, 1<PSR_SERIALIZE_BIT>
 	stcr	r11, PSR
+	FLUSH_PIPELINE
 	stcr	r0,  VBR	/* set Vector Base Register to 0, ALWAYS! */
 	FLUSH_PIPELINE
 	cmp	r2, r8, CPU_88110	/* r8 contains cputyp */
diff --git a/sys/arch/mvme88k/mvme88k/locore_asm_routines.S b/sys/arch/mvme88k/mvme88k/locore_asm_routines.S
index 7fa7de1c04a..b2340bcc6b0 100644
--- a/sys/arch/mvme88k/mvme88k/locore_asm_routines.S
+++ b/sys/arch/mvme88k/mvme88k/locore_asm_routines.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore_asm_routines.S,v 1.23 2003/08/11 20:45:17 miod Exp $	*/
+/* $OpenBSD: locore_asm_routines.S,v 1.24 2003/08/13 08:52:44 miod Exp $	*/
 /*
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
@@ -1631,6 +1631,7 @@ ENTRY(set_cpu_number)
 	ldcr	r4, PSR
 	set	r5, r4, 1<PSR_INTERRUPT_DISABLE_BIT>
 	stcr	r5, PSR
+	FLUSH_PIPELINE
 	tcnd	ne0,r0,10 /* make sure interrupts are really disabled */
 			  /* if they are not, branch to error_handler() */
 	/* put in the cpu number */
@@ -1641,6 +1642,7 @@ ENTRY(set_cpu_number)
 
 	/* put back the PSR to what it was before and return */
 	stcr	r4, PSR
+	FLUSH_PIPELINE
 	jmp	r1
 
 1:	/* bad cpu number*/
diff --git a/sys/arch/mvme88k/mvme88k/process.S b/sys/arch/mvme88k/mvme88k/process.S
index ae81e62b9ab..d90e7335668 100644
--- a/sys/arch/mvme88k/mvme88k/process.S
+++ b/sys/arch/mvme88k/mvme88k/process.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: process.S,v 1.20 2003/08/12 18:06:48 miod Exp $	*/
+/*	$OpenBSD: process.S,v 1.21 2003/08/13 08:52:44 miod Exp $	*/
 /*
  * Copyright (c) 1996 Nivas Madhur
  * All rights reserved.
@@ -87,8 +87,7 @@ ENTRY(switch_exit)
 	bsr.n	_C_LABEL(exit2)
 	 subu	r31, r31, 48		/* allocate stack  */
 	addu	r31, r31, 48		/* restore stack */
-	bsr.n	_C_LABEL(cpu_switch)	/* goto final switch */
-	 or	r2, r0, r10
+	bsr	_C_LABEL(cpu_switch)	/* goto final switch */
 
 /*
  * cpu_switch()
@@ -104,7 +103,7 @@ ENTRY(cpu_switch)
 
 	or.u	r10, r0, hi16(_C_LABEL(curpcb))
 	ld	r10,r10, lo16(_C_LABEL(curpcb))
-	st	r1, r10, PCB_PC		/*  save r1 in pcb */
+	st	r1, r10, PCB_PC
 	st	r14,r10, PCB_R14
 	st	r15,r10, PCB_R15
 	st	r16,r10, PCB_R16
@@ -126,13 +125,9 @@ ENTRY(cpu_switch)
 
 	bsr.n	_C_LABEL(getipl)
 	 or	r14,r10, 0		/* save r10 in r14 */
-
 	st	r2, r14, PCB_IPL	/* save ipl in pcb */
 
 	or.u	r11, r0, hi16(_C_LABEL(curproc))
-	ld	r11,r11, lo16(_C_LABEL(curproc))
-
-	or.u	r11, r0, hi16(_C_LABEL(curproc))
 	st	r0, r11, lo16(_C_LABEL(curproc))	/* curproc = NULL */
 
 ASLOCAL(Lidleloop)
@@ -149,7 +144,7 @@ ASLOCAL(Lidleloop)
 
 ASLOCAL(Lloopchk)			/* if whichqs is zero, keep checking */
 	bsr.n	_C_LABEL(setipl)	/* unmask all ints... */
-	 or	r2, r0, 0
+	 or	r2, r0, IPL_NONE
 
 	ldcr	r2, PSR
 	bb0	PSR_INTERRUPT_DISABLE_BIT, r2, 1f
@@ -161,8 +156,8 @@ ASLOCAL(Lloopchk)			/* if whichqs is zero, keep checking */
 	ldcr	r2, PSR
 #endif
 	clr	r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT>	/* ...and enable them */
-	FLUSH_PIPELINE
 	stcr	r2, PSR
+	FLUSH_PIPELINE
 1:
 	br	_ASM_LABEL(Lidleloop)