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authorVisa Hankala <visa@cvs.openbsd.org>2019-08-04 15:44:35 +0000
committerVisa Hankala <visa@cvs.openbsd.org>2019-08-04 15:44:35 +0000
commit36e0b233b3d5c332b4f917e508fc968b550b2a9d (patch)
tree13f9c702d8d6fa88da71f1212a196d6a6c581c6a /sys
parentfb07ec4d4a9df4f440f145563a859510f077f7fe (diff)
Ensure that a posted write completes when re-enabling interrupts
or sending an IPI.
Diffstat (limited to 'sys')
-rw-r--r--sys/arch/octeon/dev/octcit.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/sys/arch/octeon/dev/octcit.c b/sys/arch/octeon/dev/octcit.c
index f25b88676ad..6a32307cd34 100644
--- a/sys/arch/octeon/dev/octcit.c
+++ b/sys/arch/octeon/dev/octcit.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: octcit.c,v 1.10 2019/03/17 16:31:26 visa Exp $ */
+/* $OpenBSD: octcit.c,v 1.11 2019/08/04 15:44:34 visa Exp $ */
/*
* Copyright (c) 2017, 2019 Visa Hankala
@@ -484,8 +484,10 @@ octcit_splx(int newipl)
ci->ci_ipl = newipl;
- if (newipl < sc->sc_minipl[ci->ci_cpuid])
+ if (newipl < sc->sc_minipl[ci->ci_cpuid]) {
CIU3_WR_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)), 1ul << core);
+ (void)CIU3_RD_8(sc, CIU3_IDT_PP(CIU3_IDT(core, 0)));
+ }
/* If we still have softints pending trigger processing. */
if (ci->ci_softpending != 0 && newipl < IPL_SOFTINT)
@@ -528,8 +530,10 @@ void
octcit_ipi_set(cpuid_t cpuid)
{
struct octcit_softc *sc = octcit_sc;
+ uint64_t reg = CIU3_ISC_W1S(MBOX_INTSN(cpuid));
- CIU3_WR_8(sc, CIU3_ISC_W1S(MBOX_INTSN(cpuid)), CIU3_ISC_W1S_RAW);
+ CIU3_WR_8(sc, reg, CIU3_ISC_W1S_RAW);
+ (void)CIU3_RD_8(sc, reg);
}
void