new cpu type switch code.

initializes tlb miss handlers correspondent to probed cpu features.
also btlb load routine.
versions written are for pcxl and others.
cpu-dep btlb loaders are missing, only generic for now.

3 files changed, 336 insertions, 75 deletions

diff --git a/sys/arch/hppa/hppa/locore.S b/sys/arch/hppa/hppa/locore.S
index 707e19aa08d..19500b7c607 100644
--- a/sys/arch/hppa/hppa/locore.S
+++ b/sys/arch/hppa/hppa/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.30 2000/03/06 03:03:52 mickey Exp $	*/
+/*	$OpenBSD: locore.S,v 1.31 2000/03/23 20:25:40 mickey Exp $	*/
 
 /*
  * Copyright (c) 1998-2000 Michael Shalayeff
@@ -76,10 +76,6 @@
 #include "assym.h"
 
 
-	/* this macro determines when to use cr28 (ie HVT works) */
-#define	USECR28	((defined(HP7100LC_CPU) || defined(HP7300LC_CPU)) && \
-	!(defined(HP71000_CPU) || defined(HP7200_CPU) || defined(HP7300_CPU)))
-
 	.import	$global$, data
 	.import pdc, data
 	.import	boothowto, data
@@ -812,6 +808,7 @@ $syscall_end
  * interrupt vector table
  */
 #define	TLABEL(name)	$trap$name
+#define	TELABEL(num)	__CONCAT(trap_ep_,num)
 #define TRAP(name,num) \
 	.import TLABEL(name), code	! \
 	mtctl	r1, tr7			! \
@@ -832,11 +829,41 @@ $syscall_end
 	pre				! \
 	TRAP(name,num)
 
-#if USECR28
-#define	LDCR28	mfctl	cr28, r24
-#else
-#define	LDCR28	/* nop */
-#endif
+#define	STRAP(name,num,pre) \
+	.export	TLABEL(name)$num, entry	! \
+	.label	TLABEL(name)$num	! \
+	pre				! \
+	mtctl	r1, tr7			! \
+	.export	TELABEL(num), entry	! \
+	.label	TELABEL(num)		! \
+	ldil	0,r1			! \
+	ldo	0(r1), r1		! \
+	.call				! \
+	bv	0(r1)			! \
+	ldi	num, r1
+
+#define	LDILDO(name) 			! \
+	.export	name, entry		! \
+	.label	name			! \
+	ldil	L%$name,%r1		! \
+	ldo	R%$name(%r1), %r1
+
+LDILDO(itlb_x)
+LDILDO(dtlb_x)
+LDILDO(tlbd_x)
+
+LDILDO(itlb_s)
+LDILDO(dtlb_s)
+LDILDO(tlbd_s)
+
+LDILDO(itlb_t)
+LDILDO(dtlb_t)
+LDILDO(tlbd_t)
+
+LDILDO(itlb_l)
+LDILDO(dtlb_l)
+LDILDO(tlbd_l)
+
 #define	ITLBPRE \
 	mfctl	pcoq,r9		/* Offset */			! \
 	mfctl	pcsq,r8		/* Space  */			! \
@@ -844,8 +871,8 @@ $syscall_end
 #define	DTLBPRE \
 	mfctl	ior, r9		/* Offset */			! \
 	mfctl	isr, r8		/* Space  */			! \
-	depi    0,31,PGSHIFT,r9	/* align offset to page */	! \
-	LDCR28
+	depi    0,31,PGSHIFT,r9	/* align offset to page */
+	/* CR28XXX according to a popular belief cr28 should be read here */
 #define	HPMCPRE	nop
 
 	.align NBPG
@@ -859,7 +886,7 @@ hpmc_v
 	ATRAP(recnt,T_RECOVERY)		/*  3. recovery counter trap */
 	ATRAP(intr,T_INTERRUPT)		/*  4. external interrupt */
 	ATRAP(lpmc,T_LPMC)		/*  5. low-priority machine check */
-	CTRAP(itlb,T_ITLBMISS,ITLBPRE)	/*  6. instruction TLB miss fault */
+	STRAP(itlb,T_ITLBMISS,ITLBPRE)	/*  6. instruction TLB miss fault */
 	ATRAP(iprot,T_IPROT)		/*  7. instruction protection trap */
 	ATRAP(ill,T_ILLEGAL)		/*  8. Illegal instruction trap */
 	CTRAP(ibrk,T_IBREAK,)		/*  9. break instruction trap */
@@ -872,13 +899,13 @@ hpmc_v
 #else
 	ATRAP(excpt,T_EXCEPTION)
 #endif
-	CTRAP(dtlb,T_DTLBMISS,DTLBPRE)	/* 15. data TLB miss fault */
-	CTRAP(itlb,T_ITLBMISSNA,ITLBPRE)/* 16. ITLB non-access miss fault */
-	CTRAP(dtlb,T_DTLBMISSNA,DTLBPRE)/* 17. DTLB non-access miss fault */
+	STRAP(dtlb,T_DTLBMISS,DTLBPRE)	/* 15. data TLB miss fault */
+	STRAP(itlb,T_ITLBMISSNA,ITLBPRE)/* 16. ITLB non-access miss fault */
+	STRAP(dtlb,T_DTLBMISSNA,DTLBPRE)/* 17. DTLB non-access miss fault */
 	ATRAP(dprot,T_DPROT)		/* 18. data protection trap
 					      unalligned data reference trap */
 	ATRAP(dbrk,T_DBREAK)		/* 19. data break trap */
-	CTRAP(tlbd,T_TLB_DIRTY,DTLBPRE)	/* 20. TLB dirty bit trap */
+	STRAP(tlbd,T_TLB_DIRTY,DTLBPRE)	/* 20. TLB dirty bit trap */
 	ATRAP(pgref,T_PAGEREF)		/* 21. page reference trap */
 	CTRAP(emu,T_EMULATION,)		/* 22. assist emulation trap */
 	ATRAP(hpl,T_HIGHERPL)		/* 23. higher-privelege transfer trap*/
@@ -1155,8 +1182,7 @@ $sfu_emu
 	xor	r16, r24, r24		/* r24 ^= r16 */		! \
 	and	r17, r24, r24		/* r24 &= r17 */		! \
 	mfctl	vtop, r16		/* r16 = address of HPT table */! \
-	or	r16, r24, r24		/* r24 = HPT entry */		! \
-	mtctl	r24, cr28
+	or	r24, r16, r16		/* r16 = HPT entry */
 
 	/* Construct the virtual address tag. */
 #define	VTAG ! \
@@ -1164,83 +1190,75 @@ $sfu_emu
 	dep	r8, 31, 16, r16		/* put in the space id */	! \
 	depi	1, 0, 1, r16		/* and set the valid bit */
 
-
 	.align	64
-	.export	TLABEL(tlbd), entry
-TLABEL(tlbd)
-#if ! USECR28
+$tlbd_x
+$tlbd_s
+$tlbd_t
 	HPTENT	/* will update cr28 */
-#endif
+	mtctl	r16, cr28
 	
 	/*
 	 * Chase the list of entries for this hash bucket until we find
 	 * the correct mapping or NULL.
 	 */
-	ldw	hpt_entry(r24), r24
-$hash_loop_tlbd
+	ldw	hpt_entry(r16), r24
+$hash_loop_tlbd_t
 	comb,=,n r0, r24, TLABEL(all)
 	ldw	pv_va(r24), r25
 	ldw	pv_space(r24), r17
-	comb,<>,n r9, r25, $hash_loop_tlbd
+	comb,<>,n r9, r25, $hash_loop_tlbd_t
 	ldw	pv_hash(r24), r24
-	comb,<>,n r8, r17, $hash_loop_tlbd
+	comb,<>,n r8, r17, $hash_loop_tlbd_t
 	ldw	pv_hash(r24), r24
 
-#if ! USECR28
 	VTAG	/* (r8,r9) -> r16 */
-#endif
 	/* Set the dirty bit for this physical page. */
 	ldw	pv_tlbprot(r24), r25
-	b	$tlb_inshpt
+	b	$tlb_inshpt_t
 	depi	1, TLB_DIRTY_POS, 1, r25
 	
 	.align	32
-	.export	TLABEL(itlb), entry
-TLABEL(itlb)
-#if USECR28
-	HPTENT	/* will update cr28 */
-#endif
-	depi	1, TFF_ITLB_POS, 1, r1	/* mark for ITLB insert */
-	/* FALLTHROUGH */
+$itlb_x
+$itlb_s
+$itlb_t
 
-	.export	TLABEL(dtlb), entry
-TLABEL(dtlb)
-
-$tlbmiss
-	/* r1 is the trap type
+$dtlb_x
+$dtlb_s
+$dtlb_t
+	/*
+	 * r1 is the trap type
 	 * r8 is the space of the address that had the TLB miss
 	 * r9 is the offset of the address that had the TLB miss
 	 * r24 is the correspondent HPT entry pointer
 	 */
 
-#if ! USECR28
 	HPTENT	/* will update cr28 */
+	mtctl	r16, cr28
 	
+	ldw	hpt_tag(r16),r17
 	VTAG	/* (r8,r9) -> r16 */
-	ldw	hpt_tag(r24),r17
 
 	/* Compare the tag against the HPT entry.
 	   If it matches, then do the TLB insertion. */
-	comb,<>,n r16, r17, $tlb_gottalook
+	comb,<>,n r16, r17, $tlb_gottalook_t
 
 	ldw	hpt_tlbpage(r24), r17
-	b	$tlb_gothpt
+	b	$tlb_gothpt_t
 	ldw	hpt_tlbprot(r24), r25
 
-$tlb_gottalook
-#endif
+$tlb_gottalook_t
 	/*
 	 * Chase the list of entries for this hash bucket until we find
 	 * the correct mapping or NULL.
 	 */
 	ldw	hpt_entry(r24),r24
-$hash_loop
+$hash_loop_t
 	comb,=,n r0, r24, TLABEL(all)
 	ldw	pv_va(r24),r25
 	ldw	pv_space(r24),r17
-	comb,<>,n r9,r25,$hash_loop
+	comb,<>,n r9,r25,$hash_loop_t
 	ldw	pv_hash(r24),r24
-	comb,<>,n r8,r17,$hash_loop
+	comb,<>,n r8,r17,$hash_loop_t
 	ldw	pv_hash(r24),r24
 
 	/* Now set things up to enter the real mapping that we want */
@@ -1251,11 +1269,8 @@ $hash_loop
 	 * Load the HPT cache with the miss information for the next time.
 	 * The HPT entry address was saved by the HPTENT
 	 */
-$tlb_inshpt
+$tlb_inshpt_t
 	stw	r25, pv_tlbprot(r24)
-#if USECR28
-	VTAG	/* (r8,r9) -> r16 */
-#endif
 	ldw	pv_tlbpage(r24),r17
 	mfctl	cr28, r24
 
@@ -1263,9 +1278,9 @@ $tlb_inshpt
 	stw	r25, hpt_tlbprot(r24)
 	stw	r17, hpt_tlbpage(r24)
 
-$tlb_gothpt
+$tlb_gothpt_t
 	mfsp	sr1, r16
-	bb,<	r1, TFF_ITLB_POS, $tlb_itlb
+	bb,<	r1, TFF_ITLB_POS, $tlb_itlb_t
 	mtsp	r8, sr1
 
 	idtlba	r17,(sr1, r9)
@@ -1274,12 +1289,107 @@ $tlb_gothpt
 	rfir
 	nop
 
-$tlb_itlb
+$tlb_itlb_t
 	iitlba	r17,(sr1, r9)
 	iitlbp	r25,(sr1, r9)
 	mtsp	r16, sr1
 	rfir
 	nop
+
+	.align	32
+$tlbd_l
+	mfctl	cr28, r16
+
+	/*
+	 * Chase the list of entries for this hash bucket until we find
+	 * the correct mapping or NULL.
+	 */
+	ldw	hpt_entry(r16), r24
+$hash_loop_tlbd_l
+	comb,=,n r0, r24, TLABEL(all)
+	ldw	pv_va(r24), r25
+	ldw	pv_space(r24), r17
+	comb,<>,n r9, r25, $hash_loop_tlbd_l
+	ldw	pv_hash(r24), r24
+	comb,<>,n r8, r17, $hash_loop_tlbd_l
+	ldw	pv_hash(r24), r24
+
+	/* Set the dirty bit for this physical page. */
+	ldw	pv_tlbpage(r24),r17
+	ldw	pv_tlbprot(r24), r25
+	b	$tlb_inshpt_l
+	depi	1, TLB_DIRTY_POS, 1, r25
+	
+	.align	8
+$itlb_l
+	HPTENT	/* will update cr28 */
+#ifdef DDB
+	mtctl	r16, cr28
+#endif
+	b	$tlbmiss_l
+	depi	1, TFF_ITLB_POS, 1, r1	/* mark for ITLB insert */
+
+	.align	8
+$dtlb_l
+	/*mfctl	cr28, r16*/
+	HPTENT	/* weird, but sometimes dtlbmissna does not set cr28 */
+#ifdef DDB
+	mtctl	r16, cr28
+#endif
+$tlbmiss_l
+	/*
+	 * r1 is the trap type
+	 * r8 is the space of the address that had the TLB miss
+	 * r9 is the offset of the address that had the TLB miss
+	 * r16 is the correspondent HPT entry pointer
+	 */
+
+	/*
+	 * Chase the list of entries for this hash bucket until we find
+	 * the correct mapping or NULL.
+	 */
+	ldw	hpt_entry(r16),r24
+$hash_loop_l
+	comb,=,n r0, r24, TLABEL(all)
+	ldw	pv_va(r24),r25
+	ldw	pv_space(r24),r17
+	comb,<>,n r9,r25,$hash_loop_l
+	ldw	pv_hash(r24),r24
+	comb,<>,n r8,r17,$hash_loop_l
+	ldw	pv_hash(r24),r24
+
+	/* Now set things up to enter the real mapping that we want */
+	ldw	pv_tlbpage(r24),r17
+	ldw	pv_tlbprot(r24),r25
+	depi	1, TLB_REF_POS, 1, r25
+
+	/*
+	 * Load the HPT cache with the miss information for the next time.
+	 * The HPT entry address was saved by the HPTENT
+	 */
+$tlb_inshpt_l
+	stw	r25, pv_tlbprot(r24)
+	copy	r16, r24
+	VTAG	/* (r8,r9) -> r16 */
+
+	stw	r16, hpt_tag(r24)
+	stw	r25, hpt_tlbprot(r24)
+	bb,<	r1, TFF_ITLB_POS, $tlb_itlb_l
+	stw	r17, hpt_tlbpage(r24)
+
+	.word	0x04111440	; idtlbaf	r17
+	.word	0x04191400	; idtlbpf	r25
+	nop ! nop
+	rfir
+	nop
+
+$tlb_itlb_l
+	.word	0x04110440	; iitlbaf	r17
+	.word	0x04190400	; iitlbpf	r25
+	nop ! nop
+	rfir
+	nop
+
 	.export	$tlb_missend, entry
 $tlb_missend
 
diff --git a/sys/arch/hppa/hppa/machdep.c b/sys/arch/hppa/hppa/machdep.c
index c972583aae3..d6fbfef026c 100644
--- a/sys/arch/hppa/hppa/machdep.c
+++ b/sys/arch/hppa/hppa/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.24 2000/03/23 09:59:54 art Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.25 2000/03/23 20:25:41 mickey Exp $	*/
 
 /*
  * Copyright (c) 1999-2000 Michael Shalayeff
@@ -142,6 +142,9 @@ u_int	cpu_ticksnum, cpu_ticksdenom, cpu_hzticks;
 	/* exported info */
 char	machine[] = MACHINE_ARCH;
 char	cpu_model[128];
+enum hppa_cpu_type cpu_type;
+int (*cpu_btlb_ins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+	    vsize_t sz, u_int prot));
 #ifdef COMPAT_HPUX
 int	cpu_model_hpux;	/* contains HPUX_SYSCONF_CPU* kind of value */
 #endif
@@ -179,6 +182,44 @@ pid_t sigpid = 0;
 #define SDB_FOLLOW	0x01
 #endif
 
+/*
+ * Whatever CPU types we support
+ */
+extern u_int itlb_x[], dtlb_x[], tlbd_x[];
+extern u_int itlb_s[], dtlb_s[], tlbd_s[];
+extern u_int itlb_t[], dtlb_t[], tlbd_t[];
+extern u_int itlb_l[], dtlb_l[], tlbd_l[];
+int btlb_g __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+	    vsize_t sz, u_int prot));
+const struct hppa_cpu_typed {
+	char symid[8];
+	enum hppa_cpu_type type;
+	int  arch;
+	int  features;
+	u_int *itlbh, *dtlbh, *tlbdh;
+	int (*btlbins) __P((int i, pa_space_t sp, vaddr_t va, paddr_t pa,
+	    vsize_t sz, u_int prot));
+} cpu_types[] = {
+	{ "PCX",   hpcx,  0x10, 0,
+				itlb_x, dtlb_x, tlbd_x, btlb_g},
+	{ "PCXS",  hpcxs, 0x11, HPPA_FTRS_BTLBS,
+				itlb_s, dtlb_s, tlbd_s, btlb_g},
+	{ "PCXT",  hpcxt, 0x11, HPPA_FTRS_BTLBU,
+				itlb_t, dtlb_t, tlbd_t, btlb_g},
+	{ "PCXT'", hpcxta,0x11, HPPA_FTRS_BTLBU,
+				itlb_t, dtlb_t, tlbd_t, btlb_g},
+	{ "PCXL",  hpcxl, 0x11, HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+				itlb_l, dtlb_l, tlbd_l, btlb_g},
+	{ "PCXL2", hpcxl2,0x11, HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+				itlb_l, dtlb_l, tlbd_l, btlb_g},
+	{ "PCXU",  hpcxu, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+				itlb_l, dtlb_l, tlbd_l, btlb_g},
+	{ "PCXU2", hpcxu2,0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+				itlb_l, dtlb_l, tlbd_l, btlb_g},
+	{ "PCXW",  hpcxw, 0x20, HPPA_FTRS_W32B|HPPA_FTRS_BTLBU|HPPA_FTRS_HVT,
+				itlb_l, dtlb_l, tlbd_l, btlb_g},
+	{ "", 0 }
+};
 
 void
 hppa_init(start)
@@ -188,6 +229,7 @@ hppa_init(start)
 	vaddr_t v, vstart, vend;
 	register int error;
 	int hptsize;	/* size of HPT table if supported */
+	int cpu_features = 0;
 
 	boothowto |= RB_SINGLE;	/* XXX always go into single-user while debug */
 
@@ -231,12 +273,19 @@ hppa_init(start)
 
 	/* BTLB params */
 	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB,
-	    PDC_BTLB_DEFAULT, &pdc_btlb)) < 0)
-		panic("WARNING: PDC_BTLB error %d", error);
+	    PDC_BTLB_DEFAULT, &pdc_btlb)) < 0) {
+#ifdef DEBUG
+		printf("WARNING: PDC_BTLB error %d", error);
+#endif
+	} else {
+		/* purge TLBs and caches */
+		if (pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB,
+		    PDC_BTLB_PURGE_ALL) < 0)
+			printf("WARNING: BTLB purge failed\n");
 
-	/* purge TLBs and caches */
-	if (pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB, PDC_BTLB_PURGE_ALL) < 0)
-		printf("WARNING: BTLB purge failed\n");
+		cpu_features = pdc_btlb.finfo.num_c?
+		    HPPA_FTRS_BTLBU : HPPA_FTRS_BTLBS;
+	}
 
 	ptlball();
 	fcacheall();
@@ -245,22 +294,64 @@ hppa_init(start)
 	resvmem = ((vaddr_t)&kernel_text) / NBPG;
 
 	/* calculate HPT size */
-	for (hptsize = 1; hptsize < totalphysmem; hptsize *= 2);
-	mtctl(hptsize - 1, CR_HPTMASK);
+	for (hptsize = 256; hptsize < totalphysmem; hptsize *= 2);
+	hptsize *= 16;	/* sizeof(hpt_entry) */
 
 	if (pdc_call((iodcio_t)pdc, 0, PDC_TLB, PDC_TLB_INFO, &pdc_hwtlb) &&
 	    !pdc_hwtlb.min_size && !pdc_hwtlb.max_size) {
 		printf("WARNING: no HPT support, fine!\n");
+		mtctl(hptsize - 1, CR_HPTMASK);
 		hptsize = 0;
 	} else {
+		cpu_features |= HPPA_FTRS_HVT;
+
 		if (hptsize > pdc_hwtlb.max_size)
 			hptsize = pdc_hwtlb.max_size;
 		else if (hptsize < pdc_hwtlb.min_size)
 			hptsize = pdc_hwtlb.min_size;
-		/* have to reload after adjustment */
 		mtctl(hptsize - 1, CR_HPTMASK);
 	}
 
+	/*
+	 * Deal w/ CPU now
+	 */
+	{
+		const struct hppa_cpu_typed *p;
+
+		for (p = cpu_types;
+		     p->arch && p->features != cpu_features; p++);
+
+		if (!p->arch)
+			printf("WARNING: UNKNOWN CPU TYPE; GOOD LUCK (%x)\n",
+			    cpu_features);
+		else {
+		/*
+		 * Ptrs to various tlb handlers, to be filled based on cpu
+		 * features.
+		 * from locore.S
+		 */
+		extern u_int trap_ep_T_TLB_DIRTY[];
+		extern u_int trap_ep_T_ITLBMISS[];
+		extern u_int trap_ep_T_DTLBMISS[];
+		extern u_int trap_ep_T_ITLBMISSNA[];
+		extern u_int trap_ep_T_DTLBMISSNA[];
+#define	LDILDO(t,f) ((t)[0] = (f)[0], (t)[1] = (f)[1])
+
+#ifdef DEBUG
+			printf("cputype: %s\n", p->symid);
+#endif
+			cpu_type = p->type;
+
+			cpu_btlb_ins = p->btlbins;
+			LDILDO(trap_ep_T_TLB_DIRTY , p->tlbdh);
+			LDILDO(trap_ep_T_ITLBMISS  , p->itlbh);
+			LDILDO(trap_ep_T_DTLBMISS  , p->dtlbh);
+			LDILDO(trap_ep_T_ITLBMISSNA, p->itlbh);
+			LDILDO(trap_ep_T_DTLBMISSNA, p->dtlbh);
+#undef LDILDO
+		}
+	}
+
 	/* we hope this won't fail */
 	hppa_ex = extent_create("mem", 0x0, 0xffffffff, M_DEVBUF,
 	    (caddr_t)mem_ex_storage, sizeof(mem_ex_storage),
@@ -665,6 +756,26 @@ ptlball()
 }
 
 int
+btlb_g(i, sp, va, pa, sz, prot)
+	int i;
+	pa_space_t sp;
+	vaddr_t va;
+	paddr_t pa;
+	vsize_t sz;
+	u_int prot;
+{
+	int error;
+
+	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB, PDC_BTLB_INSERT,
+	    sp, va, pa, sz, prot, i)) < 0) {
+#ifdef BTLBDEBUG
+		printf("WARNING: BTLB insert failed (%d)\n", error);
+#endif
+	}
+	return error;
+}
+
+int
 btlb_insert(space, va, pa, lenp, prot)
 	pa_space_t space;
 	vaddr_t va;
@@ -702,13 +813,8 @@ btlb_insert(space, va, pa, lenp, prot)
 #ifdef BTLBDEBUG
 	printf("btlb_insert(%d): %x:%x=%x[%x,%x]\n", i, space, va, pa, len, prot);
 #endif
-	if ((error = pdc_call((iodcio_t)pdc, 0, PDC_BLOCK_TLB,PDC_BTLB_INSERT,
-	    space, va, pa, len, prot, i)) < 0) {
-#ifdef BTLBDEBUG
-		printf("WARNING: BTLB insert failed (%d)\n", error);
-#endif
+	if ((error = (*cpu_btlb_ins)(i, space, va, pa, len, prot)) < 0)
 		return -(EINVAL);
-	}
 	*lenp = len << PGSHIFT;
 
 	return i;
diff --git a/sys/arch/hppa/include/cpu.h b/sys/arch/hppa/include/cpu.h
index 1531c7af19f..4358ad9a910 100644
--- a/sys/arch/hppa/include/cpu.h
+++ b/sys/arch/hppa/include/cpu.h
@@ -1,5 +1,35 @@
-/*	$OpenBSD: cpu.h,v 1.13 2000/02/10 20:05:40 mickey Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.14 2000/03/23 20:25:41 mickey Exp $	*/
 
+/*
+ * Copyright (c) 2000 Michael Shalayeff
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Michael Shalayeff.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
 /* 
  * Copyright (c) 1988-1994, The University of Utah and
  * the Computer Systems Laboratory at the University of Utah (CSL).
@@ -30,6 +60,21 @@
 #include <machine/frame.h>
 
 /*
+ * CPU types and features
+ */
+#define	HPPA_FTRS_BTLBS		0x00000001
+#define	HPPA_FTRS_BTLBU		0x00000002
+#define	HPPA_FTRS_HVT		0x00000004
+#define	HPPA_FTRS_W32B		0x00000008
+
+#ifndef _LOCORE
+/* types */
+enum hppa_cpu_type {
+	hpcx, hpcxs, hpcxt, hpcxta, hpcxl, hpcxl2, hpcxu, hpcxu2, hpcxw
+};
+#endif
+
+/*
  * Exported definitions unique to hp700/PA-RISC cpu support.
  */