diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2012-10-03 11:18:24 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2012-10-03 11:18:24 +0000 |
| commit | 40e3b31eb52791f78d8294f973e18e478768dd5a (patch) | |
| tree | dd94803161c69ecfd6f8a5385bae313dc5440bec /sys | |
| parent | 74ffcd00af46573db81d04bbf92fa9fa46cea959 (diff) | |
Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs,
which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the
goriest md details, which are only of interest to a handful set of files; this
is similar in spirit to what alpha does, but here <machine/cpu.h> does not
include the new file.
Diffstat (limited to 'sys')
43 files changed, 409 insertions, 312 deletions
diff --git a/sys/arch/loongson/dev/bonito.c b/sys/arch/loongson/dev/bonito.c index 2874ac03938..c6eee9e18b6 100644 --- a/sys/arch/loongson/dev/bonito.c +++ b/sys/arch/loongson/dev/bonito.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bonito.c,v 1.21 2012/09/29 19:24:30 miod Exp $ */ +/* $OpenBSD: bonito.c,v 1.22 2012/10/03 11:18:20 miod Exp $ */ /* $NetBSD: bonito_mainbus.c,v 1.11 2008/04/28 20:23:10 martin Exp $ */ /* $NetBSD: bonito_pci.c,v 1.5 2008/04/28 20:23:28 martin Exp $ */ @@ -60,6 +60,7 @@ #include <machine/autoconf.h> #include <machine/bus.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/intr.h> #include <dev/pci/pcidevs.h> diff --git a/sys/arch/loongson/loongson/generic2e_machdep.c b/sys/arch/loongson/loongson/generic2e_machdep.c index be8a7d2f4ad..f868d0a1fb8 100644 --- a/sys/arch/loongson/loongson/generic2e_machdep.c +++ b/sys/arch/loongson/loongson/generic2e_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: generic2e_machdep.c,v 1.3 2012/09/29 18:54:38 miod Exp $ */ +/* $OpenBSD: generic2e_machdep.c,v 1.4 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2010 Miodrag Vallat. @@ -55,6 +55,7 @@ #include <mips64/archtype.h> #include <machine/autoconf.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/pmon.h> #include <dev/ic/i8259reg.h> diff --git a/sys/arch/loongson/loongson/locore.S b/sys/arch/loongson/loongson/locore.S index f84a72d5f5d..2c5af444e1c 100644 --- a/sys/arch/loongson/loongson/locore.S +++ b/sys/arch/loongson/loongson/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.2 2010/02/14 22:39:33 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.3 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -31,6 +31,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> diff --git a/sys/arch/loongson/loongson/machdep.c b/sys/arch/loongson/loongson/machdep.c index 3f48fe2975a..5a03811f924 100644 --- a/sys/arch/loongson/loongson/machdep.c +++ b/sys/arch/loongson/loongson/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.36 2012/09/29 19:11:06 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.37 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2009, 2010 Miodrag Vallat. @@ -72,6 +72,7 @@ #include <machine/autoconf.h> #include <mips64/cache.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/memconf.h> #include <machine/pmon.h> diff --git a/sys/arch/loongson/loongson/yeeloong_machdep.c b/sys/arch/loongson/loongson/yeeloong_machdep.c index d5d2baeba9c..922e560cb7b 100644 --- a/sys/arch/loongson/loongson/yeeloong_machdep.c +++ b/sys/arch/loongson/loongson/yeeloong_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: yeeloong_machdep.c,v 1.18 2012/09/29 18:54:38 miod Exp $ */ +/* $OpenBSD: yeeloong_machdep.c,v 1.19 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2009, 2010 Miodrag Vallat. @@ -29,6 +29,7 @@ #include <mips64/archtype.h> #include <machine/autoconf.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/pmon.h> #include <dev/isa/isareg.h> diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h index 7e7a17e89d1..f562c1f8091 100644 --- a/sys/arch/mips64/include/cpu.h +++ b/sys/arch/mips64/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.89 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: cpu.h,v 1.90 2012/10/03 11:18:23 miod Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -114,269 +114,6 @@ #endif /* _LOCORE */ -#if defined(_KERNEL) || defined(_STANDALONE) - -/* - * Status register. - */ - -#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ -#define SR_COP_0_BIT 0x10000000 -#define SR_COP_1_BIT 0x20000000 -#define SR_RP 0x08000000 -#define SR_FR_32 0x04000000 -#define SR_RE 0x02000000 -#define SR_DSD 0x01000000 /* Only on R12000 */ -#define SR_BOOT_EXC_VEC 0x00400000 -#define SR_TLB_SHUTDOWN 0x00200000 -#define SR_SOFT_RESET 0x00100000 -#define SR_DIAG_CH 0x00040000 -#define SR_DIAG_CE 0x00020000 -#define SR_DIAG_DE 0x00010000 -#define SR_KX 0x00000080 -#define SR_SX 0x00000040 -#define SR_UX 0x00000020 -#define SR_ERL 0x00000004 -#define SR_EXL 0x00000002 -#define SR_INT_ENAB 0x00000001 - -#define SOFT_INT_MASK_0 0x00000100 -#define SOFT_INT_MASK_1 0x00000200 -#define SR_INT_MASK_0 0x00000400 -#define SR_INT_MASK_1 0x00000800 -#define SR_INT_MASK_2 0x00001000 -#define SR_INT_MASK_3 0x00002000 -#define SR_INT_MASK_4 0x00004000 -#define SR_INT_MASK_5 0x00008000 - -/* R8000-specific bits */ -#define SR_SERIALIZE_FPU 0x0000010000000000 -#define SR_KPGSZ_SHIFT 36 -#define SR_UPGSZ_SHIFT 32 -#define SR_PGSZ_4K 0 -#define SR_PGSZ_8K 1 -#define SR_PGSZ_16K 2 -#define SR_PGSZ_64K 3 -#define SR_PGSZ_1M 4 -#define SR_PGSZ_4M 5 -#define SR_PGSZ_16M 6 -#define SR_PGSZ_MASK 0x0f - -#define SR_INT_MASK_6 0x00010000 -#define SR_INT_MASK_7 0x00020000 -#define SR_INT_MASK_8 0x00040000 - -#ifdef CPU_R8000 -#define SR_XX 0x00000040 -#define SR_KSU_MASK 0x00000010 -#define SR_KSU_USER 0x00000010 -#define SR_KSU_KERNEL 0x00000000 -#define SR_INT_MASK 0x0007ff00 -#else -#define SR_XX 0x80000000 -#define SR_KSU_MASK 0x00000018 -#define SR_KSU_USER 0x00000010 -#define SR_KSU_SUPER 0x00000008 -#define SR_KSU_KERNEL 0x00000000 -#define SR_INT_MASK 0x0000ff00 -#endif - -/* - * Interrupt control register in RM7000. Expansion of interrupts. - */ - -#define IC_INT_MASK 0x00003f00 /* Two msb reserved */ -#define IC_INT_MASK_6 0x00000100 -#define IC_INT_MASK_7 0x00000200 -#define IC_INT_MASK_8 0x00000400 -#define IC_INT_MASK_9 0x00000800 -#define IC_INT_TIMR 0x00001000 /* 12 Timer */ -#define IC_INT_PERF 0x00002000 /* 13 Performance counter */ -#define IC_INT_TE 0x00000080 /* Timer on INT11 */ - -#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) - -/* - * Cause register. - */ - -#ifdef CPU_R8000 -#define CR_BR_DELAY 0x8000000000000000 -#define CR_EXC_CODE 0x000000f8 -#define CR_EXC_CODE_SHIFT 3 -#define CR_COP_ERR 0x10000000 -#else -#define CR_BR_DELAY 0x80000000 -#define CR_EXC_CODE 0x0000007c -#define CR_EXC_CODE_SHIFT 2 -#define CR_COP_ERR 0x30000000 -#endif -#define CR_COP1_ERR 0x10000000 -#define CR_COP2_ERR 0x20000000 -#define CR_COP3_ERR 0x20000000 -#define CR_INT_SOFT0 0x00000100 -#define CR_INT_SOFT1 0x00000200 -#define CR_INT_0 0x00000400 -#define CR_INT_1 0x00000800 -#define CR_INT_2 0x00001000 -#define CR_INT_3 0x00002000 -#define CR_INT_4 0x00004000 -#define CR_INT_5 0x00008000 -/* Following on RM7000 and R8000 */ -#define CR_INT_6 0x00010000 -#define CR_INT_7 0x00020000 -#define CR_INT_8 0x00040000 -/* Following on RM7000 */ -#define CR_INT_9 0x00080000 -#define CR_INT_HARD 0x000ffc00 -#define CR_INT_TIMR 0x00100000 /* 12 Timer */ -#define CR_INT_PERF 0x00200000 /* 13 Performance counter */ -/* R8000 specific */ -#define CR_FPE 0x01000000 -#define CR_VCE 0x02000000 -#define CR_BERR 0x04000000 -#define CR_NMI 0x08000000 - -#ifdef CPU_R8000 -#define CR_INT_MASK 0x0407ff00 /* contains CR_BERR */ -#else -#define CR_INT_MASK 0x003fff00 -#endif - -/* - * Config register. - */ - -#define CFGR_CCA_MASK 0x00000007 -#define CFGR_CU 0x00000008 -#define CFGR_ICE 0x0000000200000000 -#define CFGR_SMM 0x0000000400000000 - -/* - * Location of exception vectors. - */ - -#ifdef CPU_R8000 -#define RESET_EXC_VEC PHYS_TO_XKPHYS(0x1fc00000, CCA_NC) -/* all the others are relative to COP_0_TRAPBASE */ -/* #define UTLB_MISS_EXC_VEC 0x00000000 */ -/* #define KV1TLB_MISS_EXC_VEC 0x00000400 */ -/* #define KV0TLB_MISS_EXC_VEC 0x00000800 */ -/* #define GEN_EXC_VEC 0x00000c00 */ -#else -#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) -#define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000) -#define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080) -#define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100) -#define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180) -#endif - -/* - * Coprocessor 0 registers - */ - -/* Common subset */ -#define COP_0_COUNT $9 -#define COP_0_TLB_HI $10 -#define COP_0_STATUS_REG $12 -#define COP_0_CAUSE_REG $13 -#define COP_0_EXC_PC $14 -#define COP_0_PRID $15 -#define COP_0_CONFIG $16 - -/* R4000/5000/10000 */ -#define COP_0_TLB_INDEX $0 -#define COP_0_TLB_RANDOM $1 -#define COP_0_TLB_LO0 $2 -#define COP_0_TLB_LO1 $3 -#define COP_0_TLB_CONTEXT $4 -#define COP_0_TLB_PG_MASK $5 -#define COP_0_TLB_WIRED $6 -#define COP_0_BAD_VADDR $8 -#define COP_0_COMPARE $11 -#define COP_0_LLADDR $17 -#define COP_0_WATCH_LO $18 -#define COP_0_WATCH_HI $19 -#define COP_0_TLB_XCONTEXT $20 -#define COP_0_ECC $26 -#define COP_0_CACHE_ERR $27 -#define COP_0_TAG_LO $28 -#define COP_0_TAG_HI $29 -#define COP_0_ERROR_PC $30 - -/* R8000 specific */ -#define COP_0_TLB_SET $0 -#define COP_0_TLB_LO $2 -#define COP_0_UBASE $4 -#define COP_0_SHIFTAMT $5 -#define COP_0_TRAPBASE $6 -#define COP_0_BAD_PADDR $7 -#define COP_0_VADDR $8 -#define COP_0_WORK0 $18 -#define COP_0_WORK1 $19 -#define COP_0_PBASE $20 -#define COP_0_GBASE $21 -#define COP_0_TFP_TLB_WIRED $24 -#define COP_0_DCACHE $28 -#define COP_0_ICACHE $29 - -/* RM7000 specific */ -#define COP_0_WATCH_1 $18 -#define COP_0_WATCH_2 $19 -#define COP_0_WATCH_M $24 -#define COP_0_PC_COUNT $25 -#define COP_0_PC_CTRL $22 - -#define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ - -/* R10000 specific */ -#define COP_0_TLB_FR_MASK $21 - -/* Loongson-2 specific */ -#define COP_0_DIAG $22 - -/* Octeon specific */ -#define COP_0_TLB_PG_GRAIN $5, 1 -#define COP_0_CVMCTL $9, 7 -#define COP_0_CVMMEMCTL $11, 7 -#define COP_0_EBASE $15, 1 - -/* - * COP_0_COUNT speed divider. - */ -#if defined(CPU_OCTEON) || defined(CPU_R8000) -#define CP0_CYCLE_DIVIDER 1 -#else -#define CP0_CYCLE_DIVIDER 2 -#endif - -/* - * Values for the code field in a break instruction. - */ -#define BREAK_INSTR 0x0000000d -#define BREAK_VAL_MASK 0x03ff0000 -#define BREAK_VAL_SHIFT 16 -#define BREAK_KDB_VAL 512 -#define BREAK_SSTEP_VAL 513 -#define BREAK_BRKPT_VAL 514 -#define BREAK_SOVER_VAL 515 -#define BREAK_DDB_VAL 516 -#define BREAK_FPUEMUL_VAL 517 -#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) -#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) -#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) -#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) -#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) -#define BREAK_FPUEMUL (BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT)) - -/* - * The floating point version and status registers. - */ -#define FPC_ID $0 -#define FPC_CSR $31 - -#endif /* _KERNEL || _STANDALONE */ - /* * Exported definitions unique to mips cpu support. */ @@ -522,6 +259,7 @@ void cp0_calibrate(struct cpu_info *); */ #define clockframe trap_frame /* Use normal trap frame */ +#define SR_KSU_USER 0x00000010 #define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) #define CLKF_PC(framep) ((framep)->pc) #define CLKF_INTR(framep) (curcpu()->ci_intrdepth > 1) /* XXX */ @@ -571,6 +309,28 @@ void cp0_calibrate(struct cpu_info *); #endif /* _KERNEL && !_LOCORE */ +#ifdef _KERNEL +/* + * Values for the code field in a break instruction. + */ +#define BREAK_INSTR 0x0000000d +#define BREAK_VAL_MASK 0x03ff0000 +#define BREAK_VAL_SHIFT 16 +#define BREAK_KDB_VAL 512 +#define BREAK_SSTEP_VAL 513 +#define BREAK_BRKPT_VAL 514 +#define BREAK_SOVER_VAL 515 +#define BREAK_DDB_VAL 516 +#define BREAK_FPUEMUL_VAL 517 +#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) +#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) +#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) +#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) +#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) +#define BREAK_FPUEMUL (BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT)) + +#endif /* _KERNEL */ + /* * CTL_MACHDEP definitions. */ diff --git a/sys/arch/mips64/include/mips_cpu.h b/sys/arch/mips64/include/mips_cpu.h new file mode 100644 index 00000000000..b7c26f6ae93 --- /dev/null +++ b/sys/arch/mips64/include/mips_cpu.h @@ -0,0 +1,294 @@ +/* $OpenBSD: mips_cpu.h,v 1.1 2012/10/03 11:18:23 miod Exp $ */ + +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell and Rick Macklem. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * Copyright (C) 1989 Digital Equipment Corporation. + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appears in all copies. + * Digital Equipment Corporation makes no representations about the + * suitability of this software for any purpose. It is provided "as is" + * without express or implied warranty. + * + * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 + */ + +#ifndef _MIPS64_CPUREGS_H_ +#define _MIPS64_CPUREGS_H_ + +#if defined(_KERNEL) || defined(_STANDALONE) + +/* + * Status register. + */ + +#define SR_COP_USABILITY 0x30000000 /* CP0 and CP1 only */ +#define SR_COP_0_BIT 0x10000000 +#define SR_COP_1_BIT 0x20000000 +#define SR_RP 0x08000000 +#define SR_FR_32 0x04000000 +#define SR_RE 0x02000000 +#define SR_DSD 0x01000000 /* Only on R12000 */ +#define SR_BOOT_EXC_VEC 0x00400000 +#define SR_TLB_SHUTDOWN 0x00200000 +#define SR_SOFT_RESET 0x00100000 +#define SR_DIAG_CH 0x00040000 +#define SR_DIAG_CE 0x00020000 +#define SR_DIAG_DE 0x00010000 +#define SR_KX 0x00000080 +#define SR_SX 0x00000040 +#define SR_UX 0x00000020 +#define SR_ERL 0x00000004 +#define SR_EXL 0x00000002 +#define SR_INT_ENAB 0x00000001 + +#define SOFT_INT_MASK_0 0x00000100 +#define SOFT_INT_MASK_1 0x00000200 +#define SR_INT_MASK_0 0x00000400 +#define SR_INT_MASK_1 0x00000800 +#define SR_INT_MASK_2 0x00001000 +#define SR_INT_MASK_3 0x00002000 +#define SR_INT_MASK_4 0x00004000 +#define SR_INT_MASK_5 0x00008000 + +/* R8000-specific bits */ +#define SR_SERIALIZE_FPU 0x0000010000000000 +#define SR_KPGSZ_SHIFT 36 +#define SR_UPGSZ_SHIFT 32 +#define SR_PGSZ_4K 0 +#define SR_PGSZ_8K 1 +#define SR_PGSZ_16K 2 +#define SR_PGSZ_64K 3 +#define SR_PGSZ_1M 4 +#define SR_PGSZ_4M 5 +#define SR_PGSZ_16M 6 +#define SR_PGSZ_MASK 0x0f + +#define SR_INT_MASK_6 0x00010000 +#define SR_INT_MASK_7 0x00020000 +#define SR_INT_MASK_8 0x00040000 + +#ifdef CPU_R8000 +#define SR_XX 0x00000040 +#define SR_KSU_MASK 0x00000010 +#define SR_KSU_KERNEL 0x00000000 +#define SR_INT_MASK 0x0007ff00 +#else +#define SR_XX 0x80000000 +#define SR_KSU_MASK 0x00000018 +#define SR_KSU_SUPER 0x00000008 +#define SR_KSU_KERNEL 0x00000000 +#define SR_INT_MASK 0x0000ff00 +#endif +/* SR_KSU_USER is in <mips64/cpu.h> for CLKF_USERMODE() */ +#ifndef SR_KSU_USER +#define SR_KSU_USER 0x00000010 +#endif + +/* + * Interrupt control register in RM7000. Expansion of interrupts. + */ + +#define IC_INT_MASK 0x00003f00 /* Two msb reserved */ +#define IC_INT_MASK_6 0x00000100 +#define IC_INT_MASK_7 0x00000200 +#define IC_INT_MASK_8 0x00000400 +#define IC_INT_MASK_9 0x00000800 +#define IC_INT_TIMR 0x00001000 /* 12 Timer */ +#define IC_INT_PERF 0x00002000 /* 13 Performance counter */ +#define IC_INT_TE 0x00000080 /* Timer on INT11 */ + +#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) + +/* + * Cause register. + */ + +#ifdef CPU_R8000 +#define CR_BR_DELAY 0x8000000000000000 +#define CR_EXC_CODE 0x000000f8 +#define CR_EXC_CODE_SHIFT 3 +#define CR_COP_ERR 0x10000000 +#else +#define CR_BR_DELAY 0x80000000 +#define CR_EXC_CODE 0x0000007c +#define CR_EXC_CODE_SHIFT 2 +#define CR_COP_ERR 0x30000000 +#endif +#define CR_COP1_ERR 0x10000000 +#define CR_COP2_ERR 0x20000000 +#define CR_COP3_ERR 0x20000000 +#define CR_INT_SOFT0 0x00000100 +#define CR_INT_SOFT1 0x00000200 +#define CR_INT_0 0x00000400 +#define CR_INT_1 0x00000800 +#define CR_INT_2 0x00001000 +#define CR_INT_3 0x00002000 +#define CR_INT_4 0x00004000 +#define CR_INT_5 0x00008000 +/* Following on RM7000 and R8000 */ +#define CR_INT_6 0x00010000 +#define CR_INT_7 0x00020000 +#define CR_INT_8 0x00040000 +/* Following on RM7000 */ +#define CR_INT_9 0x00080000 +#define CR_INT_HARD 0x000ffc00 +#define CR_INT_TIMR 0x00100000 /* 12 Timer */ +#define CR_INT_PERF 0x00200000 /* 13 Performance counter */ +/* R8000 specific */ +#define CR_FPE 0x01000000 +#define CR_VCE 0x02000000 +#define CR_BERR 0x04000000 +#define CR_NMI 0x08000000 + +#ifdef CPU_R8000 +#define CR_INT_MASK 0x0407ff00 /* contains CR_BERR */ +#else +#define CR_INT_MASK 0x003fff00 +#endif + +/* + * Config register. + */ + +#define CFGR_CCA_MASK 0x00000007 +#define CFGR_CU 0x00000008 +#define CFGR_ICE 0x0000000200000000 +#define CFGR_SMM 0x0000000400000000 + +/* + * Location of exception vectors. + */ + +#ifdef CPU_R8000 +#define RESET_EXC_VEC PHYS_TO_XKPHYS(0x1fc00000, CCA_NC) +/* all the others are relative to COP_0_TRAPBASE */ +/* #define UTLB_MISS_EXC_VEC 0x00000000 */ +/* #define KV1TLB_MISS_EXC_VEC 0x00000400 */ +/* #define KV0TLB_MISS_EXC_VEC 0x00000800 */ +/* #define GEN_EXC_VEC 0x00000c00 */ +#else +#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) +#define TLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000000) +#define XTLB_MISS_EXC_VEC (CKSEG1_BASE + 0x00000080) +#define CACHE_ERR_EXC_VEC (CKSEG1_BASE + 0x00000100) +#define GEN_EXC_VEC (CKSEG1_BASE + 0x00000180) +#endif + +/* + * Coprocessor 0 registers + */ + +/* Common subset */ +#define COP_0_COUNT $9 +#define COP_0_TLB_HI $10 +#define COP_0_STATUS_REG $12 +#define COP_0_CAUSE_REG $13 +#define COP_0_EXC_PC $14 +#define COP_0_PRID $15 +#define COP_0_CONFIG $16 + +/* R4000/5000/10000 */ +#define COP_0_TLB_INDEX $0 +#define COP_0_TLB_RANDOM $1 +#define COP_0_TLB_LO0 $2 +#define COP_0_TLB_LO1 $3 +#define COP_0_TLB_CONTEXT $4 +#define COP_0_TLB_PG_MASK $5 +#define COP_0_TLB_WIRED $6 +#define COP_0_BAD_VADDR $8 +#define COP_0_COMPARE $11 +#define COP_0_LLADDR $17 +#define COP_0_WATCH_LO $18 +#define COP_0_WATCH_HI $19 +#define COP_0_TLB_XCONTEXT $20 +#define COP_0_ECC $26 +#define COP_0_CACHE_ERR $27 +#define COP_0_TAG_LO $28 +#define COP_0_TAG_HI $29 +#define COP_0_ERROR_PC $30 + +/* R8000 specific */ +#define COP_0_TLB_SET $0 +#define COP_0_TLB_LO $2 +#define COP_0_UBASE $4 +#define COP_0_SHIFTAMT $5 +#define COP_0_TRAPBASE $6 +#define COP_0_BAD_PADDR $7 +#define COP_0_VADDR $8 +#define COP_0_WORK0 $18 +#define COP_0_WORK1 $19 +#define COP_0_PBASE $20 +#define COP_0_GBASE $21 +#define COP_0_TFP_TLB_WIRED $24 +#define COP_0_DCACHE $28 +#define COP_0_ICACHE $29 + +/* RM7000 specific */ +#define COP_0_WATCH_1 $18 +#define COP_0_WATCH_2 $19 +#define COP_0_WATCH_M $24 +#define COP_0_PC_COUNT $25 +#define COP_0_PC_CTRL $22 + +#define COP_0_ICR $20 /* Use cfc0/ctc0 to access */ + +/* R10000 specific */ +#define COP_0_TLB_FR_MASK $21 + +/* Loongson-2 specific */ +#define COP_0_DIAG $22 + +/* Octeon specific */ +#define COP_0_TLB_PG_GRAIN $5, 1 +#define COP_0_CVMCTL $9, 7 +#define COP_0_CVMMEMCTL $11, 7 +#define COP_0_EBASE $15, 1 + +/* + * COP_0_COUNT speed divider. + */ +#if defined(CPU_OCTEON) || defined(CPU_R8000) +#define CP0_CYCLE_DIVIDER 1 +#else +#define CP0_CYCLE_DIVIDER 2 +#endif + +/* + * The floating point version and status registers. + */ +#define FPC_ID $0 +#define FPC_CSR $31 + +#endif /* _KERNEL || _STANDALONE */ + +#endif /* !_MIPS64_CPUREGS_H_ */ diff --git a/sys/arch/mips64/mips64/cache_r4k.c b/sys/arch/mips64/mips64/cache_r4k.c index 577709269f0..774306d7a5d 100644 --- a/sys/arch/mips64/mips64/cache_r4k.c +++ b/sys/arch/mips64/mips64/cache_r4k.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_r4k.c,v 1.10 2012/09/29 19:24:31 miod Exp $ */ +/* $OpenBSD: cache_r4k.c,v 1.11 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -21,6 +21,7 @@ #include <mips64/cache.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <uvm/uvm_extern.h> diff --git a/sys/arch/mips64/mips64/cache_r5k.c b/sys/arch/mips64/mips64/cache_r5k.c index fa97c87f97e..d27f407682d 100644 --- a/sys/arch/mips64/mips64/cache_r5k.c +++ b/sys/arch/mips64/mips64/cache_r5k.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_r5k.c,v 1.7 2012/09/29 19:24:31 miod Exp $ */ +/* $OpenBSD: cache_r5k.c,v 1.8 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -60,6 +60,7 @@ #include <mips64/cache.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <uvm/uvm_extern.h> diff --git a/sys/arch/mips64/mips64/cache_tfp_subr.S b/sys/arch/mips64/mips64/cache_tfp_subr.S index 1f9ef4aaa73..05ab11a9d51 100644 --- a/sys/arch/mips64/mips64/cache_tfp_subr.S +++ b/sys/arch/mips64/mips64/cache_tfp_subr.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_tfp_subr.S,v 1.1 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: cache_tfp_subr.S,v 1.2 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -19,6 +19,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include "assym.h" diff --git a/sys/arch/mips64/mips64/clock.c b/sys/arch/mips64/mips64/clock.c index 2379b038a5e..a6ab97a041a 100644 --- a/sys/arch/mips64/mips64/clock.c +++ b/sys/arch/mips64/mips64/clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: clock.c,v 1.37 2012/07/14 19:50:12 miod Exp $ */ +/* $OpenBSD: clock.c,v 1.38 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -42,6 +42,7 @@ #include <machine/autoconf.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <mips64/dev/clockvar.h> diff --git a/sys/arch/mips64/mips64/context.S b/sys/arch/mips64/mips64/context.S index 846ab4d223c..174eafd8bfe 100644 --- a/sys/arch/mips64/mips64/context.S +++ b/sys/arch/mips64/mips64/context.S @@ -1,4 +1,4 @@ -/* $OpenBSD: context.S,v 1.50 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: context.S,v 1.51 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2002-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -33,6 +33,7 @@ #include <machine/cpu.h> #include <machine/pte.h> #include <machine/regnum.h> +#include <mips64/mips_cpu.h> #include <machine/cpustate.h> #ifdef CPU_LOONGSON2 #include <machine/loongson2.h> diff --git a/sys/arch/mips64/mips64/cp0access.S b/sys/arch/mips64/mips64/cp0access.S index e4bd7891380..b92dcfbecb9 100644 --- a/sys/arch/mips64/mips64/cp0access.S +++ b/sys/arch/mips64/mips64/cp0access.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cp0access.S,v 1.18 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: cp0access.S,v 1.19 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -36,6 +36,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include "assym.h" diff --git a/sys/arch/mips64/mips64/cpu.c b/sys/arch/mips64/mips64/cpu.c index b57e00dfb8e..fd9b14d1cd4 100644 --- a/sys/arch/mips64/mips64/cpu.c +++ b/sys/arch/mips64/mips64/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.48 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: cpu.c,v 1.49 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 1997-2004 Opsycon AB (www.opsycon.se) @@ -35,6 +35,7 @@ #include <uvm/uvm_extern.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/autoconf.h> int cpumatch(struct device *, void *, void *); diff --git a/sys/arch/mips64/mips64/exception.S b/sys/arch/mips64/mips64/exception.S index e01a9a8073b..1faa2eec42a 100644 --- a/sys/arch/mips64/mips64/exception.S +++ b/sys/arch/mips64/mips64/exception.S @@ -1,4 +1,4 @@ -/* $OpenBSD: exception.S,v 1.35 2012/09/29 19:02:26 miod Exp $ */ +/* $OpenBSD: exception.S,v 1.36 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2002-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -42,6 +42,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> #ifdef CPU_LOONGSON2 diff --git a/sys/arch/mips64/mips64/exception_tfp.S b/sys/arch/mips64/mips64/exception_tfp.S index 97a85f148c4..f1727d88026 100644 --- a/sys/arch/mips64/mips64/exception_tfp.S +++ b/sys/arch/mips64/mips64/exception_tfp.S @@ -1,4 +1,4 @@ -/* $OpenBSD: exception_tfp.S,v 1.1 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: exception_tfp.S,v 1.2 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -52,6 +52,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/pte.h> #include <machine/regnum.h> #include <machine/cpustate.h> diff --git a/sys/arch/mips64/mips64/fp_emulate.c b/sys/arch/mips64/mips64/fp_emulate.c index c22aa10abd4..1b4a48a806d 100644 --- a/sys/arch/mips64/mips64/fp_emulate.c +++ b/sys/arch/mips64/mips64/fp_emulate.c @@ -1,4 +1,4 @@ -/* $OpenBSD: fp_emulate.c,v 1.7 2012/09/29 19:24:31 miod Exp $ */ +/* $OpenBSD: fp_emulate.c,v 1.8 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2010 Miodrag Vallat. @@ -20,6 +20,9 @@ * Floating Point completion/emulation code (MI softfloat code control engine). * * Supports all MIPS IV COP1 and COP1X floating-point instructions. + * + * Floating-point load and store instructions, as well as branch instructions, + * are only handled if the kernel is compiled with option FPUEMUL. */ #include <sys/param.h> @@ -28,6 +31,7 @@ #include <sys/signalvar.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/fpu.h> #include <machine/frame.h> #include <machine/ieee.h> @@ -67,6 +71,8 @@ fpu_fn3 fpu_cvt_w; fpu_fn3 fpu_div; fpu_fn3 fpu_floor_l; fpu_fn3 fpu_floor_w; +int fpu_int_l(struct trap_frame *, uint, uint, uint, uint, uint); +int fpu_int_w(struct trap_frame *, uint, uint, uint, uint, uint); fpu_fn4 fpu_madd; fpu_fn4 fpu_msub; fpu_fn3 fpu_mov; @@ -86,9 +92,6 @@ fpu_fn3 fpu_sub; fpu_fn3 fpu_trunc_l; fpu_fn3 fpu_trunc_w; -int fpu_int_l(struct trap_frame *, uint, uint, uint, uint, uint); -int fpu_int_w(struct trap_frame *, uint, uint, uint, uint, uint); - /* * Encoding of operand format within opcodes `fmt' and `fmt3' fields. */ @@ -237,6 +240,7 @@ MipsFPTrap(struct trap_frame *tf) #ifdef FPUEMUL skip_insn = 0; #endif + /* FALLTHROUGH */ case OP_MF: case OP_DMF: case OP_CF: @@ -271,6 +275,7 @@ MipsFPTrap(struct trap_frame *tf) * emulation, unless there is no FPU. */ emulate = 1; + break; #endif default: /* diff --git a/sys/arch/mips64/mips64/interrupt.c b/sys/arch/mips64/mips64/interrupt.c index 79fdd1d7e4c..c9325b36813 100644 --- a/sys/arch/mips64/mips64/interrupt.c +++ b/sys/arch/mips64/mips64/interrupt.c @@ -1,4 +1,4 @@ -/* $OpenBSD: interrupt.c,v 1.62 2012/09/29 19:13:15 miod Exp $ */ +/* $OpenBSD: interrupt.c,v 1.63 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -35,6 +35,7 @@ #include <uvm/uvm_extern.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/intr.h> #include <machine/frame.h> diff --git a/sys/arch/mips64/mips64/lcore_access.S b/sys/arch/mips64/mips64/lcore_access.S index c625d29e4e5..82a775862b6 100644 --- a/sys/arch/mips64/mips64/lcore_access.S +++ b/sys/arch/mips64/mips64/lcore_access.S @@ -1,4 +1,4 @@ -/* $OpenBSD: lcore_access.S,v 1.23 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: lcore_access.S,v 1.24 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -31,6 +31,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> #include <machine/trap.h> diff --git a/sys/arch/mips64/mips64/lcore_ddb.S b/sys/arch/mips64/mips64/lcore_ddb.S index 761bfde2271..738b6e85b18 100644 --- a/sys/arch/mips64/mips64/lcore_ddb.S +++ b/sys/arch/mips64/mips64/lcore_ddb.S @@ -1,4 +1,4 @@ -/* $OpenBSD: lcore_ddb.S,v 1.12 2012/09/29 19:02:26 miod Exp $ */ +/* $OpenBSD: lcore_ddb.S,v 1.13 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -31,6 +31,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> #include <machine/trap.h> diff --git a/sys/arch/mips64/mips64/lcore_float.S b/sys/arch/mips64/mips64/lcore_float.S index 7b64a514450..ed4ed6417c8 100644 --- a/sys/arch/mips64/mips64/lcore_float.S +++ b/sys/arch/mips64/mips64/lcore_float.S @@ -1,4 +1,4 @@ -/* $OpenBSD: lcore_float.S,v 1.21 2012/09/29 19:02:26 miod Exp $ */ +/* $OpenBSD: lcore_float.S,v 1.22 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -31,6 +31,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> diff --git a/sys/arch/mips64/mips64/mips64_machdep.c b/sys/arch/mips64/mips64/mips64_machdep.c index ae3eb2f64fc..17eb0386186 100644 --- a/sys/arch/mips64/mips64/mips64_machdep.c +++ b/sys/arch/mips64/mips64/mips64_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: mips64_machdep.c,v 1.7 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: mips64_machdep.c,v 1.8 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2009, 2010, 2012 Miodrag Vallat. @@ -50,6 +50,7 @@ #include <machine/autoconf.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <uvm/uvm.h> diff --git a/sys/arch/mips64/mips64/mips64r2.S b/sys/arch/mips64/mips64/mips64r2.S index cb04f7245d7..f8169550852 100644 --- a/sys/arch/mips64/mips64/mips64r2.S +++ b/sys/arch/mips64/mips64/mips64r2.S @@ -1,4 +1,4 @@ -/* $OpenBSD: mips64r2.S,v 1.1 2012/03/24 20:06:02 miod Exp $ */ +/* $OpenBSD: mips64r2.S,v 1.2 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2011 Miodrag Vallat. @@ -21,7 +21,7 @@ */ #include <machine/asm.h> -#include <machine/cpu.h> +#include <mips64/mips_cpu.h> .set noreorder .set mips64r2 diff --git a/sys/arch/mips64/mips64/sendsig.c b/sys/arch/mips64/mips64/sendsig.c index 8d714646dcf..9bae0f3c79d 100644 --- a/sys/arch/mips64/mips64/sendsig.c +++ b/sys/arch/mips64/mips64/sendsig.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sendsig.c,v 1.18 2012/08/22 13:33:32 okan Exp $ */ +/* $OpenBSD: sendsig.c,v 1.19 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 1990 The Regents of the University of California. @@ -73,6 +73,7 @@ #include <uvm/uvm_extern.h> #include <machine/regnum.h> +#include <mips64/mips_cpu.h> /* * WARNING: code in locore.s assumes the layout shown for sf_signum diff --git a/sys/arch/mips64/mips64/softintr.c b/sys/arch/mips64/mips64/softintr.c index fb9a659a997..7b475c68894 100644 --- a/sys/arch/mips64/mips64/softintr.c +++ b/sys/arch/mips64/mips64/softintr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: softintr.c,v 1.14 2012/09/29 19:24:31 miod Exp $ */ +/* $OpenBSD: softintr.c,v 1.15 2012/10/03 11:18:23 miod Exp $ */ /* $NetBSD: softintr.c,v 1.2 2003/07/15 00:24:39 lukem Exp $ */ /* @@ -43,6 +43,9 @@ #include <machine/atomic.h> #include <machine/intr.h> +#ifdef MULTIPROCESSOR +#include <mips64/mips_cpu.h> +#endif struct soft_intrq soft_intrq[SI_NQUEUES]; diff --git a/sys/arch/mips64/mips64/tlb_tfp.S b/sys/arch/mips64/mips64/tlb_tfp.S index 4fd6b9c0777..50deaa0836d 100644 --- a/sys/arch/mips64/mips64/tlb_tfp.S +++ b/sys/arch/mips64/mips64/tlb_tfp.S @@ -1,4 +1,4 @@ -/* $OpenBSD: tlb_tfp.S,v 1.1 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: tlb_tfp.S,v 1.2 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -19,6 +19,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/pte.h> #include "assym.h" diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S index 8ce1d03e0d6..f8d51f190fc 100644 --- a/sys/arch/mips64/mips64/tlbhandler.S +++ b/sys/arch/mips64/mips64/tlbhandler.S @@ -1,4 +1,4 @@ -/* $OpenBSD: tlbhandler.S,v 1.37 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: tlbhandler.S,v 1.38 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 1995-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -34,6 +34,7 @@ #include <machine/pte.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> #ifdef CPU_LOONGSON2 diff --git a/sys/arch/mips64/mips64/trap.c b/sys/arch/mips64/mips64/trap.c index ddd72637ce8..87def00ef27 100644 --- a/sys/arch/mips64/mips64/trap.c +++ b/sys/arch/mips64/mips64/trap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: trap.c,v 1.87 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: trap.c,v 1.88 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -62,6 +62,7 @@ #include <machine/autoconf.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/fpu.h> #include <machine/frame.h> #include <machine/mips_opcode.h> diff --git a/sys/arch/mips64/mips64/vm_machdep.c b/sys/arch/mips64/mips64/vm_machdep.c index 71b53aa0bfa..3ef50ab20e2 100644 --- a/sys/arch/mips64/mips64/vm_machdep.c +++ b/sys/arch/mips64/mips64/vm_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: vm_machdep.c,v 1.26 2012/09/29 21:37:03 miod Exp $ */ +/* $OpenBSD: vm_machdep.c,v 1.27 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 1988 University of Utah. * Copyright (c) 1992, 1993 @@ -54,7 +54,7 @@ #include <machine/cpu.h> -#include <machine/autoconf.h> +#include <mips64/mips_cpu.h> extern void proc_trampoline(void); /* diff --git a/sys/arch/octeon/dev/octeon_intr.c b/sys/arch/octeon/dev/octeon_intr.c index 1988f9c5f94..8c41ecf2345 100644 --- a/sys/arch/octeon/dev/octeon_intr.c +++ b/sys/arch/octeon/dev/octeon_intr.c @@ -37,6 +37,7 @@ #include <sys/proc.h> #include <mips64/archtype.h> +#include <mips64/mips_cpu.h> #include <machine/autoconf.h> #include <machine/atomic.h> diff --git a/sys/arch/octeon/octeon/locore.S b/sys/arch/octeon/octeon/locore.S index a44d3f93cc4..991ea37d4d2 100644 --- a/sys/arch/octeon/octeon/locore.S +++ b/sys/arch/octeon/octeon/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.4 2012/06/17 11:02:32 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.5 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -31,6 +31,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> diff --git a/sys/arch/octeon/octeon/machdep.c b/sys/arch/octeon/octeon/machdep.c index f6285548c64..337bc68b03f 100644 --- a/sys/arch/octeon/octeon/machdep.c +++ b/sys/arch/octeon/octeon/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.20 2012/09/29 19:11:08 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.21 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2009, 2010 Miodrag Vallat. @@ -73,6 +73,7 @@ #include <machine/autoconf.h> #include <mips64/cache.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/memconf.h> #include <dev/cons.h> diff --git a/sys/arch/sgi/localbus/imc.c b/sys/arch/sgi/localbus/imc.c index de8d914fbbf..c952a5cf946 100644 --- a/sys/arch/sgi/localbus/imc.c +++ b/sys/arch/sgi/localbus/imc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: imc.c,v 1.11 2012/09/29 21:46:02 miod Exp $ */ +/* $OpenBSD: imc.c,v 1.12 2012/10/03 11:18:23 miod Exp $ */ /* $NetBSD: imc.c,v 1.32 2011/07/01 18:53:46 dyoung Exp $ */ /* @@ -56,6 +56,7 @@ #include <machine/autoconf.h> #include <machine/bus.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <sgi/sgi/ip22.h> #include <sgi/localbus/imcreg.h> diff --git a/sys/arch/sgi/localbus/int.c b/sys/arch/sgi/localbus/int.c index 5747821efd1..cb18ef32538 100644 --- a/sys/arch/sgi/localbus/int.c +++ b/sys/arch/sgi/localbus/int.c @@ -1,4 +1,4 @@ -/* $OpenBSD: int.c,v 1.8 2012/09/29 19:24:31 miod Exp $ */ +/* $OpenBSD: int.c,v 1.9 2012/10/03 11:18:23 miod Exp $ */ /* $NetBSD: int.c,v 1.24 2011/07/01 18:53:46 dyoung Exp $ */ /* @@ -45,6 +45,7 @@ #include <machine/autoconf.h> #include <machine/bus.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/intr.h> #include <dev/ic/i8253reg.h> diff --git a/sys/arch/sgi/localbus/macebus.c b/sys/arch/sgi/localbus/macebus.c index ecdab990db0..1ef13d58237 100644 --- a/sys/arch/sgi/localbus/macebus.c +++ b/sys/arch/sgi/localbus/macebus.c @@ -1,4 +1,4 @@ -/* $OpenBSD: macebus.c,v 1.60 2012/09/29 18:54:39 miod Exp $ */ +/* $OpenBSD: macebus.c,v 1.61 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2000-2004 Opsycon AB (www.opsycon.se) @@ -40,6 +40,7 @@ #include <sys/proc.h> #include <mips64/archtype.h> +#include <mips64/mips_cpu.h> #include <machine/autoconf.h> #include <machine/intr.h> diff --git a/sys/arch/sgi/localbus/tcc.c b/sys/arch/sgi/localbus/tcc.c index 517bb6d08b8..e8d3233ffd0 100644 --- a/sys/arch/sgi/localbus/tcc.c +++ b/sys/arch/sgi/localbus/tcc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: tcc.c,v 1.1 2012/09/29 21:46:02 miod Exp $ */ +/* $OpenBSD: tcc.c,v 1.2 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -33,8 +33,7 @@ #include <machine/autoconf.h> #include <machine/bus.h> #include <machine/cpu.h> - -#include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <sgi/sgi/ip22.h> #include <sgi/localbus/tccreg.h> diff --git a/sys/arch/sgi/sgi/ip27_machdep.c b/sys/arch/sgi/sgi/ip27_machdep.c index f43757df18c..395b76c25e2 100644 --- a/sys/arch/sgi/sgi/ip27_machdep.c +++ b/sys/arch/sgi/sgi/ip27_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ip27_machdep.c,v 1.56 2012/09/29 18:54:39 miod Exp $ */ +/* $OpenBSD: ip27_machdep.c,v 1.57 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2008, 2009 Miodrag Vallat. @@ -35,6 +35,7 @@ #include <machine/autoconf.h> #include <machine/bus.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/memconf.h> #include <machine/mnode.h> #include <machine/atomic.h> diff --git a/sys/arch/sgi/sgi/ip30_machdep.c b/sys/arch/sgi/sgi/ip30_machdep.c index 0b48259d4dc..e8ed425192f 100644 --- a/sys/arch/sgi/sgi/ip30_machdep.c +++ b/sys/arch/sgi/sgi/ip30_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ip30_machdep.c,v 1.56 2012/09/29 19:11:08 miod Exp $ */ +/* $OpenBSD: ip30_machdep.c,v 1.57 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2008, 2009 Miodrag Vallat. @@ -33,6 +33,7 @@ #include <machine/autoconf.h> #include <machine/bus.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/memconf.h> #include <uvm/uvm.h> diff --git a/sys/arch/sgi/sgi/ip30_nmi.S b/sys/arch/sgi/sgi/ip30_nmi.S index 18d3cda0251..1402c986a13 100644 --- a/sys/arch/sgi/sgi/ip30_nmi.S +++ b/sys/arch/sgi/sgi/ip30_nmi.S @@ -1,4 +1,4 @@ -/* $OpenBSD: ip30_nmi.S,v 1.5 2012/09/29 19:02:26 miod Exp $ */ +/* $OpenBSD: ip30_nmi.S,v 1.6 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2010 Miodrag Vallat. @@ -18,8 +18,9 @@ #include <machine/asm.h> #include <machine/cpu.h> -#include <machine/cpustate.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> +#include <machine/cpustate.h> #define HW_CPU_NUMBER_REG 0x900000000ff50000 /* HEART_PRID */ diff --git a/sys/arch/sgi/sgi/ip32_machdep.c b/sys/arch/sgi/sgi/ip32_machdep.c index 59144b3462a..7e4ce7863a3 100644 --- a/sys/arch/sgi/sgi/ip32_machdep.c +++ b/sys/arch/sgi/sgi/ip32_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ip32_machdep.c,v 1.19 2012/09/29 19:29:06 miod Exp $ */ +/* $OpenBSD: ip32_machdep.c,v 1.20 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -38,6 +38,7 @@ #include <machine/autoconf.h> #include <machine/bus.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/memconf.h> #include <mips64/arcbios.h> diff --git a/sys/arch/sgi/sgi/locore.S b/sys/arch/sgi/sgi/locore.S index 5a08aacf50e..c3ae327f15d 100644 --- a/sys/arch/sgi/sgi/locore.S +++ b/sys/arch/sgi/sgi/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.14 2012/09/29 19:02:27 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.15 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -31,6 +31,7 @@ #include <machine/param.h> #include <machine/asm.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/regnum.h> #include <machine/cpustate.h> diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c index 9fd00f14fdf..bb0d256c724 100644 --- a/sys/arch/sgi/sgi/machdep.c +++ b/sys/arch/sgi/sgi/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.130 2012/09/29 21:46:02 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.131 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -55,6 +55,7 @@ #include <mips64/cache.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/frame.h> #include <machine/autoconf.h> #include <machine/memconf.h> diff --git a/sys/arch/sgi/xbow/xheart.c b/sys/arch/sgi/xbow/xheart.c index 70d88b08749..65caa7ef1e2 100644 --- a/sys/arch/sgi/xbow/xheart.c +++ b/sys/arch/sgi/xbow/xheart.c @@ -1,4 +1,4 @@ -/* $OpenBSD: xheart.c,v 1.24 2012/09/29 18:54:39 miod Exp $ */ +/* $OpenBSD: xheart.c,v 1.25 2012/10/03 11:18:23 miod Exp $ */ /* * Copyright (c) 2008 Miodrag Vallat. @@ -31,6 +31,7 @@ #include <machine/atomic.h> #include <machine/autoconf.h> #include <machine/cpu.h> +#include <mips64/mips_cpu.h> #include <machine/intr.h> #include <sgi/xbow/xbow.h> |