Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)

Modelled after the arm implementation.  The first consumer would be
__builtin___clear_cache() in libcompiler_rt.

Input from kettenis@ and deraadt@, ok kettenis@

2 files changed, 56 insertions, 1 deletions

diff --git a/sys/arch/riscv64/include/sysarch.h b/sys/arch/riscv64/include/sysarch.h
new file mode 100644
index 00000000000..bbc4dee2b97
--- /dev/null
+++ b/sys/arch/riscv64/include/sysarch.h
@@ -0,0 +1,43 @@
+/*	$OpenBSD: sysarch.h,v 1.1 2021/09/14 12:03:49 jca Exp $	*/
+
+/*
+ * Copyright (c) 2021 Jeremie Courreges-Anglas <jca@openbsd.org>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef	_RISCV64_SYSARCH_H_
+#define	_RISCV64_SYSARCH_H_
+
+/*
+ * Architecture specific syscalls (riscv64)
+ */
+
+#define	RISCV_SYNC_ICACHE	0
+
+struct riscv_sync_icache_args {
+	u_int64_t	addr;		/* Virtual start address */
+	size_t		len;		/* Region size */
+};
+
+#ifndef _KERNEL
+
+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+int	sysarch(int, void *);
+__END_DECLS
+
+#endif	/* _KERNEL */
+
+#endif	/* _RISCV64_SYSARCH_H_ */
diff --git a/sys/arch/riscv64/riscv64/machdep.c b/sys/arch/riscv64/riscv64/machdep.c
index 575e2298601..8e5643fb4cc 100644
--- a/sys/arch/riscv64/riscv64/machdep.c
+++ b/sys/arch/riscv64/riscv64/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.25 2021/07/02 14:50:18 kettenis Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.26 2021/09/14 12:03:49 jca Exp $	*/
 
 /*
  * Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
@@ -44,6 +44,7 @@
 #include <machine/bus.h>
 #include <machine/riscv64var.h>
 #include <machine/sbi.h>
+#include <machine/sysarch.h>
 
 #include <machine/db_machdep.h>
 #include <ddb/db_extern.h>
@@ -514,9 +515,20 @@ sys_sysarch(struct proc *p, void *v, register_t *retval)
 		syscallarg(int) op;
 		syscallarg(void *) parms;
 	} */ *uap = v;
+	struct riscv_sync_icache_args args;
 	int error = 0;
 
 	switch (SCARG(uap, op)) {
+	case RISCV_SYNC_ICACHE:
+		if (SCARG(uap, parms) != NULL)
+			error = copyin(SCARG(uap, parms), &args, sizeof(args));
+		if (error)
+			break;
+		/*
+		 * XXX Validate args.addr and args.len before using them.
+		 */
+		pmap_proc_iflush(p->p_p, (vaddr_t)args.addr, args.len);
+		break;
 	default:
 		error = EINVAL;
 		break;