cpu0: RNG AES AES-CTR SHA1 SHA256 RSA

on fancy new VIA C3 Esther (aka C7) cpus

2 files changed, 42 insertions, 15 deletions

diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index 72cb8067182..66b3c7f69a3 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.320 2005/06/01 16:41:03 mickey Exp $	*/
+/*	$OpenBSD: machdep.c,v 1.321 2005/06/26 19:23:53 deraadt Exp $	*/
 /*	$NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $	*/
 
 /*-
@@ -1198,13 +1198,14 @@ cyrix3_cpu_setup(struct cpu_info *ci)
 		} else
 			val = 0;
 
-		if (val & 0x44/*???*/)
+		if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE))
 			printf("%s:", ci->ci_dev.dv_xname);
+
 		/* Enable RNG if present and disabled */
-		if (val & 0x4) {
+		if (val & C3_CPUID_HAS_RNG) {
 			extern int viac3_rnd_present;
 
-			if (!(val & 0x8)) {
+			if (!(val & C3_CPUID_DO_RNG)) {
 				msreg = rdmsr(0x110B);
 				msreg |= 0x40;
 				wrmsr(0x110B, msreg);
@@ -1212,10 +1213,11 @@ cyrix3_cpu_setup(struct cpu_info *ci)
 			viac3_rnd_present = 1;
 			printf(" RNG");
 		}
+
 		/* Enable AES engine if present and disabled */
-		if (val & 0x40) {
+		if (val & C3_CPUID_HAS_ACE) {
 #ifdef CRYPTO
-			if (!(val & 0x80)) {
+			if (!(val & C3_CPUID_DO_ACE)) {
 				msreg = rdmsr(0x1107);
 				msreg |= (0x01 << 28);
 				wrmsr(0x1107, msreg);
@@ -1224,11 +1226,24 @@ cyrix3_cpu_setup(struct cpu_info *ci)
 #endif /* CRYPTO */
 			printf(" AES");
 		}
-#if 0
+
+		/* Enable ACE2 engine if present and disabled */
+		if (val & C3_CPUID_HAS_ACE2) {
+#ifdef CRYPTO
+			if (!(val & C3_CPUID_DO_ACE2)) {
+				msreg = rdmsr(0x1107);
+				msreg |= (0x01 << 28);
+				wrmsr(0x1107, msreg);
+			}
+			i386_has_xcrypt |= C3_HAS_AESCTR;
+#endif /* CRYPTO */
+			printf(" AES-CTR");
+		}
+
 		/* Enable SHA engine if present and disabled */
-		if (val & 0x40/**/) {
+		if (val & C3_CPUID_HAS_PHE) {
 #ifdef CRYPTO
-			if (!(val & 0x80/**/)) {
+			if (!(val & C3_CPUID_DO_PHE)) {
 				msreg = rdmsr(0x1107);
 				msreg |= (0x01 << 28/**/);
 				wrmsr(0x1107, msreg);
@@ -1237,12 +1252,11 @@ cyrix3_cpu_setup(struct cpu_info *ci)
 #endif /* CRYPTO */
 			printf(" SHA1 SHA256");
 		}
-#endif
-#if 0
+
 		/* Enable MM engine if present and disabled */
-		if (val & 0x40/*???*/) {
+		if (val & C3_CPUID_HAS_PMM) {
 #ifdef CRYPTO
-			if (!(val & 0x80/**/)) {
+			if (!(val & C3_CPUID_DO_PMM)) {
 				msreg = rdmsr(0x1107);
 				msreg |= (0x01 << 28/**/);
 				wrmsr(0x1107, msreg);
@@ -1251,7 +1265,7 @@ cyrix3_cpu_setup(struct cpu_info *ci)
 #endif /* CRYPTO */
 			printf(" RSA");
 		}
-#endif
+
 		printf("\n");
 		break;
 	}
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 850ca2249ad..b3c90521454 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.24 2004/06/25 01:02:53 tom Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.25 2005/06/26 19:24:22 deraadt Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -433,6 +433,19 @@
 #define C3_HAS_AES			1	/* cpu has AES */
 #define C3_HAS_SHA			2	/* cpu has SHA1 & SHA256 */
 #define C3_HAS_MM			4	/* cpu has RSA instructions */
+#define C3_HAS_AESCTR			8	/* cpu has AES-CTR instructions */
+
+/* Centaur Extended Feature flags */
+#define C3_CPUID_HAS_RNG		0x000004
+#define C3_CPUID_DO_RNG			0x000008
+#define C3_CPUID_HAS_ACE		0x000040
+#define C3_CPUID_DO_ACE			0x000080
+#define C3_CPUID_HAS_ACE2		0x000100
+#define C3_CPUID_DO_ACE2		0x000200
+#define C3_CPUID_HAS_PHE		0x000400
+#define C3_CPUID_DO_PHE			0x000800
+#define C3_CPUID_HAS_PMM		0x001000
+#define C3_CPUID_DO_PMM			0x002000
 
 /* VIA C3 xcrypt-* instruction context control options */
 #define	C3_CRYPT_CWLO_ROUND_M		0x0000000f