diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2017-08-06 20:05:25 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2017-08-06 20:05:25 +0000 |
| commit | 93766fc50072ba145a9ce42fdfd80b260681fcba (patch) | |
| tree | 919b92de0c872d1076a0505435934764c73f8995 /sys | |
| parent | 34bef784618026136b1c3cd38421a34f9b3aec2c (diff) | |
Fix TCR definitions to avoid integer overflow. Rename TCR_ASID_16 to TCR_AS
to match the official ARM docs.
ok patrick@, tom@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/arm64/arm64/locore0.S | 4 | ||||
| -rw-r--r-- | sys/arch/arm64/include/armreg.h | 30 |
2 files changed, 21 insertions, 13 deletions
diff --git a/sys/arch/arm64/arm64/locore0.S b/sys/arch/arm64/arm64/locore0.S index cf67a325261..3a71bb4c16f 100644 --- a/sys/arch/arm64/arm64/locore0.S +++ b/sys/arch/arm64/arm64/locore0.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore0.S,v 1.1 2017/06/04 14:10:42 patrick Exp $ */ +/* $OpenBSD: locore0.S,v 1.2 2017/08/06 20:05:24 kettenis Exp $ */ /*- * Copyright (c) 2012-2014 Andrew Turner * All rights reserved. @@ -606,7 +606,7 @@ mair: MAIR_ATTR(0x88, 3) tcr: .quad (TCR_T1SZ(64 - VIRT_BITS) | TCR_T0SZ(64 - 48) | \ - TCR_ASID_16 | TCR_TG1_4K | TCR_CACHE_ATTRS | TCR_SMP_ATTRS) + TCR_AS | TCR_TG1_4K | TCR_CACHE_ATTRS | TCR_SMP_ATTRS) sctlr_set: /* Bits to set */ .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h index 74bd27e983d..4cdbd25c40f 100644 --- a/sys/arch/arm64/include/armreg.h +++ b/sys/arch/arm64/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.4 2017/04/27 10:23:19 kettenis Exp $ */ +/* $OpenBSD: armreg.h,v 1.5 2017/08/06 20:05:24 kettenis Exp $ */ /*- * Copyright (c) 2013, 2014 Andrew Turner * Copyright (c) 2015 The FreeBSD Foundation @@ -444,20 +444,20 @@ #define PSR_N 0x80000000 /* TCR_EL1 - Translation Control Register */ -#define TCR_ASID_16 (1 << 36) +#define TCR_AS (1UL << 36) #define TCR_IPS_SHIFT 32 -#define TCR_IPS_32BIT (0 << TCR_IPS_SHIFT) -#define TCR_IPS_36BIT (1 << TCR_IPS_SHIFT) -#define TCR_IPS_40BIT (2 << TCR_IPS_SHIFT) -#define TCR_IPS_42BIT (3 << TCR_IPS_SHIFT) -#define TCR_IPS_44BIT (4 << TCR_IPS_SHIFT) -#define TCR_IPS_48BIT (5 << TCR_IPS_SHIFT) +#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) +#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) +#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) +#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) +#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) +#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) #define TCR_TG1_SHIFT 30 -#define TCR_TG1_16K (1 << TCR_TG1_SHIFT) -#define TCR_TG1_4K (2 << TCR_TG1_SHIFT) -#define TCR_TG1_64K (3 << TCR_TG1_SHIFT) +#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) +#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) +#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) #define TCR_SH1_SHIFT 28 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) @@ -465,6 +465,14 @@ #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) #define TCR_IRGN1_SHIFT 24 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) + +#define TCR_A1 (1UL << 22) + +#define TCR_TG0_SHIFT 14 +#define TCR_TG0_16K (1UL << TCR_TG0_SHIFT) +#define TCR_TG0_4K (2UL << TCR_TG0_SHIFT) +#define TCR_TG0_64K (3UL << TCR_TG0_SHIFT) + #define TCR_SH0_SHIFT 12 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) #define TCR_ORGN0_SHIFT 10 |