In the upstreamed and official device tree for i.MX8MQ the clocks

have changed.  The clocks are not split into SRC, PRE_DIV, DIV and
CG anymore.  There is only a single index for each clock and we
need to handle them as composite clocks internally.

ok kettenis@

2 files changed, 291 insertions, 342 deletions

diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index 0074ea58061..3a0bb2d6a0a 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.14 2019/03/13 09:49:46 patrick Exp $ */
+/* $OpenBSD: imxccm.c,v 1.15 2019/04/01 08:49:35 patrick Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -203,6 +203,8 @@ struct imxccm_softc {
 	int			sc_ndivs;
 	struct imxccm_mux	*sc_muxs;
 	int			sc_nmuxs;
+	struct imxccm_divider	*sc_predivs;
+	int			sc_npredivs;
 	struct clock_device	sc_cd;
 };
 
@@ -275,6 +277,8 @@ imxccm_attach(struct device *parent, struct device *self, void *aux)
 		sc->sc_ndivs = nitems(imx8mq_divs);
 		sc->sc_muxs = imx8mq_muxs;
 		sc->sc_nmuxs = nitems(imx8mq_muxs);
+		sc->sc_predivs = imx8mq_predivs;
+		sc->sc_npredivs = nitems(imx8mq_predivs);
 	} else if (OF_is_compatible(sc->sc_node, "fsl,imx7d-ccm")) {
 		sc->sc_gates = imx7d_gates;
 		sc->sc_ngates = nitems(imx7d_gates);
@@ -748,10 +752,10 @@ imxccm_imx8mq_usb(struct imxccm_softc *sc, uint32_t idx)
 	case 0:
 		return clock_get_frequency(sc->sc_node, "osc_25m");
 	case 1:
-		if (idx == IMX8MQ_CLK_USB_CORE_REF_SRC ||
-		    idx == IMX8MQ_CLK_USB_PHY_REF_SRC)
+		if (idx == IMX8MQ_CLK_USB_CORE_REF ||
+		    idx == IMX8MQ_CLK_USB_PHY_REF)
 			return 100 * 1000 * 1000; /* sys1_pll_100m */
-		if (idx == IMX8MQ_CLK_USB_BUS_SRC)
+		if (idx == IMX8MQ_CLK_USB_BUS)
 			return 500 * 1000 * 1000; /* sys2_pll_500m */
 		printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
 		return 0;
@@ -1043,7 +1047,8 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 {
 	struct imxccm_softc *sc = cookie;
 	uint32_t idx = cells[0];
-	uint32_t div, parent;
+	uint32_t div, pre, reg, parent;
+	uint32_t freq;
 
 	/* Dummy clock. */
 	if (idx == 0)
@@ -1064,40 +1069,66 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 
 	if (sc->sc_gates == imx8mq_gates) {
 		switch (idx) {
-		case IMX8MQ_ARM_PLL:
-			return imxccm_imx8mq_get_pll(sc, idx);
-		case IMX8MQ_CLK_A53_SRC:
+		case IMX8MQ_CLK_ARM:
 			parent = IMX8MQ_ARM_PLL;
 			return imxccm_get_frequency(sc, &parent);
-		case IMX8MQ_CLK_ENET_AXI_SRC:
-			return imxccm_imx8mq_enet(sc, idx);
-		case IMX8MQ_CLK_I2C1_SRC:
-		case IMX8MQ_CLK_I2C2_SRC:
-		case IMX8MQ_CLK_I2C3_SRC:
-		case IMX8MQ_CLK_I2C4_SRC:
-			return imxccm_imx8mq_i2c(sc, idx);
-		case IMX8MQ_CLK_UART1_SRC:
-		case IMX8MQ_CLK_UART2_SRC:
-		case IMX8MQ_CLK_UART3_SRC:
-		case IMX8MQ_CLK_UART4_SRC:
-			return imxccm_imx8mq_uart(sc, idx);
-		case IMX8MQ_CLK_USDHC1_SRC:
-		case IMX8MQ_CLK_USDHC2_SRC:
-			return imxccm_imx8mq_usdhc(sc, idx);
-		case IMX8MQ_CLK_USB_BUS_SRC:
-		case IMX8MQ_CLK_USB_CORE_REF_SRC:
-		case IMX8MQ_CLK_USB_PHY_REF_SRC:
-			return imxccm_imx8mq_usb(sc, idx);
-		case IMX8MQ_CLK_ECSPI1_SRC:
-		case IMX8MQ_CLK_ECSPI2_SRC:
-		case IMX8MQ_CLK_ECSPI3_SRC:
-			return imxccm_imx8mq_ecspi(sc, idx);
-		case IMX8MQ_CLK_PWM1_SRC:
-		case IMX8MQ_CLK_PWM2_SRC:
-		case IMX8MQ_CLK_PWM3_SRC:
-		case IMX8MQ_CLK_PWM4_SRC:
-			return imxccm_imx8mq_pwm(sc, idx);
+		case IMX8MQ_ARM_PLL:
+			return imxccm_imx8mq_get_pll(sc, idx);
+		}
+
+		/* These are composite clocks. */
+		if (idx < sc->sc_ngates && sc->sc_gates[idx].reg &&
+		    idx < sc->sc_ndivs && sc->sc_divs[idx].reg &&
+		    idx < sc->sc_npredivs && sc->sc_predivs[idx].reg) {
+			switch (idx) {
+			case IMX8MQ_CLK_ENET_AXI:
+				freq = imxccm_imx8mq_enet(sc, idx);
+				break;
+			case IMX8MQ_CLK_I2C1:
+			case IMX8MQ_CLK_I2C2:
+			case IMX8MQ_CLK_I2C3:
+			case IMX8MQ_CLK_I2C4:
+				freq = imxccm_imx8mq_i2c(sc, idx);
+				break;
+			case IMX8MQ_CLK_UART1:
+			case IMX8MQ_CLK_UART2:
+			case IMX8MQ_CLK_UART3:
+			case IMX8MQ_CLK_UART4:
+				freq = imxccm_imx8mq_uart(sc, idx);
+				break;
+			case IMX8MQ_CLK_USDHC1:
+			case IMX8MQ_CLK_USDHC2:
+				freq = imxccm_imx8mq_usdhc(sc, idx);
+				break;
+			case IMX8MQ_CLK_USB_BUS:
+			case IMX8MQ_CLK_USB_CORE_REF:
+			case IMX8MQ_CLK_USB_PHY_REF:
+				freq = imxccm_imx8mq_usb(sc, idx);
+				break;
+			case IMX8MQ_CLK_ECSPI1:
+			case IMX8MQ_CLK_ECSPI2:
+			case IMX8MQ_CLK_ECSPI3:
+				freq = imxccm_imx8mq_ecspi(sc, idx);
+				break;
+			case IMX8MQ_CLK_PWM1:
+			case IMX8MQ_CLK_PWM2:
+			case IMX8MQ_CLK_PWM3:
+			case IMX8MQ_CLK_PWM4:
+				freq = imxccm_imx8mq_pwm(sc, idx);
+				break;
+			default:
+				printf("%s: 0x%08x\n", __func__, idx);
+				return 0;
+			}
+
+			reg = HREAD4(sc, sc->sc_divs[idx].reg);
+			div = reg >> sc->sc_divs[idx].shift;
+			div = div & sc->sc_divs[idx].mask;
+			pre = reg >> sc->sc_predivs[idx].shift;
+			pre = pre & sc->sc_predivs[idx].mask;
+			return ((freq / (pre + 1)) / (div + 1));
 		}
+
 	} else if (sc->sc_gates == imx7d_gates) {
 		switch (idx) {
 		case IMX7D_ENET_AXI_ROOT_SRC:
@@ -1171,7 +1202,7 @@ imxccm_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)
 
 	if (sc->sc_divs == imx8mq_divs) {
 		switch (idx) {
-		case IMX8MQ_CLK_A53_DIV:
+		case IMX8MQ_CLK_ARM:
 			parent = IMX8MQ_CLK_A53_SRC;
 			return imxccm_set_frequency(cookie, &parent, freq);
 		case IMX8MQ_CLK_A53_SRC:
@@ -1185,21 +1216,20 @@ imxccm_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)
 			pcells[1] = IMX8MQ_ARM_PLL_OUT;
 			imxccm_set_parent(cookie, &idx, pcells);
 			return ret;
-		case IMX8MQ_CLK_USB_BUS_SRC:
-		case IMX8MQ_CLK_USB_CORE_REF_SRC:
-		case IMX8MQ_CLK_USB_PHY_REF_SRC:
+		case IMX8MQ_CLK_USB_BUS:
+		case IMX8MQ_CLK_USB_CORE_REF:
+		case IMX8MQ_CLK_USB_PHY_REF:
 			if (imxccm_get_frequency(sc, cells) != freq)
 				break;
 			return 0;
-		case IMX8MQ_CLK_USDHC1_DIV:
-			parent = sc->sc_divs[idx].parent;
-			if (imxccm_get_frequency(sc, &parent) != freq)
-				break;
-			imxccm_enable(cookie, &parent, 1);
+		case IMX8MQ_CLK_USDHC1:
+			imxccm_enable(cookie, &idx, 1);
 			reg = HREAD4(sc, sc->sc_divs[idx].reg);
 			reg &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);
-			reg |= (0x0 << sc->sc_divs[idx].shift);
 			HWRITE4(sc, sc->sc_divs[idx].reg, reg);
+			reg = HREAD4(sc, sc->sc_predivs[idx].reg);
+			reg &= ~(sc->sc_predivs[idx].mask << sc->sc_predivs[idx].shift);
+			HWRITE4(sc, sc->sc_predivs[idx].reg, reg);
 			return 0;
 		}
 	} else if (sc->sc_divs == imx7d_divs) {
@@ -1258,7 +1288,7 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)
 				mux |= (0x4 << sc->sc_muxs[idx].shift);
 			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
 			return 0;
-		case IMX8MQ_CLK_USB_BUS_SRC:
+		case IMX8MQ_CLK_USB_BUS:
 			if (pidx != IMX8MQ_SYS2_PLL_500M)
 				break;
 			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
@@ -1266,8 +1296,8 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)
 			mux |= (0x1 << sc->sc_muxs[idx].shift);
 			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
 			return 0;
-		case IMX8MQ_CLK_USB_CORE_REF_SRC:
-		case IMX8MQ_CLK_USB_PHY_REF_SRC:
+		case IMX8MQ_CLK_USB_CORE_REF:
+		case IMX8MQ_CLK_USB_PHY_REF:
 			if (pidx != IMX8MQ_SYS1_PLL_100M)
 				break;
 			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
@@ -1275,8 +1305,8 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)
 			mux |= (0x1 << sc->sc_muxs[idx].shift);
 			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
 			return 0;
-		case IMX8MQ_CLK_PCIE1_CTRL_SRC:
-		case IMX8MQ_CLK_PCIE2_CTRL_SRC:
+		case IMX8MQ_CLK_PCIE1_CTRL:
+		case IMX8MQ_CLK_PCIE2_CTRL:
 			if (pidx != IMX8MQ_SYS2_PLL_250M)
 				break;
 			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
@@ -1284,8 +1314,8 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)
 			mux |= (0x1 << sc->sc_muxs[idx].shift);
 			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
 			return 0;
-		case IMX8MQ_CLK_PCIE1_PHY_SRC:
-		case IMX8MQ_CLK_PCIE2_PHY_SRC:
+		case IMX8MQ_CLK_PCIE1_PHY:
+		case IMX8MQ_CLK_PCIE2_PHY:
 			if (pidx != IMX8MQ_SYS2_PLL_100M)
 				break;
 			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h
index ea865f6bd96..71420524dfe 100644
--- a/sys/dev/fdt/imxccm_clocks.h
+++ b/sys/dev/fdt/imxccm_clocks.h
@@ -303,303 +303,222 @@ struct imxccm_mux imx7d_muxs[] = {
 #define IMX8MQ_CLK_A53_SRC		0x58
 #define IMX8MQ_CLK_A53_CG		0x59
 #define IMX8MQ_CLK_A53_DIV		0x5a
-#define IMX8MQ_CLK_ENET_AXI_SRC		0x6b
-#define IMX8MQ_CLK_ENET_AXI_CG		0x6c
-#define IMX8MQ_CLK_ENET_AXI_PRE_DIV	0x6d
-#define IMX8MQ_CLK_ENET_AXI_DIV		0x6e
-#define IMX8MQ_CLK_USB_BUS_SRC		0x83
-#define IMX8MQ_CLK_USB_BUS_CG		0x84
-#define IMX8MQ_CLK_USB_BUS_PRE_DIV	0x85
-#define IMX8MQ_CLK_PCIE1_CTRL_SRC	0xb7
-#define IMX8MQ_CLK_PCIE1_CTRL_CG	0xb8
-#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV	0xb9
-#define IMX8MQ_CLK_PCIE1_CTRL_DIV	0xba
-#define IMX8MQ_CLK_PCIE1_PHY_SRC	0xbb
-#define IMX8MQ_CLK_PCIE1_PHY_CG		0xbc
-#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV	0xbd
-#define IMX8MQ_CLK_PCIE1_PHY_DIV	0xbe
-#define IMX8MQ_CLK_PCIE1_AUX_SRC	0xbf
-#define IMX8MQ_CLK_PCIE1_AUX_CG		0xc0
-#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV	0xc1
-#define IMX8MQ_CLK_PCIE1_AUX_DIV	0xc2
-#define IMX8MQ_CLK_USB_BUS_DIV		0x86
-#define IMX8MQ_CLK_ENET_REF_SRC		0xeb
-#define IMX8MQ_CLK_ENET_REF_CG		0xec
-#define IMX8MQ_CLK_ENET_REF_PRE_DIV	0xed
-#define IMX8MQ_CLK_ENET_REF_DIV		0xee
-#define IMX8MQ_CLK_ENET_TIMER_SRC	0xef
-#define IMX8MQ_CLK_ENET_TIMER_CG	0xf0
-#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV	0xf1
-#define IMX8MQ_CLK_ENET_TIMER_DIV	0xf2
-#define IMX8MQ_CLK_ENET_PHY_REF_SRC	0xf3
-#define IMX8MQ_CLK_ENET_PHY_REF_CG	0xf4
-#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV	0xf5
-#define IMX8MQ_CLK_ENET_PHY_REF_DIV	0xf6
-#define IMX8MQ_CLK_USDHC1_SRC		0xff
-#define IMX8MQ_CLK_USDHC1_CG		0x100
-#define IMX8MQ_CLK_USDHC1_PRE_DIV	0x101
-#define IMX8MQ_CLK_USDHC1_DIV		0x102
-#define IMX8MQ_CLK_USDHC2_SRC		0x103
-#define IMX8MQ_CLK_USDHC2_CG		0x104
-#define IMX8MQ_CLK_USDHC2_PRE_DIV	0x105
-#define IMX8MQ_CLK_USDHC2_DIV		0x106
-#define IMX8MQ_CLK_I2C1_SRC		0x107
-#define IMX8MQ_CLK_I2C1_CG		0x108
-#define IMX8MQ_CLK_I2C1_PRE_DIV		0x109
-#define IMX8MQ_CLK_I2C1_DIV		0x10a
-#define IMX8MQ_CLK_I2C2_SRC		0x10b
-#define IMX8MQ_CLK_I2C2_CG		0x10c
-#define IMX8MQ_CLK_I2C2_PRE_DIV		0x10d
-#define IMX8MQ_CLK_I2C2_DIV		0x10e
-#define IMX8MQ_CLK_I2C3_SRC		0x10f
-#define IMX8MQ_CLK_I2C3_CG		0x110
-#define IMX8MQ_CLK_I2C3_PRE_DIV		0x111
-#define IMX8MQ_CLK_I2C3_DIV		0x112
-#define IMX8MQ_CLK_I2C4_SRC		0x113
-#define IMX8MQ_CLK_I2C4_CG		0x114
-#define IMX8MQ_CLK_I2C4_PRE_DIV		0x115
-#define IMX8MQ_CLK_I2C4_DIV		0x116
-#define IMX8MQ_CLK_UART1_SRC		0x117
-#define IMX8MQ_CLK_UART1_CG		0x118
-#define IMX8MQ_CLK_UART1_PRE_DIV	0x119
-#define IMX8MQ_CLK_UART1_DIV		0x11a
-#define IMX8MQ_CLK_UART2_SRC		0x11b
-#define IMX8MQ_CLK_UART2_CG		0x11c
-#define IMX8MQ_CLK_UART2_PRE_DIV	0x11d
-#define IMX8MQ_CLK_UART2_DIV		0x11e
-#define IMX8MQ_CLK_UART3_SRC		0x11f
-#define IMX8MQ_CLK_UART3_CG		0x120
-#define IMX8MQ_CLK_UART3_PRE_DIV	0x121
-#define IMX8MQ_CLK_UART3_DIV		0x122
-#define IMX8MQ_CLK_UART4_SRC		0x123
-#define IMX8MQ_CLK_UART4_CG		0x124
-#define IMX8MQ_CLK_UART4_PRE_DIV	0x125
-#define IMX8MQ_CLK_UART4_DIV		0x126
-#define IMX8MQ_CLK_USB_CORE_REF_SRC	0x127
-#define IMX8MQ_CLK_USB_CORE_REF_CG	0x128
-#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV	0x129
-#define IMX8MQ_CLK_USB_CORE_REF_DIV	0x12a
-#define IMX8MQ_CLK_USB_PHY_REF_SRC	0x12b
-#define IMX8MQ_CLK_USB_PHY_REF_CG	0x12c
-#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV	0x12d
-#define IMX8MQ_CLK_USB_PHY_REF_DIV	0x12e
-#define IMX8MQ_CLK_ECSPI1_SRC		0x12f
-#define IMX8MQ_CLK_ECSPI1_CG		0x130
-#define IMX8MQ_CLK_ECSPI1_PRE_DIV	0x131
-#define IMX8MQ_CLK_ECSPI1_DIV		0x132
-#define IMX8MQ_CLK_ECSPI2_SRC		0x133
-#define IMX8MQ_CLK_ECSPI2_CG		0x134
-#define IMX8MQ_CLK_ECSPI2_PRE_DIV	0x135
-#define IMX8MQ_CLK_ECSPI2_DIV		0x136
-#define IMX8MQ_CLK_PWM1_SRC		0x137
-#define IMX8MQ_CLK_PWM1_CG		0x138
-#define IMX8MQ_CLK_PWM1_PRE_DIV		0x139
-#define IMX8MQ_CLK_PWM1_DIV		0x13a
-#define IMX8MQ_CLK_PWM2_SRC		0x13b
-#define IMX8MQ_CLK_PWM2_CG		0x13c
-#define IMX8MQ_CLK_PWM2_PRE_DIV		0x13d
-#define IMX8MQ_CLK_PWM2_DIV		0x13e
-#define IMX8MQ_CLK_PWM3_SRC		0x13f
-#define IMX8MQ_CLK_PWM3_CG		0x140
-#define IMX8MQ_CLK_PWM3_PRE_DIV		0x141
-#define IMX8MQ_CLK_PWM3_DIV		0x142
-#define IMX8MQ_CLK_PWM4_SRC		0x143
-#define IMX8MQ_CLK_PWM4_CG		0x144
-#define IMX8MQ_CLK_PWM4_PRE_DIV		0x145
-#define IMX8MQ_CLK_PWM4_DIV		0x146
-#define IMX8MQ_CLK_PCIE2_CTRL_SRC	0x17b
-#define IMX8MQ_CLK_PCIE2_CTRL_CG	0x17c
-#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV	0x17d
-#define IMX8MQ_CLK_PCIE2_CTRL_DIV	0x17e
-#define IMX8MQ_CLK_PCIE2_PHY_SRC	0x17f
-#define IMX8MQ_CLK_PCIE2_PHY_CG		0x180
-#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV	0x181
-#define IMX8MQ_CLK_PCIE2_PHY_DIV	0x182
-#define IMX8MQ_CLK_PCIE2_AUX_SRC	0x183
-#define IMX8MQ_CLK_PCIE2_AUX_CG		0x184
-#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV	0x185
-#define IMX8MQ_CLK_PCIE2_AUX_DIV	0x186
-#define IMX8MQ_CLK_ECSPI3_SRC		0x187
-#define IMX8MQ_CLK_ECSPI3_CG		0x188
-#define IMX8MQ_CLK_ECSPI3_PRE_DIV	0x189
-#define IMX8MQ_CLK_ECSPI3_DIV		0x18a
-#define IMX8MQ_CLK_ECSPI1_ROOT		0x18d
-#define IMX8MQ_CLK_ECSPI2_ROOT		0x18e
-#define IMX8MQ_CLK_ECSPI3_ROOT		0x18f
-#define IMX8MQ_CLK_ENET1_ROOT		0x190
-#define IMX8MQ_CLK_I2C1_ROOT		0x192
-#define IMX8MQ_CLK_I2C2_ROOT		0x193
-#define IMX8MQ_CLK_I2C3_ROOT		0x194
-#define IMX8MQ_CLK_I2C4_ROOT		0x195
-#define IMX8MQ_CLK_PCIE1_ROOT		0x197
-#define IMX8MQ_CLK_PCIE2_ROOT		0x198
-#define IMX8MQ_CLK_PWM1_ROOT		0x199
-#define IMX8MQ_CLK_PWM2_ROOT		0x19a
-#define IMX8MQ_CLK_PWM3_ROOT		0x19b
-#define IMX8MQ_CLK_PWM4_ROOT		0x19c
-#define IMX8MQ_CLK_UART1_ROOT		0x1a4
-#define IMX8MQ_CLK_UART2_ROOT		0x1a5
-#define IMX8MQ_CLK_UART3_ROOT		0x1a6
-#define IMX8MQ_CLK_UART4_ROOT		0x1a7
-#define IMX8MQ_CLK_USB1_CTRL_ROOT	0x1a8
-#define IMX8MQ_CLK_USB2_CTRL_ROOT	0x1a9
-#define IMX8MQ_CLK_USB1_PHY_ROOT	0x1aa
-#define IMX8MQ_CLK_USB2_PHY_ROOT	0x1ab
-#define IMX8MQ_CLK_USDHC1_ROOT		0x1ac
-#define IMX8MQ_CLK_USDHC2_ROOT		0x1ad
+#define IMX8MQ_CLK_ENET_AXI		0x68
+#define IMX8MQ_CLK_NAND_USDHC_BUS	0x69
+#define IMX8MQ_CLK_USB_BUS		0x6e
+#define IMX8MQ_CLK_PCIE1_CTRL		0x7c
+#define IMX8MQ_CLK_PCIE1_PHY		0x7d
+#define IMX8MQ_CLK_PCIE1_AUX		0x7e
+#define IMX8MQ_CLK_ENET_REF		0x89
+#define IMX8MQ_CLK_ENET_TIMER		0x8a
+#define IMX8MQ_CLK_ENET_PHY_REF		0x8b
+#define IMX8MQ_CLK_USDHC1		0x8e
+#define IMX8MQ_CLK_USDHC2		0x8f
+#define IMX8MQ_CLK_I2C1			0x90
+#define IMX8MQ_CLK_I2C2			0x91
+#define IMX8MQ_CLK_I2C3			0x92
+#define IMX8MQ_CLK_I2C4			0x93
+#define IMX8MQ_CLK_UART1		0x94
+#define IMX8MQ_CLK_UART2		0x95
+#define IMX8MQ_CLK_UART3		0x96
+#define IMX8MQ_CLK_UART4		0x97
+#define IMX8MQ_CLK_USB_CORE_REF		0x98
+#define IMX8MQ_CLK_USB_PHY_REF		0x99
+#define IMX8MQ_CLK_ECSPI1		0x9a
+#define IMX8MQ_CLK_ECSPI2		0x9b
+#define IMX8MQ_CLK_PWM1			0x9c
+#define IMX8MQ_CLK_PWM2			0x9d
+#define IMX8MQ_CLK_PWM3			0x9e
+#define IMX8MQ_CLK_PWM4			0x9f
+#define IMX8MQ_CLK_PCIE2_CTRL		0xad
+#define IMX8MQ_CLK_PCIE2_PHY		0xae
+#define IMX8MQ_CLK_PCIE2_AUX		0xaf
+#define IMX8MQ_CLK_ECSPI3		0xb0
+#define IMX8MQ_CLK_ECSPI1_ROOT		0xb3
+#define IMX8MQ_CLK_ECSPI2_ROOT		0xb4
+#define IMX8MQ_CLK_ECSPI3_ROOT		0xb5
+#define IMX8MQ_CLK_ENET1_ROOT		0xb6
+#define IMX8MQ_CLK_I2C1_ROOT		0xb8
+#define IMX8MQ_CLK_I2C2_ROOT		0xb9
+#define IMX8MQ_CLK_I2C3_ROOT		0xba
+#define IMX8MQ_CLK_I2C4_ROOT		0xbb
+#define IMX8MQ_CLK_PCIE1_ROOT		0xbd
+#define IMX8MQ_CLK_PCIE2_ROOT		0xbe
+#define IMX8MQ_CLK_PWM1_ROOT		0xbf
+#define IMX8MQ_CLK_PWM2_ROOT		0xc0
+#define IMX8MQ_CLK_PWM3_ROOT		0xc1
+#define IMX8MQ_CLK_PWM4_ROOT		0xc2
+#define IMX8MQ_CLK_UART1_ROOT		0xca
+#define IMX8MQ_CLK_UART2_ROOT		0xcb
+#define IMX8MQ_CLK_UART3_ROOT		0xcc
+#define IMX8MQ_CLK_UART4_ROOT		0xcd
+#define IMX8MQ_CLK_USB1_CTRL_ROOT	0xce
+#define IMX8MQ_CLK_USB2_CTRL_ROOT	0xcf
+#define IMX8MQ_CLK_USB1_PHY_ROOT	0xd0
+#define IMX8MQ_CLK_USB2_PHY_ROOT	0xd1
+#define IMX8MQ_CLK_USDHC1_ROOT		0xd2
+#define IMX8MQ_CLK_USDHC2_ROOT		0xd3
+#define IMX8MQ_CLK_ARM			0x102
 
 struct imxccm_gate imx8mq_gates[] = {
-	[IMX8MQ_CLK_A53_CG] = { 0x8000, 14, IMX8MQ_CLK_A53_SRC },
-	[IMX8MQ_CLK_ENET_AXI_CG] = { 0x8880, 14, IMX8MQ_CLK_ENET_AXI_SRC },
-	[IMX8MQ_CLK_USB_BUS_CG] = { 0x8b80, 14, IMX8MQ_CLK_USB_BUS_SRC },
-	[IMX8MQ_CLK_PCIE1_CTRL_CG] = { 0xa300, 14, IMX8MQ_CLK_PCIE1_CTRL_SRC },
-	[IMX8MQ_CLK_PCIE1_PHY_CG] = { 0xa380, 14, IMX8MQ_CLK_PCIE1_PHY_SRC },
-	[IMX8MQ_CLK_PCIE1_AUX_CG] = { 0xa400, 14, IMX8MQ_CLK_PCIE1_AUX_SRC },
-	[IMX8MQ_CLK_ENET_REF_CG] = { 0xa980, 14, IMX8MQ_CLK_ENET_REF_SRC },
-	[IMX8MQ_CLK_ENET_TIMER_CG] = { 0xaa00, 14, IMX8MQ_CLK_ENET_TIMER_SRC },
-	[IMX8MQ_CLK_ENET_PHY_REF_CG] = { 0xaa80, 14, IMX8MQ_CLK_ENET_PHY_REF_SRC },
-	[IMX8MQ_CLK_USDHC1_CG] = { 0xac00, 14, IMX8MQ_CLK_USDHC1_SRC },
-	[IMX8MQ_CLK_USDHC2_CG] = { 0xac80, 14, IMX8MQ_CLK_USDHC2_SRC },
-	[IMX8MQ_CLK_I2C1_CG] = { 0xad00, 14, IMX8MQ_CLK_I2C1_SRC },
-	[IMX8MQ_CLK_I2C2_CG] = { 0xad80, 14, IMX8MQ_CLK_I2C2_SRC },
-	[IMX8MQ_CLK_I2C3_CG] = { 0xae00, 14, IMX8MQ_CLK_I2C3_SRC },
-	[IMX8MQ_CLK_I2C4_CG] = { 0xae80, 14, IMX8MQ_CLK_I2C4_SRC },
-	[IMX8MQ_CLK_UART1_CG] = { 0xaf00, 14, IMX8MQ_CLK_UART1_SRC },
-	[IMX8MQ_CLK_UART2_CG] = { 0xaf80, 14, IMX8MQ_CLK_UART2_SRC },
-	[IMX8MQ_CLK_UART3_CG] = { 0xb000, 14, IMX8MQ_CLK_UART3_SRC },
-	[IMX8MQ_CLK_UART4_CG] = { 0xb080, 14, IMX8MQ_CLK_UART4_SRC },
-	[IMX8MQ_CLK_USB_CORE_REF_CG] = { 0xb100, 14, IMX8MQ_CLK_USB_CORE_REF_SRC },
-	[IMX8MQ_CLK_USB_PHY_REF_CG] = { 0xb180, 14, IMX8MQ_CLK_USB_PHY_REF_SRC },
-	[IMX8MQ_CLK_ECSPI1_CG] = { 0xb280, 14, IMX8MQ_CLK_ECSPI1_SRC },
-	[IMX8MQ_CLK_ECSPI2_CG] = { 0xb300, 14, IMX8MQ_CLK_ECSPI2_SRC },
-	[IMX8MQ_CLK_PWM1_CG] = { 0xb380, 14, IMX8MQ_CLK_PWM1_SRC },
-	[IMX8MQ_CLK_PWM2_CG] = { 0xb400, 14, IMX8MQ_CLK_PWM2_SRC },
-	[IMX8MQ_CLK_PWM3_CG] = { 0xb480, 14, IMX8MQ_CLK_PWM3_SRC },
-	[IMX8MQ_CLK_PWM4_CG] = { 0xb500, 14, IMX8MQ_CLK_PWM4_SRC },
-	[IMX8MQ_CLK_PCIE2_CTRL_CG] = { 0xc000, 14, IMX8MQ_CLK_PCIE2_CTRL_SRC },
-	[IMX8MQ_CLK_PCIE2_PHY_CG] = { 0xc080, 14, IMX8MQ_CLK_PCIE2_PHY_SRC },
-	[IMX8MQ_CLK_PCIE2_AUX_CG] = { 0xc100, 14, IMX8MQ_CLK_PCIE2_AUX_SRC },
-	[IMX8MQ_CLK_ECSPI3_CG] = { 0xc180, 14, IMX8MQ_CLK_ECSPI3_SRC },
-	[IMX8MQ_CLK_ECSPI1_ROOT] = { 0x4070, 0, IMX8MQ_CLK_ECSPI1_DIV },
-	[IMX8MQ_CLK_ECSPI2_ROOT] = { 0x4080, 0, IMX8MQ_CLK_ECSPI2_DIV },
-	[IMX8MQ_CLK_ECSPI3_ROOT] = { 0x4090, 0, IMX8MQ_CLK_ECSPI3_DIV },
-	[IMX8MQ_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MQ_CLK_ENET_AXI_DIV },
-	[IMX8MQ_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MQ_CLK_I2C1_DIV },
-	[IMX8MQ_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MQ_CLK_I2C2_DIV },
-	[IMX8MQ_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MQ_CLK_I2C3_DIV },
-	[IMX8MQ_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MQ_CLK_I2C4_DIV },
-	[IMX8MQ_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MQ_CLK_PCIE1_CTRL_DIV },
-	[IMX8MQ_CLK_PCIE2_ROOT] = { 0x4640, 0, IMX8MQ_CLK_PCIE2_CTRL_DIV },
-	[IMX8MQ_CLK_PWM1_ROOT] = { 0x4280, 0, IMX8MQ_CLK_PWM1_DIV },
-	[IMX8MQ_CLK_PWM2_ROOT] = { 0x4290, 0, IMX8MQ_CLK_PWM2_DIV },
-	[IMX8MQ_CLK_PWM3_ROOT] = { 0x42a0, 0, IMX8MQ_CLK_PWM3_DIV },
-	[IMX8MQ_CLK_PWM4_ROOT] = { 0x42b0, 0, IMX8MQ_CLK_PWM4_DIV },
-	[IMX8MQ_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MQ_CLK_UART1_DIV },
-	[IMX8MQ_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MQ_CLK_UART2_DIV },
-	[IMX8MQ_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MQ_CLK_UART3_DIV },
-	[IMX8MQ_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MQ_CLK_UART4_DIV },
-	[IMX8MQ_CLK_USB1_CTRL_ROOT] = { 0x44d0, 0, IMX8MQ_CLK_USB_CORE_REF_DIV },
-	[IMX8MQ_CLK_USB2_CTRL_ROOT] = { 0x44e0, 0, IMX8MQ_CLK_USB_CORE_REF_DIV },
-	[IMX8MQ_CLK_USB1_PHY_ROOT] = { 0x44f0, 0, IMX8MQ_CLK_USB_PHY_REF_DIV },
-	[IMX8MQ_CLK_USB2_PHY_ROOT] = { 0x4500, 0, IMX8MQ_CLK_USB_PHY_REF_DIV },
-	[IMX8MQ_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MQ_CLK_USDHC1_DIV },
-	[IMX8MQ_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MQ_CLK_USDHC2_DIV },
+	[IMX8MQ_CLK_A53_CG] = { 0x8000, 14 },
+	[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 14 },
+	[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 14 },
+	[IMX8MQ_CLK_USB_BUS] = { 0x8b80, 14 },
+	[IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 14 },
+	[IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 14 },
+	[IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 14 },
+	[IMX8MQ_CLK_ENET_REF] = { 0xa980, 14 },
+	[IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 14 },
+	[IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 14 },
+	[IMX8MQ_CLK_USDHC1] = { 0xac00, 14 },
+	[IMX8MQ_CLK_USDHC2] = { 0xac80, 14 },
+	[IMX8MQ_CLK_I2C1] = { 0xad00, 14 },
+	[IMX8MQ_CLK_I2C2] = { 0xad80, 14 },
+	[IMX8MQ_CLK_I2C3] = { 0xae00, 14 },
+	[IMX8MQ_CLK_I2C4] = { 0xae80, 14 },
+	[IMX8MQ_CLK_UART1] = { 0xaf00, 14 },
+	[IMX8MQ_CLK_UART2] = { 0xaf80, 14 },
+	[IMX8MQ_CLK_UART3] = { 0xb000, 14 },
+	[IMX8MQ_CLK_UART4] = { 0xb080, 14 },
+	[IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 14 },
+	[IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 14 },
+	[IMX8MQ_CLK_ECSPI1] = { 0xb280, 14 },
+	[IMX8MQ_CLK_ECSPI2] = { 0xb300, 14 },
+	[IMX8MQ_CLK_PWM1] = { 0xb380, 14 },
+	[IMX8MQ_CLK_PWM2] = { 0xb400, 14 },
+	[IMX8MQ_CLK_PWM3] = { 0xb480, 14 },
+	[IMX8MQ_CLK_PWM4] = { 0xb500, 14 },
+	[IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 14 },
+	[IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 14 },
+	[IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 14 },
+	[IMX8MQ_CLK_ECSPI3] = { 0xc180, 14 },
+	[IMX8MQ_CLK_ECSPI1_ROOT] = { 0x4070, 0, IMX8MQ_CLK_ECSPI1 },
+	[IMX8MQ_CLK_ECSPI2_ROOT] = { 0x4080, 0, IMX8MQ_CLK_ECSPI2 },
+	[IMX8MQ_CLK_ECSPI3_ROOT] = { 0x4090, 0, IMX8MQ_CLK_ECSPI3 },
+	[IMX8MQ_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MQ_CLK_ENET_AXI },
+	[IMX8MQ_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MQ_CLK_I2C1 },
+	[IMX8MQ_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MQ_CLK_I2C2 },
+	[IMX8MQ_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MQ_CLK_I2C3 },
+	[IMX8MQ_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MQ_CLK_I2C4 },
+	[IMX8MQ_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MQ_CLK_PCIE1_CTRL },
+	[IMX8MQ_CLK_PCIE2_ROOT] = { 0x4640, 0, IMX8MQ_CLK_PCIE2_CTRL },
+	[IMX8MQ_CLK_PWM1_ROOT] = { 0x4280, 0, IMX8MQ_CLK_PWM1 },
+	[IMX8MQ_CLK_PWM2_ROOT] = { 0x4290, 0, IMX8MQ_CLK_PWM2 },
+	[IMX8MQ_CLK_PWM3_ROOT] = { 0x42a0, 0, IMX8MQ_CLK_PWM3 },
+	[IMX8MQ_CLK_PWM4_ROOT] = { 0x42b0, 0, IMX8MQ_CLK_PWM4 },
+	[IMX8MQ_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MQ_CLK_UART1 },
+	[IMX8MQ_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MQ_CLK_UART2 },
+	[IMX8MQ_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MQ_CLK_UART3 },
+	[IMX8MQ_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MQ_CLK_UART4 },
+	[IMX8MQ_CLK_USB1_CTRL_ROOT] = { 0x44d0, 0, IMX8MQ_CLK_USB_CORE_REF },
+	[IMX8MQ_CLK_USB2_CTRL_ROOT] = { 0x44e0, 0, IMX8MQ_CLK_USB_CORE_REF },
+	[IMX8MQ_CLK_USB1_PHY_ROOT] = { 0x44f0, 0, IMX8MQ_CLK_USB_PHY_REF },
+	[IMX8MQ_CLK_USB2_PHY_ROOT] = { 0x4500, 0, IMX8MQ_CLK_USB_PHY_REF },
+	[IMX8MQ_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MQ_CLK_USDHC1 },
+	[IMX8MQ_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MQ_CLK_USDHC2 },
 };
 
 struct imxccm_divider imx8mq_divs[] = {
 	[IMX8MQ_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MQ_CLK_A53_CG },
-	[IMX8MQ_CLK_ENET_AXI_PRE_DIV] = { 0x8880, 16, 0x7, IMX8MQ_CLK_ENET_AXI_CG },
-	[IMX8MQ_CLK_ENET_AXI_DIV] = { 0x8880, 0, 0x3f, IMX8MQ_CLK_ENET_AXI_PRE_DIV },
-	[IMX8MQ_CLK_USB_BUS_PRE_DIV] = { 0x8b80, 16, 0x7, IMX8MQ_CLK_USB_BUS_CG },
-	[IMX8MQ_CLK_USB_BUS_DIV] = { 0x8b80, 0, 0x3f, IMX8MQ_CLK_USB_BUS_PRE_DIV },
-	[IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV] = { 0xa300, 16, 0x7, IMX8MQ_CLK_PCIE1_CTRL_CG },
-	[IMX8MQ_CLK_PCIE1_CTRL_DIV] = { 0xa300, 0, 0x3f, IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV },
-	[IMX8MQ_CLK_PCIE1_PHY_PRE_DIV] = { 0xa380, 16, 0x7, IMX8MQ_CLK_PCIE1_PHY_CG },
-	[IMX8MQ_CLK_PCIE1_PHY_DIV] = { 0xa380, 0, 0x3f, IMX8MQ_CLK_PCIE1_PHY_PRE_DIV },
-	[IMX8MQ_CLK_PCIE1_AUX_PRE_DIV] = { 0xa400, 16, 0x7, IMX8MQ_CLK_PCIE1_AUX_CG },
-	[IMX8MQ_CLK_PCIE1_AUX_DIV] = { 0xa400, 0, 0x3f, IMX8MQ_CLK_PCIE1_AUX_PRE_DIV },
-	[IMX8MQ_CLK_ENET_REF_PRE_DIV] = { 0xa980, 16, 0x7, IMX8MQ_CLK_ENET_REF_CG },
-	[IMX8MQ_CLK_ENET_REF_DIV] = { 0xa980, 0, 0x3f, IMX8MQ_CLK_ENET_REF_PRE_DIV },
-	[IMX8MQ_CLK_ENET_TIMER_PRE_DIV] = { 0xaa00, 16, 0x7, IMX8MQ_CLK_ENET_TIMER_CG },
-	[IMX8MQ_CLK_ENET_TIMER_DIV] = { 0xaa00, 0, 0x3f, IMX8MQ_CLK_ENET_TIMER_PRE_DIV },
-	[IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV] = { 0xaa80, 16, 0x7, IMX8MQ_CLK_ENET_PHY_REF_CG },
-	[IMX8MQ_CLK_ENET_PHY_REF_DIV] = { 0xaa80, 0, 0x3f, IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV },
-	[IMX8MQ_CLK_USDHC1_PRE_DIV] = { 0xac00, 16, 0x7, IMX8MQ_CLK_USDHC1_CG },
-	[IMX8MQ_CLK_USDHC1_DIV] = { 0xac00, 0, 0x3f, IMX8MQ_CLK_USDHC1_PRE_DIV },
-	[IMX8MQ_CLK_USDHC2_PRE_DIV] = { 0xac80, 16, 0x7, IMX8MQ_CLK_USDHC2_CG },
-	[IMX8MQ_CLK_USDHC2_DIV] = { 0xac80, 0, 0x3f, IMX8MQ_CLK_USDHC2_PRE_DIV },
-	[IMX8MQ_CLK_I2C1_PRE_DIV] = { 0xad00, 16, 0x7, IMX8MQ_CLK_I2C1_CG },
-	[IMX8MQ_CLK_I2C1_DIV] = { 0xad00, 0, 0x3f, IMX8MQ_CLK_I2C1_PRE_DIV },
-	[IMX8MQ_CLK_I2C2_PRE_DIV] = { 0xad80, 16, 0x7, IMX8MQ_CLK_I2C2_CG },
-	[IMX8MQ_CLK_I2C2_DIV] = { 0xad80, 0, 0x3f, IMX8MQ_CLK_I2C2_PRE_DIV },
-	[IMX8MQ_CLK_I2C3_PRE_DIV] = { 0xae00, 16, 0x7, IMX8MQ_CLK_I2C3_CG },
-	[IMX8MQ_CLK_I2C3_DIV] = { 0xae00, 0, 0x3f, IMX8MQ_CLK_I2C3_PRE_DIV },
-	[IMX8MQ_CLK_I2C4_PRE_DIV] = { 0xae80, 16, 0x7, IMX8MQ_CLK_I2C4_CG },
-	[IMX8MQ_CLK_I2C4_DIV] = { 0xae80, 0, 0x3f, IMX8MQ_CLK_I2C4_PRE_DIV },
-	[IMX8MQ_CLK_UART1_PRE_DIV] = { 0xaf00, 16, 0x7, IMX8MQ_CLK_UART1_CG },
-	[IMX8MQ_CLK_UART1_DIV] = { 0xaf00, 0, 0x3f, IMX8MQ_CLK_UART1_PRE_DIV },
-	[IMX8MQ_CLK_UART2_PRE_DIV] = { 0xaf80, 16, 0x7, IMX8MQ_CLK_UART2_CG },
-	[IMX8MQ_CLK_UART2_DIV] = { 0xaf80, 0, 0x3f, IMX8MQ_CLK_UART2_PRE_DIV },
-	[IMX8MQ_CLK_UART3_PRE_DIV] = { 0xb000, 16, 0x7, IMX8MQ_CLK_UART3_CG },
-	[IMX8MQ_CLK_UART3_DIV] = { 0xb000, 0, 0x3f, IMX8MQ_CLK_UART3_PRE_DIV },
-	[IMX8MQ_CLK_UART4_PRE_DIV] = { 0xb080, 16, 0x7, IMX8MQ_CLK_UART4_CG },
-	[IMX8MQ_CLK_UART4_DIV] = { 0xb080, 0, 0x3f, IMX8MQ_CLK_UART4_PRE_DIV },
-	[IMX8MQ_CLK_USB_CORE_REF_PRE_DIV] = { 0xb100, 16, 0x7, IMX8MQ_CLK_USB_CORE_REF_CG },
-	[IMX8MQ_CLK_USB_CORE_REF_DIV] = { 0xb100, 0, 0x3f, IMX8MQ_CLK_USB_CORE_REF_PRE_DIV },
-	[IMX8MQ_CLK_USB_PHY_REF_PRE_DIV] = { 0xb180, 16, 0x7, IMX8MQ_CLK_USB_PHY_REF_CG },
-	[IMX8MQ_CLK_USB_PHY_REF_DIV] = { 0xb180, 0, 0x3f, IMX8MQ_CLK_USB_PHY_REF_PRE_DIV },
-	[IMX8MQ_CLK_ECSPI1_PRE_DIV] = { 0xb280, 16, 0x7, IMX8MQ_CLK_ECSPI1_CG },
-	[IMX8MQ_CLK_ECSPI1_DIV] = { 0xb280, 0, 0x3f, IMX8MQ_CLK_ECSPI1_PRE_DIV },
-	[IMX8MQ_CLK_ECSPI2_PRE_DIV] = { 0xb300, 16, 0x7, IMX8MQ_CLK_ECSPI2_CG },
-	[IMX8MQ_CLK_ECSPI2_DIV] = { 0xb300, 0, 0x3f, IMX8MQ_CLK_ECSPI2_PRE_DIV },
-	[IMX8MQ_CLK_PWM1_PRE_DIV] = { 0xb380, 16, 0x7, IMX8MQ_CLK_PWM1_CG },
-	[IMX8MQ_CLK_PWM1_DIV] = { 0xb380, 0, 0x3f, IMX8MQ_CLK_PWM1_PRE_DIV },
-	[IMX8MQ_CLK_PWM2_PRE_DIV] = { 0xb400, 16, 0x7, IMX8MQ_CLK_PWM2_CG },
-	[IMX8MQ_CLK_PWM2_DIV] = { 0xb400, 0, 0x3f, IMX8MQ_CLK_PWM2_PRE_DIV },
-	[IMX8MQ_CLK_PWM3_PRE_DIV] = { 0xb480, 16, 0x7, IMX8MQ_CLK_PWM3_CG },
-	[IMX8MQ_CLK_PWM3_DIV] = { 0xb480, 0, 0x3f, IMX8MQ_CLK_PWM3_PRE_DIV },
-	[IMX8MQ_CLK_PWM4_PRE_DIV] = { 0xb500, 16, 0x7, IMX8MQ_CLK_PWM4_CG },
-	[IMX8MQ_CLK_PWM4_DIV] = { 0xb500, 0, 0x3f, IMX8MQ_CLK_PWM4_PRE_DIV },
-	[IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV] = { 0xc000, 16, 0x7, IMX8MQ_CLK_PCIE2_CTRL_CG },
-	[IMX8MQ_CLK_PCIE2_CTRL_DIV] = { 0xc000, 0, 0x3f, IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV },
-	[IMX8MQ_CLK_PCIE2_PHY_PRE_DIV] = { 0xc080, 16, 0x7, IMX8MQ_CLK_PCIE2_PHY_CG },
-	[IMX8MQ_CLK_PCIE2_PHY_DIV] = { 0xc080, 0, 0x3f, IMX8MQ_CLK_PCIE2_PHY_PRE_DIV },
-	[IMX8MQ_CLK_PCIE2_AUX_PRE_DIV] = { 0xc100, 16, 0x7, IMX8MQ_CLK_PCIE2_AUX_CG },
-	[IMX8MQ_CLK_PCIE2_AUX_DIV] = { 0xc100, 0, 0x3f, IMX8MQ_CLK_PCIE2_AUX_PRE_DIV },
-	[IMX8MQ_CLK_ECSPI3_PRE_DIV] = { 0xc180, 16, 0x7, IMX8MQ_CLK_ECSPI3_CG },
-	[IMX8MQ_CLK_ECSPI3_DIV] = { 0xc180, 0, 0x3f, IMX8MQ_CLK_ECSPI3_PRE_DIV },
+	[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 0, 0x3f },
+	[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f },
+	[IMX8MQ_CLK_USB_BUS] = { 0x8b80, 0, 0x3f },
+	[IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 0, 0x3f },
+	[IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 0, 0x3f },
+	[IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 0, 0x3f },
+	[IMX8MQ_CLK_ENET_REF] = { 0xa980, 0, 0x3f },
+	[IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 0, 0x3f },
+	[IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 0, 0x3f },
+	[IMX8MQ_CLK_USDHC1] = { 0xac00, 0, 0x3f },
+	[IMX8MQ_CLK_USDHC2] = { 0xac80, 0, 0x3f },
+	[IMX8MQ_CLK_I2C1] = { 0xad00, 0, 0x3f },
+	[IMX8MQ_CLK_I2C2] = { 0xad80, 0, 0x3f },
+	[IMX8MQ_CLK_I2C3] = { 0xae00, 0, 0x3f },
+	[IMX8MQ_CLK_I2C4] = { 0xae80, 0, 0x3f },
+	[IMX8MQ_CLK_UART1] = { 0xaf00, 0, 0x3f },
+	[IMX8MQ_CLK_UART2] = { 0xaf80, 0, 0x3f },
+	[IMX8MQ_CLK_UART3] = { 0xb000, 0, 0x3f },
+	[IMX8MQ_CLK_UART4] = { 0xb080, 0, 0x3f },
+	[IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 0, 0x3f },
+	[IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 0, 0x3f },
+	[IMX8MQ_CLK_ECSPI1] = { 0xb280, 0, 0x3f },
+	[IMX8MQ_CLK_ECSPI2] = { 0xb300, 0, 0x3f },
+	[IMX8MQ_CLK_PWM1] = { 0xb380, 0, 0x3f },
+	[IMX8MQ_CLK_PWM2] = { 0xb400, 0, 0x3f },
+	[IMX8MQ_CLK_PWM3] = { 0xb480, 0, 0x3f },
+	[IMX8MQ_CLK_PWM4] = { 0xb500, 0, 0x3f },
+	[IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 0, 0x3f },
+	[IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 0, 0x3f },
+	[IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 0, 0x3f },
+	[IMX8MQ_CLK_ECSPI3] = { 0xc180, 0, 0x3f },
+};
+
+struct imxccm_divider imx8mq_predivs[] = {
+	[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 16, 0x7 },
+	[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 },
+	[IMX8MQ_CLK_USB_BUS] = { 0x8b80, 16, 0x7 },
+	[IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 16, 0x7 },
+	[IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 16, 0x7 },
+	[IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 16, 0x7 },
+	[IMX8MQ_CLK_ENET_REF] = { 0xa980, 16, 0x7 },
+	[IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 16, 0x7 },
+	[IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 16, 0x7 },
+	[IMX8MQ_CLK_USDHC1] = { 0xac00, 16, 0x7 },
+	[IMX8MQ_CLK_USDHC2] = { 0xac80, 16, 0x7 },
+	[IMX8MQ_CLK_I2C1] = { 0xad00, 16, 0x7 },
+	[IMX8MQ_CLK_I2C2] = { 0xad80, 16, 0x7 },
+	[IMX8MQ_CLK_I2C3] = { 0xae00, 16, 0x7 },
+	[IMX8MQ_CLK_I2C4] = { 0xae80, 16, 0x7 },
+	[IMX8MQ_CLK_UART1] = { 0xaf00, 16, 0x7 },
+	[IMX8MQ_CLK_UART2] = { 0xaf80, 16, 0x7 },
+	[IMX8MQ_CLK_UART3] = { 0xb000, 16, 0x7 },
+	[IMX8MQ_CLK_UART4] = { 0xb080, 16, 0x7 },
+	[IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 16, 0x7 },
+	[IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 16, 0x7 },
+	[IMX8MQ_CLK_ECSPI1] = { 0xb280, 16, 0x7 },
+	[IMX8MQ_CLK_ECSPI2] = { 0xb300, 16, 0x7 },
+	[IMX8MQ_CLK_PWM1] = { 0xb380, 16, 0x7 },
+	[IMX8MQ_CLK_PWM2] = { 0xb400, 16, 0x7 },
+	[IMX8MQ_CLK_PWM3] = { 0xb480, 16, 0x7 },
+	[IMX8MQ_CLK_PWM4] = { 0xb500, 16, 0x7 },
+	[IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 16, 0x7 },
+	[IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 16, 0x7 },
+	[IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 16, 0x7 },
+	[IMX8MQ_CLK_ECSPI3] = { 0xc180, 16, 0x7 },
 };
 
 struct imxccm_mux imx8mq_muxs[] = {
 	[IMX8MQ_CLK_A53_SRC] = { 0x8000, 24, 0x7 },
-	[IMX8MQ_CLK_ENET_AXI_SRC] = { 0x8880, 24, 0x7 },
-	[IMX8MQ_CLK_USB_BUS_SRC] = { 0x8b80, 24, 0x7 },
-	[IMX8MQ_CLK_PCIE1_CTRL_SRC] = { 0xa300, 24, 0x7 },
-	[IMX8MQ_CLK_PCIE1_PHY_SRC] = { 0xa380, 24, 0x7 },
-	[IMX8MQ_CLK_PCIE1_AUX_SRC] = { 0xa400, 24, 0x7 },
-	[IMX8MQ_CLK_ENET_REF_SRC] = { 0xa980, 24, 0x7 },
-	[IMX8MQ_CLK_ENET_TIMER_SRC] = { 0xaa00, 24, 0x7 },
-	[IMX8MQ_CLK_ENET_PHY_REF_SRC] = { 0xaa80, 24, 0x7 },
-	[IMX8MQ_CLK_USDHC1_SRC] = { 0xac00, 24, 0x7 },
-	[IMX8MQ_CLK_USDHC2_SRC] = { 0xac80, 24, 0x7 },
-	[IMX8MQ_CLK_I2C1_SRC] = { 0xad00, 24, 0x7 },
-	[IMX8MQ_CLK_I2C2_SRC] = { 0xad80, 24, 0x7 },
-	[IMX8MQ_CLK_I2C3_SRC] = { 0xae00, 24, 0x7 },
-	[IMX8MQ_CLK_I2C4_SRC] = { 0xae80, 24, 0x7 },
-	[IMX8MQ_CLK_UART1_SRC] = { 0xaf00, 24, 0x7 },
-	[IMX8MQ_CLK_UART2_SRC] = { 0xaf80, 24, 0x7 },
-	[IMX8MQ_CLK_UART3_SRC] = { 0xb000, 24, 0x7 },
-	[IMX8MQ_CLK_UART4_SRC] = { 0xb080, 24, 0x7 },
-	[IMX8MQ_CLK_USB_CORE_REF_SRC] = { 0xb100, 24, 0x7 },
-	[IMX8MQ_CLK_USB_PHY_REF_SRC] = { 0xb180, 24, 0x7 },
-	[IMX8MQ_CLK_ECSPI1_SRC] = { 0xb280, 24, 0x7 },
-	[IMX8MQ_CLK_ECSPI2_SRC] = { 0xb300, 24, 0x7 },
-	[IMX8MQ_CLK_PWM1_SRC] = { 0xb380, 24, 0x7 },
-	[IMX8MQ_CLK_PWM2_SRC] = { 0xb400, 24, 0x7 },
-	[IMX8MQ_CLK_PWM3_SRC] = { 0xb480, 24, 0x7 },
-	[IMX8MQ_CLK_PWM4_SRC] = { 0xb500, 24, 0x7 },
-	[IMX8MQ_CLK_PCIE2_CTRL_SRC] = { 0xc000, 24, 0x7 },
-	[IMX8MQ_CLK_PCIE2_PHY_SRC] = { 0xc080, 24, 0x7 },
-	[IMX8MQ_CLK_PCIE2_AUX_SRC] = { 0xc100, 24, 0x7 },
-	[IMX8MQ_CLK_ECSPI3_SRC] = { 0xc180, 24, 0x7 },
+	[IMX8MQ_CLK_ENET_AXI] = { 0x8880, 24, 0x7 },
+	[IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 },
+	[IMX8MQ_CLK_USB_BUS] = { 0x8b80, 24, 0x7 },
+	[IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 24, 0x7 },
+	[IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 24, 0x7 },
+	[IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 24, 0x7 },
+	[IMX8MQ_CLK_ENET_REF] = { 0xa980, 24, 0x7 },
+	[IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 24, 0x7 },
+	[IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 24, 0x7 },
+	[IMX8MQ_CLK_USDHC1] = { 0xac00, 24, 0x7 },
+	[IMX8MQ_CLK_USDHC2] = { 0xac80, 24, 0x7 },
+	[IMX8MQ_CLK_I2C1] = { 0xad00, 24, 0x7 },
+	[IMX8MQ_CLK_I2C2] = { 0xad80, 24, 0x7 },
+	[IMX8MQ_CLK_I2C3] = { 0xae00, 24, 0x7 },
+	[IMX8MQ_CLK_I2C4] = { 0xae80, 24, 0x7 },
+	[IMX8MQ_CLK_UART1] = { 0xaf00, 24, 0x7 },
+	[IMX8MQ_CLK_UART2] = { 0xaf80, 24, 0x7 },
+	[IMX8MQ_CLK_UART3] = { 0xb000, 24, 0x7 },
+	[IMX8MQ_CLK_UART4] = { 0xb080, 24, 0x7 },
+	[IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 24, 0x7 },
+	[IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 24, 0x7 },
+	[IMX8MQ_CLK_ECSPI1] = { 0xb280, 24, 0x7 },
+	[IMX8MQ_CLK_ECSPI2] = { 0xb300, 24, 0x7 },
+	[IMX8MQ_CLK_PWM1] = { 0xb380, 24, 0x7 },
+	[IMX8MQ_CLK_PWM2] = { 0xb400, 24, 0x7 },
+	[IMX8MQ_CLK_PWM3] = { 0xb480, 24, 0x7 },
+	[IMX8MQ_CLK_PWM4] = { 0xb500, 24, 0x7 },
+	[IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 },
+	[IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 },
+	[IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 24, 0x7 },
+	[IMX8MQ_CLK_ECSPI3] = { 0xc180, 24, 0x7 },
 };