It turns out that, when the IRIX header files mention CTR/DCD/DTR/RTS wiring

is inverted on Indigo, this just means that Indigo does not use the same
values as the later models. It does not mean that the Indigo is using wrong
values, which is how I first read this. In reality, Indigo systems use the
expected values of these signals being active low, while later designs
use active high signals.

So yes, some systems have inverted values - but the ones which need
compensating are not those I thought.

Change the logic to do TRT, but keep the device flags check, to be able to
force the other behaviour if the kernel guesses wrongly. Tested on Indigo,
Indy and Indigo 2.

2 files changed, 22 insertions, 21 deletions

diff --git a/sys/arch/sgi/hpc/zs.c b/sys/arch/sgi/hpc/zs.c
index 488d2115c72..a825fa552d3 100644
--- a/sys/arch/sgi/hpc/zs.c
+++ b/sys/arch/sgi/hpc/zs.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: zs.c,v 1.8 2012/04/29 09:01:38 miod Exp $	*/
+/*	$OpenBSD: zs.c,v 1.9 2012/05/12 16:47:44 miod Exp $	*/
 /*	$NetBSD: zs.c,v 1.37 2011/02/20 07:59:50 matt Exp $	*/
 
 /*-
@@ -227,9 +227,22 @@ zs_hpc_attach(struct device *parent, struct device *self, void *aux)
 		ch = &zsc->zsc_cs_store[channel];
 		cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch;
 
-		/* pick Indigo wiring if requested */
-		if (cf->cf_flags & ZSCFL_INDIGO_WIRING)
-			ch->cs_flags |= ZSCFL_INDIGO_WIRING;
+		/*
+		 * According to IRIX <sys/z8530.h>, on Indigo, the CTR, DCD,
+		 * DTR and RTS bits are inverted.
+		 *
+		 * That is, inverted when compared to the Indy and Indigo 2
+		 * designs. However, it turns out that the Indigo wiring is
+		 * the `natural' one, with these pins being inverted from
+		 * what one would naively expect, on the other designs.
+		 *
+		 * Choose wiring logic according to the hardware we run on,
+		 * and the device flags.
+		 */
+		if (sys_config.system_type != SGI_IP20)
+			ch->cs_flags |= ZSCFL_INVERT_WIRING;
+		if (cf->cf_flags & ZSCFL_INVERT_WIRING)
+			ch->cs_flags ^= ZSCFL_INVERT_WIRING;
 
 		cs->cs_reg_csr = NULL;
 		cs->cs_reg_data = NULL;
@@ -470,11 +483,7 @@ zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
 	ZS_DELAY();
 
-	/*
-	 * According to IRIX <sys/z8530.h>, on Indigo, the CTS and DCD bits
-	 * are inverted.
-	 */
-	if ((zsc->cs_flags & ZSCFL_INDIGO_WIRING) && reg == 0)
+	if ((zsc->cs_flags & ZSCFL_INVERT_WIRING) && reg == 0)
 		val ^= ZSRR0_CTS | ZSRR0_DCD;
 
 	return val;
@@ -485,11 +494,7 @@ zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
 {
 	struct zs_channel *zsc = (struct zs_channel *)cs;
 
-	/*
-	 * According to IRIX <sys/z8530.h>, on Indigo, the RTS and DTR bits
-	 * are inverted.
-	 */
-	if ((zsc->cs_flags & ZSCFL_INDIGO_WIRING) && reg == 5)
+	if ((zsc->cs_flags & ZSCFL_INVERT_WIRING) && reg == 5)
 		val ^= ZSWR5_DTR | ZSWR5_RTS;
 
 	bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg);
@@ -511,11 +516,7 @@ zs_read_csr(struct zs_chanstate *cs)
 	val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR);
 	ZS_DELAY();
 
-	/*
-	 * According to IRIX <sys/z8530.h>, on Indigo, the CTS and DCD bits
-	 * are inverted.
-	 */
-	if (zsc->cs_flags & ZSCFL_INDIGO_WIRING)
+	if (zsc->cs_flags & ZSCFL_INVERT_WIRING)
 		val ^= ZSRR0_CTS | ZSRR0_DCD;
 
 	return val;
diff --git a/sys/arch/sgi/include/z8530var.h b/sys/arch/sgi/include/z8530var.h
index a71726ddefb..487913357af 100644
--- a/sys/arch/sgi/include/z8530var.h
+++ b/sys/arch/sgi/include/z8530var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: z8530var.h,v 1.2 2012/04/29 08:59:12 miod Exp $	*/
+/*	$OpenBSD: z8530var.h,v 1.3 2012/05/12 16:47:44 miod Exp $	*/
 /*	$NetBSD: z8530var.h,v 1.10 2011/07/01 21:00:21 dyoung Exp $	*/
 
 /*
@@ -92,7 +92,7 @@ struct zs_channel {
 	bus_space_tag_t		cs_bustag;	/* Machine-dependent */
 	bus_space_handle_t	cs_regs;
 	int			cs_flags;
-#define	ZSCFL_INDIGO_WIRING		0x01
+#define	ZSCFL_INVERT_WIRING		0x01
 };
 
 struct zsc_softc {