diff options
| author | Mark Kettenis <kettenis@cvs.openbsd.org> | 2014-06-17 19:49:54 +0000 |
|---|---|---|
| committer | Mark Kettenis <kettenis@cvs.openbsd.org> | 2014-06-17 19:49:54 +0000 |
| commit | ad40be57af916f227a185b88d51123d99ea6acd9 (patch) | |
| tree | f6d69aacf7da127da8cce000cc3c2528859427f7 /sys | |
| parent | f4c68172f3b2828addbb88ac963fa0fb50ebd5d2 (diff) | |
Implement the membar(9) API for hppa.
ok miod@, dlg@, guenther@
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arch/hppa/include/atomic.h | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/sys/arch/hppa/include/atomic.h b/sys/arch/hppa/include/atomic.h index 9cfe677db9c..3b290c58fe0 100644 --- a/sys/arch/hppa/include/atomic.h +++ b/sys/arch/hppa/include/atomic.h @@ -1,4 +1,4 @@ -/* $OpenBSD: atomic.h,v 1.6 2014/03/29 18:09:29 guenther Exp $ */ +/* $OpenBSD: atomic.h,v 1.7 2014/06/17 19:49:53 kettenis Exp $ */ /* Public Domain */ @@ -70,5 +70,24 @@ atomic_clearbits_long(volatile unsigned long *uip, unsigned long v) __asm volatile("mtctl %0, %%cr15":: "r" (eiem)); } +/* + * Although the PA-RISC 2.0 architecture allows an implementation to + * be weakly ordered, all PA-RISC processers to date implement a + * strong memory ordering model. So all we need is a compiler + * barrier. + */ + +static inline void +__insn_barrier(void) +{ + __asm volatile("" : : : "memory"); +} + +#define membar_enter() __insn_barrier() +#define membar_exit() __insn_barrier() +#define membar_producer() __insn_barrier() +#define membar_consumer() __insn_barrier() +#define membar_sync() __insn_barrier() + #endif /* defined(_KERNEL) */ #endif /* _MACHINE_ATOMIC_H_ */ |