diff options
author | Joshua Stein <jcs@cvs.openbsd.org> | 2018-04-15 00:11:00 +0000 |
---|---|---|
committer | Joshua Stein <jcs@cvs.openbsd.org> | 2018-04-15 00:11:00 +0000 |
commit | adb7ae98a1c6ab33d3efed1517a420d1e4022efe (patch) | |
tree | 569da17a4c6b44c5f60587bcb1cdfa8001453e20 /sys | |
parent | 034c6708458ef06c6dab1c9a382e7946d4840afd (diff) |
pucdata: convert port types and frequencies to a lookup table to
allow for custom frequencies not a multiple of COM_FREQ
ok deraadt
Diffstat (limited to 'sys')
-rw-r--r-- | sys/dev/pci/pucdata.c | 1100 | ||||
-rw-r--r-- | sys/dev/pci/pucvar.h | 38 | ||||
-rw-r--r-- | sys/dev/puc/com_puc.c | 15 |
3 files changed, 585 insertions, 568 deletions
diff --git a/sys/dev/pci/pucdata.c b/sys/dev/pci/pucdata.c index b516d4efc20..172ae5c7ae1 100644 --- a/sys/dev/pci/pucdata.c +++ b/sys/dev/pci/pucdata.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pucdata.c,v 1.106 2017/08/04 22:39:36 uaa Exp $ */ +/* $OpenBSD: pucdata.c,v 1.107 2018/04/15 00:10:59 jcs Exp $ */ /* $NetBSD: pucdata.c,v 1.6 1999/07/03 05:55:23 cgd Exp $ */ /* @@ -51,175 +51,175 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 7 Series KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 8 Series KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 8 Series LP KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 9 Series KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 9 Series LP KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 100 Series KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 100 Series LP KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 82946GZ KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82946GZ_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 82Q965 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q965_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 82G965 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G965_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 82Q35 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q35_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 82G33 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82G33_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 82Q33 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q33_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 82X38 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82X38_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* GM965 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82GM965_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* GME965 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82GME965_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* GM45 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82GM45_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* Q45 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82Q45_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* 3400 KT */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_KT, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* Intel EG20T */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EG20T_SERIAL_1, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* Intel EG20T */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EG20T_SERIAL_2, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* Intel EG20T */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EG20T_SERIAL_3, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* Intel EG20T */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EG20T_SERIAL_4, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* Atom S1200 UART */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOM_S1200_UART, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, /* @@ -237,8 +237,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_9050, 0xd84d, 0x6810 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_LPT, 0x20, 0x0000 }, - { PUC_LPT, 0x24, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, + { PUC_PORT_LPT, 0x24, 0x0000 }, }, }, @@ -257,8 +257,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_9050, 0xd84d, 0x6808 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -276,8 +276,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_DCI, PCI_PRODUCT_DCI_APCI2, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0008 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0008 }, }, }, @@ -286,10 +286,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_DCI, PCI_PRODUCT_DCI_APCI4, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0008 }, - { PUC_COM_POW2(0), 0x1c, 0x0010 }, - { PUC_COM_POW2(0), 0x1c, 0x0018 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0008 }, + { PUC_PORT_COM, 0x1c, 0x0010 }, + { PUC_PORT_COM, 0x1c, 0x0018 }, }, }, @@ -298,14 +298,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_DCI, PCI_PRODUCT_DCI_APCI8, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0008 }, - { PUC_COM_POW2(0), 0x1c, 0x0010 }, - { PUC_COM_POW2(0), 0x1c, 0x0018 }, - { PUC_COM_POW2(0), 0x1c, 0x0020 }, - { PUC_COM_POW2(0), 0x1c, 0x0028 }, - { PUC_COM_POW2(0), 0x1c, 0x0030 }, - { PUC_COM_POW2(0), 0x1c, 0x0038 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0008 }, + { PUC_PORT_COM, 0x1c, 0x0010 }, + { PUC_PORT_COM, 0x1c, 0x0018 }, + { PUC_PORT_COM, 0x1c, 0x0020 }, + { PUC_PORT_COM, 0x1c, 0x0028 }, + { PUC_PORT_COM, 0x1c, 0x0030 }, + { PUC_PORT_COM, 0x1c, 0x0038 }, }, }, /* IBM SurePOS 300 Series (481033H) serial ports */ @@ -313,10 +313,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_IBM, PCI_PRODUCT_IBM_4810_SCC, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, /* Port C */ - { PUC_COM_POW2(0), 0x18, 0x0000 }, /* Port D */ - { PUC_COM_POW2(0), 0x14, 0x0000 }, /* Port E */ - { PUC_COM_POW2(0), 0x1c, 0x0000 }, /* Port F */ + { PUC_PORT_COM, 0x10, 0x0000 }, /* Port C */ + { PUC_PORT_COM, 0x18, 0x0000 }, /* Port D */ + { PUC_PORT_COM, 0x14, 0x0000 }, /* Port E */ + { PUC_PORT_COM, 0x1c, 0x0000 }, /* Port F */ }, }, @@ -339,7 +339,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1000, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, }, }, @@ -348,7 +348,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1001, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, }, }, @@ -357,7 +357,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1002, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, }, }, @@ -366,8 +366,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1010, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -376,8 +376,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1011, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -386,8 +386,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1012, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -396,7 +396,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1020, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -405,8 +405,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1021, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x18, 0x0000 }, - { PUC_LPT, 0x20, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, }, }, @@ -415,8 +415,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1030, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -425,8 +425,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1031, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -435,8 +435,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1032, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -445,9 +445,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1034, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_LPT, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, }, }, @@ -456,9 +456,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1035, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_LPT, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, }, }, @@ -467,9 +467,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1036, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_LPT, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, }, }, @@ -478,10 +478,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1050, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x20, 0x0000 }, - { PUC_COM_POW2(0), 0x24, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x24, 0x0000 }, }, }, @@ -490,10 +490,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1051, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x20, 0x0000 }, - { PUC_COM_POW2(0), 0x24, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x24, 0x0000 }, }, }, @@ -502,10 +502,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_1052, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x20, 0x0000 }, - { PUC_COM_POW2(0), 0x24, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x24, 0x0000 }, }, }, @@ -518,7 +518,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2020, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -527,8 +527,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2021, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -537,9 +537,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2040, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_LPT, 0x14, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -548,9 +548,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2041, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_LPT, 0x14, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -559,9 +559,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2042, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_LPT, 0x14, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -570,7 +570,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2000, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -579,7 +579,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2001, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -588,7 +588,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2002, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -597,8 +597,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2010, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_LPT, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, }, }, @@ -607,8 +607,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2011, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_LPT, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, }, }, @@ -617,8 +617,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2012, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_LPT, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, }, }, @@ -627,8 +627,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2030, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -637,8 +637,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2031, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -647,8 +647,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2032, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -657,9 +657,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2060, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -668,9 +668,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2061, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -679,9 +679,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2062, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -690,10 +690,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2050, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -702,10 +702,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2051, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -714,10 +714,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2052, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -726,14 +726,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2081, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x20, 0x0000 }, - { PUC_COM_POW2(0), 0x20, 0x0008 }, - { PUC_COM_POW2(0), 0x20, 0x0010 }, - { PUC_COM_POW2(0), 0x20, 0x0018 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x20, 0x0008 }, + { PUC_PORT_COM, 0x20, 0x0010 }, + { PUC_PORT_COM, 0x20, 0x0018 }, }, }, @@ -743,10 +743,10 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2082 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_MUL(10), 0x10, 0x0000 }, - { PUC_COM_MUL(10), 0x10, 0x0008 }, - { PUC_COM_MUL(10), 0x10, 0x0010 }, - { PUC_COM_MUL(10), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0018 }, }, }, @@ -756,10 +756,10 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_OXFORD2, 0 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, }, }, @@ -768,7 +768,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_EXSYS_EX41092,0x0000,0x0000}, { 0xffff, 0xffff, 0x0000,0x0000}, { - { PUC_COM_MUL(10), 0x10, 0x0000 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0000 }, }, }, @@ -778,10 +778,10 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_OXFORD2, 0 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, }, }, @@ -791,10 +791,10 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2082 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_MUL(10), 0x10, 0x0000 }, - { PUC_COM_MUL(10), 0x10, 0x0008 }, - { PUC_COM_MUL(10), 0x10, 0x0010 }, - { PUC_COM_MUL(10), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0018 }, }, }, @@ -805,10 +805,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_1077, 0x10b5, 0x1077 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, }, }, @@ -823,14 +823,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_1076, 0x10b5, 0x1076 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0008 }, - { PUC_COM_POW2(0), 0x18, 0x0010 }, - { PUC_COM_POW2(0), 0x18, 0x0018 }, - { PUC_COM_POW2(0), 0x18, 0x0020 }, - { PUC_COM_POW2(0), 0x18, 0x0028 }, - { PUC_COM_POW2(0), 0x18, 0x0030 }, - { PUC_COM_POW2(0), 0x18, 0x0038 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0008 }, + { PUC_PORT_COM, 0x18, 0x0010 }, + { PUC_PORT_COM, 0x18, 0x0018 }, + { PUC_PORT_COM, 0x18, 0x0020 }, + { PUC_PORT_COM, 0x18, 0x0028 }, + { PUC_PORT_COM, 0x18, 0x0030 }, + { PUC_PORT_COM, 0x18, 0x0038 }, }, }, @@ -841,7 +841,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_VSCOM_PCI011H, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -853,7 +853,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCIx10H, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -867,7 +867,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI100H, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, }, }, @@ -882,8 +882,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI200H, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, }, }, @@ -900,20 +900,20 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI800H_0, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, }, }, { /* "VScom PCI-400H/800H", */ { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI800H_1, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, }, }, @@ -925,8 +925,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI200HV2, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, }, }, @@ -939,7 +939,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI010L, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -953,7 +953,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI100L, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, }, }, @@ -966,8 +966,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI110L, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -981,8 +981,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI200L, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, }, }, @@ -995,9 +995,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI210L, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_LPT, 0x1c, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x1c, 0x0000 }, }, }, @@ -1011,10 +1011,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOLEX, PCI_PRODUCT_MOLEX_VSCOM_PCI400L, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x20, 0x0000 }, - { PUC_COM_POW2(3), 0x20, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0008 }, }, }, @@ -1026,14 +1026,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD, PCI_PRODUCT_OXFORD_VSCOM_PCI800L, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x20, 0x0000 }, - { PUC_COM_POW2(3), 0x20, 0x0008 }, - { PUC_COM_POW2(3), 0x20, 0x0010 }, - { PUC_COM_POW2(3), 0x20, 0x0018 }, - { PUC_COM_POW2(3), 0x20, 0x0020 }, - { PUC_COM_POW2(3), 0x20, 0x0028 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0020 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0028 }, }, }, @@ -1044,10 +1044,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_EXSYS_EX41098, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x10, 0x0008 }, - { PUC_COM_POW2(0), 0x10, 0x0010 }, - { PUC_COM_POW2(0), 0x10, 0x0018 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0008 }, + { PUC_PORT_COM, 0x10, 0x0010 }, + { PUC_PORT_COM, 0x10, 0x0018 }, }, }, @@ -1067,8 +1067,8 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_OXFORD2, 0x0001 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, }, }, @@ -1077,8 +1077,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OX16PCI952, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -1087,7 +1087,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OX16PCI952P, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1096,7 +1096,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OXPCIE952, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1106,10 +1106,10 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_SIIG, PCI_PRODUCT_SIIG_2050 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_MUL(10), 0x10, 0x0000 }, - { PUC_COM_MUL(10), 0x10, 0x0008 }, - { PUC_COM_MUL(10), 0x10, 0x0010 }, - { PUC_COM_MUL(10), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL10, 0x10, 0x0018 }, }, }, @@ -1119,8 +1119,8 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_IODATA, 0xc070 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, }, }, @@ -1129,10 +1129,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OX16PCI954, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x10, 0x0008 }, - { PUC_COM_POW2(0), 0x10, 0x0010 }, - { PUC_COM_POW2(0), 0x10, 0x0018 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0008 }, + { PUC_PORT_COM, 0x10, 0x0010 }, + { PUC_PORT_COM, 0x10, 0x0018 }, }, }, @@ -1141,9 +1141,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OXMPCI954, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(2), 0x10, 0x0000 }, - { PUC_COM_POW2(2), 0x10, 0x0008 }, - { PUC_COM_POW2(2), 0x10, 0x0010 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0010 }, }, }, @@ -1152,10 +1152,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OX16PCI954K, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -1164,7 +1164,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OX16PCI954P, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1173,7 +1173,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OXPCIE952S, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1186,8 +1186,8 @@ const struct puc_device_description puc_devs[] = { 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0008 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0008 }, }, }, @@ -1199,7 +1199,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_MARTH, 0x1033, 0x8014 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1208,7 +1208,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_PKUG, 0x1033, 0x8012 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1217,7 +1217,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_TWOSP_1P, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1226,8 +1226,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_TWOSP_2S, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -1239,8 +1239,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_QUATTRO_AB2, 0, 0 }, { 0xffff, 0xfffe, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -1252,8 +1252,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_LAVAPORT_0, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(2), 0x10, 0x0000 }, - { PUC_COM_POW2(2), 0x14, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x14, 0x0000 }, }, }, @@ -1264,7 +1264,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_LAVAPORT_2, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(2), 0x10, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0000 }, }, }, @@ -1273,7 +1273,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_650, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(2), 0x10, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0000 }, }, }, @@ -1282,7 +1282,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_IOFLEX_2S_0, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1291,7 +1291,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_IOFLEX_2S_1, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1300,10 +1300,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_OCTOPUS550_0, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -1312,10 +1312,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LAVA, PCI_PRODUCT_LAVA_OCTOPUS550_1, 0, 0 }, { 0xffff, 0xfffc, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -1324,7 +1324,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_USR, PCI_PRODUCT_USR_3CP5610, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1334,7 +1334,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_VENUSMODEM, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0008 }, + { PUC_PORT_COM, 0x18, 0x0008 }, }, }, @@ -1343,7 +1343,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_TOPIC, PCI_PRODUCT_TOPIC_5634PCV, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1352,10 +1352,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SYBA, PCI_PRODUCT_SYBA_4S, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x03e8 }, - { PUC_COM_POW2(0), 0x10, 0x02e8 }, - { PUC_COM_POW2(0), 0x10, 0x03f8 }, - { PUC_COM_POW2(0), 0x10, 0x02f8 }, + { PUC_PORT_COM, 0x10, 0x03e8 }, + { PUC_PORT_COM, 0x10, 0x02e8 }, + { PUC_PORT_COM, 0x10, 0x03f8 }, + { PUC_PORT_COM, 0x10, 0x02f8 }, }, }, @@ -1364,12 +1364,12 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SYBA, PCI_PRODUCT_SYBA_4S2P, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x02e8 }, - { PUC_COM_POW2(0), 0x10, 0x02f8 }, - { PUC_LPT, 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x10, 0x03e8 }, - { PUC_COM_POW2(0), 0x10, 0x03f8 }, - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x02e8 }, + { PUC_PORT_COM, 0x10, 0x02f8 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x03e8 }, + { PUC_PORT_COM, 0x10, 0x03f8 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1378,10 +1378,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOXA, PCI_PRODUCT_MOXA_CP114, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, }, }, @@ -1390,10 +1390,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOXA, PCI_PRODUCT_MOXA_C104H, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, }, }, @@ -1402,10 +1402,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOXA, PCI_PRODUCT_MOXA_CP104UL, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, }, }, @@ -1414,10 +1414,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOXA, PCI_PRODUCT_MOXA_CP104JU, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, }, }, @@ -1426,10 +1426,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOXA, PCI_PRODUCT_MOXA_CP104EL, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, }, }, @@ -1438,14 +1438,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOXA, PCI_PRODUCT_MOXA_C168H, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, - { PUC_COM_POW2(3), 0x18, 0x0020 }, - { PUC_COM_POW2(3), 0x18, 0x0028 }, - { PUC_COM_POW2(3), 0x18, 0x0030 }, - { PUC_COM_POW2(3), 0x18, 0x0038 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0020 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0028 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0030 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0038 }, }, }, @@ -1454,14 +1454,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_MOXA, PCI_PRODUCT_MOXA_CP168U, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x18, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0010 }, - { PUC_COM_POW2(3), 0x18, 0x0018 }, - { PUC_COM_POW2(3), 0x18, 0x0020 }, - { PUC_COM_POW2(3), 0x18, 0x0028 }, - { PUC_COM_POW2(3), 0x18, 0x0030 }, - { PUC_COM_POW2(3), 0x18, 0x0038 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0020 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0028 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0030 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0038 }, }, }, @@ -1470,7 +1470,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9805, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1479,7 +1479,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9835, 0x1000, 0x0001 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1488,9 +1488,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9835, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -1499,10 +1499,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9845, 0x1000, 0x0004 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -1511,11 +1511,11 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9845, 0x1000, 0x0014 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_LPT, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, }, }, @@ -1524,12 +1524,12 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9845, 0x1000, 0x0006 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x20, 0x0000 }, - { PUC_COM_POW2(0), 0x24, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x24, 0x0000 }, }, }, @@ -1538,8 +1538,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9845, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -1552,17 +1552,17 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9865, 0xa000, 0x1000 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "NetMos NM9865 6 UART: 4 UART ISA" */ { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9865, 0xa000, 0x3004 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -1571,7 +1571,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9901, 0xa000, 0x1000 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1580,7 +1580,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9901, 0xa000, 0x2000 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1588,7 +1588,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9922, 0xa000, 0x1000 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, @@ -1603,10 +1603,10 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OX16PCI954 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, }, }, { /* OX16PCI954 8-bit pass-through Local Bus */ @@ -1614,10 +1614,10 @@ const struct puc_device_description puc_devs[] = { PCI_VENDOR_OXFORD2, 0x9511 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, }, }, @@ -1625,8 +1625,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_4018A, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_LPT, 0x10, 0x0000 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -1638,7 +1638,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4000 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, }, }, @@ -1646,8 +1646,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4010 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_LPT, 0x10, 0x0000 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -1655,7 +1655,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4020 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, }, }, @@ -1663,8 +1663,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4030 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, }, }, @@ -1672,8 +1672,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x0002 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, }, }, @@ -1681,10 +1681,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4050 }, { 0xffff, 0xffff, 0xffff, 0xe0f0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0008 }, }, }, @@ -1692,14 +1692,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x5066 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0008 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, - { PUC_COM_POW2(0), 0x20, 0x0000 }, - { PUC_COM_POW2(0), 0x24, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0008 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x20, 0x0000 }, + { PUC_PORT_COM, 0x24, 0x0000 }, }, }, @@ -1707,14 +1707,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4060 }, { 0xffff, 0xffff, 0xffff, 0xe0f0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_COM_POW2(3), 0x14, 0x0008 }, - { PUC_COM_POW2(3), 0x18, 0x0000 }, - { PUC_COM_POW2(3), 0x1c, 0x0000 }, - { PUC_COM_POW2(3), 0x20, 0x0000 }, - { PUC_COM_POW2(3), 0x24, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x1c, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x20, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x24, 0x0000 }, }, }, @@ -1722,9 +1722,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4070 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_LPT, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, }, }, @@ -1732,10 +1732,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4080 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_LPT, 0x18, 0x0000 }, - { PUC_LPT, 0x20, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, }, }, @@ -1743,12 +1743,12 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX, PCI_PRODUCT_SUNIX_40XX, 0x1409, 0x4090 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0008 }, - { PUC_LPT, 0x18, 0x0000 }, - { PUC_LPT, 0x20, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0008 }, + { PUC_PORT_LPT, 0x18, 0x0000 }, + { PUC_PORT_LPT, 0x20, 0x0000 }, }, }, @@ -1760,7 +1760,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0100 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_LPT, 0x14, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, }, }, @@ -1768,22 +1768,22 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0010 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_COM_POW2(3), 0x14, 0x0008 }, - { PUC_COM_POW2(3), 0x14, 0x0010 }, - { PUC_COM_POW2(3), 0x14, 0x0018 }, - { PUC_COM_POW2(3), 0x14, 0x0020 }, - { PUC_COM_POW2(3), 0x14, 0x0028 }, - { PUC_COM_POW2(3), 0x14, 0x0030 }, - { PUC_COM_POW2(3), 0x14, 0x0038 }, - { PUC_COM_POW2(3), 0x14, 0x0040 }, - { PUC_COM_POW2(3), 0x14, 0x0048 }, - { PUC_COM_POW2(3), 0x14, 0x0050 }, - { PUC_COM_POW2(3), 0x14, 0x0058 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0020 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0028 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0030 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0038 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0040 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0048 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0050 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0058 }, }, }, @@ -1791,7 +1791,7 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0001 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, }, }, @@ -1799,8 +1799,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0002 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, }, }, @@ -1808,10 +1808,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0004 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, }, }, @@ -1819,14 +1819,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0008 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, - { PUC_COM_POW2(3), 0x14, 0x0000 }, - { PUC_COM_POW2(3), 0x14, 0x0008 }, - { PUC_COM_POW2(3), 0x14, 0x0010 }, - { PUC_COM_POW2(3), 0x14, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x14, 0x0018 }, }, }, @@ -1834,8 +1834,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0101 }, { 0xffff, 0xffff, 0xffff, 0xeff0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_LPT, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, }, }, @@ -1843,9 +1843,9 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0102 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_LPT, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, }, }, @@ -1853,11 +1853,11 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_SUNIX2, PCI_PRODUCT_SUNIX2_50XX, 0x1fd4, 0x0104 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0008 }, - { PUC_COM_POW2(3), 0x10, 0x0010 }, - { PUC_COM_POW2(3), 0x10, 0x0018 }, - { PUC_LPT, 0x14, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0018 }, + { PUC_PORT_LPT, 0x14, 0x0000 }, }, }, @@ -1870,10 +1870,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_9050, 0x12e0, 0x0031 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(2), 0x18, 0x0000 }, - { PUC_COM_POW2(2), 0x18, 0x0008 }, - { PUC_COM_POW2(2), 0x18, 0x0010 }, - { PUC_COM_POW2(2), 0x18, 0x0018 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0018 }, }, }, @@ -1886,14 +1886,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_9050, 0x12e0, 0x0021 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(2), 0x18, 0x0000 }, - { PUC_COM_POW2(2), 0x18, 0x0008 }, - { PUC_COM_POW2(2), 0x18, 0x0010 }, - { PUC_COM_POW2(2), 0x18, 0x0018 }, - { PUC_COM_POW2(2), 0x18, 0x0020 }, - { PUC_COM_POW2(2), 0x18, 0x0028 }, - { PUC_COM_POW2(2), 0x18, 0x0030 }, - { PUC_COM_POW2(2), 0x18, 0x0038 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0008 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0010 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0018 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0020 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0028 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0030 }, + { PUC_PORT_COM_MUL4, 0x18, 0x0038 }, }, }, @@ -1902,14 +1902,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_CRONYX_OMEGA, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0008 }, - { PUC_COM_POW2(0), 0x18, 0x0010 }, - { PUC_COM_POW2(0), 0x18, 0x0018 }, - { PUC_COM_POW2(0), 0x18, 0x0020 }, - { PUC_COM_POW2(0), 0x18, 0x0028 }, - { PUC_COM_POW2(0), 0x18, 0x0030 }, - { PUC_COM_POW2(0), 0x18, 0x0038 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0008 }, + { PUC_PORT_COM, 0x18, 0x0010 }, + { PUC_PORT_COM, 0x18, 0x0018 }, + { PUC_PORT_COM, 0x18, 0x0020 }, + { PUC_PORT_COM, 0x18, 0x0028 }, + { PUC_PORT_COM, 0x18, 0x0030 }, + { PUC_PORT_COM, 0x18, 0x0038 }, }, }, @@ -1918,14 +1918,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_PLX, PCI_PRODUCT_PLX_9016, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(2), 0x10, 0x0000 }, - { PUC_COM_POW2(2), 0x10, 0x0008 }, - { PUC_COM_POW2(2), 0x10, 0x0010 }, - { PUC_COM_POW2(2), 0x10, 0x0018 }, - { PUC_COM_POW2(2), 0x10, 0x0020 }, - { PUC_COM_POW2(2), 0x10, 0x0028 }, - { PUC_COM_POW2(2), 0x10, 0x0030 }, - { PUC_COM_POW2(2), 0x10, 0x0038 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0008 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0010 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0018 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0020 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0028 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0030 }, + { PUC_PORT_COM_MUL4, 0x10, 0x0038 }, }, }, @@ -1934,10 +1934,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_AVLAB, PCI_PRODUCT_AVLAB_LPPCI4S_2, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -1946,10 +1946,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_AVLAB, PCI_PRODUCT_AVLAB_LPPCI4S, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, @@ -1958,8 +1958,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_AVLAB, PCI_PRODUCT_AVLAB_PCI2S, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, @@ -1968,10 +1968,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_DIGI, PCI_PRODUCT_DIGI_NEO4, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0200 }, - { PUC_COM_POW2(3), 0x10, 0x0400 }, - { PUC_COM_POW2(3), 0x10, 0x0600 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0200 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0400 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0600 }, }, }, @@ -1980,14 +1980,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_DIGI, PCI_PRODUCT_DIGI_NEO8, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0200 }, - { PUC_COM_POW2(3), 0x10, 0x0400 }, - { PUC_COM_POW2(3), 0x10, 0x0600 }, - { PUC_COM_POW2(3), 0x10, 0x0800 }, - { PUC_COM_POW2(3), 0x10, 0x0a00 }, - { PUC_COM_POW2(3), 0x10, 0x0c00 }, - { PUC_COM_POW2(3), 0x10, 0x0e00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0200 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0400 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0600 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0800 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0a00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0c00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0e00 }, }, }, @@ -1996,14 +1996,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_DIGI, PCI_PRODUCT_DIGI_NEO8_PCIE, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0200 }, - { PUC_COM_POW2(3), 0x10, 0x0400 }, - { PUC_COM_POW2(3), 0x10, 0x0600 }, - { PUC_COM_POW2(3), 0x10, 0x0800 }, - { PUC_COM_POW2(3), 0x10, 0x0a00 }, - { PUC_COM_POW2(3), 0x10, 0x0c00 }, - { PUC_COM_POW2(3), 0x10, 0x0e00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0200 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0400 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0600 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0800 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0a00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0c00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0e00 }, }, }, @@ -2016,10 +2016,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_EXAR, PCI_PRODUCT_EXAR_XR17C158, 0x2205, 0x2003 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0200 }, - { PUC_COM_POW2(3), 0x10, 0x0400 }, - { PUC_COM_POW2(3), 0x10, 0x0600 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0200 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0400 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0600 }, }, }, @@ -2027,8 +2027,8 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_EXAR, PCI_PRODUCT_EXAR_XR17C152, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0200 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0200 }, }, }, @@ -2036,10 +2036,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_EXAR, PCI_PRODUCT_EXAR_XR17C154, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0200 }, - { PUC_COM_POW2(3), 0x10, 0x0400 }, - { PUC_COM_POW2(3), 0x10, 0x0600 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0200 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0400 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0600 }, }, }, @@ -2047,14 +2047,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_EXAR, PCI_PRODUCT_EXAR_XR17C158, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0200 }, - { PUC_COM_POW2(3), 0x10, 0x0400 }, - { PUC_COM_POW2(3), 0x10, 0x0600 }, - { PUC_COM_POW2(3), 0x10, 0x0800 }, - { PUC_COM_POW2(3), 0x10, 0x0a00 }, - { PUC_COM_POW2(3), 0x10, 0x0c00 }, - { PUC_COM_POW2(3), 0x10, 0x0e00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0200 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0400 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0600 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0800 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0a00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0c00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0e00 }, }, }, @@ -2062,10 +2062,10 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_EXAR, PCI_PRODUCT_EXAR_XR17V354, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(3), 0x10, 0x0000 }, - { PUC_COM_POW2(3), 0x10, 0x0400 }, - { PUC_COM_POW2(3), 0x10, 0x0800 }, - { PUC_COM_POW2(3), 0x10, 0x0C00 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0000 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0400 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0800 }, + { PUC_PORT_COM_MUL8, 0x10, 0x0C00 }, }, }, @@ -2073,14 +2073,14 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_DRAC_3_VUART, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(7), 0x14, 0x0000 }, + { PUC_PORT_COM_MUL128, 0x14, 0x0000 }, }, }, { /* Dell DRAC 4 Virtual UART */ { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_DRAC_4_VUART, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(7), 0x14, 0x0000 }, + { PUC_PORT_COM_MUL128, 0x14, 0x0000 }, }, }, @@ -2094,174 +2094,174 @@ const struct puc_device_description puc_devs[] = { { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_GLOBALMODEM56,0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "", */ { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_MODEM56, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "", */ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_SERIAL,0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "", */ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_SERIAL_2,0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "", */ { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_SERIAL_GC,0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "", */ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MODEM56, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "", */ { PCI_VENDOR_OXFORD2, PCI_PRODUCT_OXFORD2_OXCB950,0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "Xircom Cardbus 56K Modem", */ { PCI_VENDOR_XIRCOM, PCI_PRODUCT_XIRCOM_MODEM_56K,0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "Xircom CBEM56G Modem", */ { PCI_VENDOR_XIRCOM, PCI_PRODUCT_XIRCOM_CBEM56G, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "Xircom 56k Modem", */ { PCI_VENDOR_XIRCOM, PCI_PRODUCT_XIRCOM_MODEM56, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "WinChipHead CH351 (2S)", */ { PCI_VENDOR_WCH2, PCI_PRODUCT_WCH2_CH351, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, { /* "WinChipHead CH352", */ { PCI_VENDOR_WCH, PCI_PRODUCT_WCH_CH352, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, { /* "WinChipHead CH382 (2S)", */ { PCI_VENDOR_WCH2, PCI_PRODUCT_WCH2_CH382_1, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x00c0 }, - { PUC_COM_POW2(0), 0x10, 0x00c8 }, + { PUC_PORT_COM, 0x10, 0x00c0 }, + { PUC_PORT_COM, 0x10, 0x00c8 }, }, }, { /* "WinChipHead CH382 (2S1P)", */ { PCI_VENDOR_WCH2, PCI_PRODUCT_WCH2_CH382_2, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x00c0 }, - { PUC_COM_POW2(0), 0x10, 0x00c8 }, + { PUC_PORT_COM, 0x10, 0x00c0 }, + { PUC_PORT_COM, 0x10, 0x00c8 }, }, }, { /* "TXIC TX382B (2S)", */ { PCI_VENDOR_TXIC, PCI_PRODUCT_TXIC_TX382B, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, } }, { /* "ASIX AX99100", */ { PCI_VENDOR_ASIX, PCI_PRODUCT_ASIX_AX99100, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, } }, { /* "NetMos NM9820 UART" */ { PCI_VENDOR_NETMOS, PCI_PRODUCT_NETMOS_NM9820, 0, 0 }, { 0xffff, 0xffff, 0, 0 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "MosChip MCS9865 Quad Serial Port" */ { PCI_VENDOR_MOSCHIP, PCI_PRODUCT_MOSCHIP_MCS9865, 0x1000, 0x4 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, - { PUC_COM_POW2(0), 0x18, 0x0000 }, - { PUC_COM_POW2(0), 0x1c, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, + { PUC_PORT_COM, 0x18, 0x0000 }, + { PUC_PORT_COM, 0x1c, 0x0000 }, }, }, { /* "MosChip MCS9865 Dual Serial Port" */ { PCI_VENDOR_MOSCHIP, PCI_PRODUCT_MOSCHIP_MCS9865, 0x1000, 0x2 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x14, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x14, 0x0000 }, }, }, { /* "MosChip MCS9865 Single Serial Port" */ { PCI_VENDOR_MOSCHIP, PCI_PRODUCT_MOSCHIP_MCS9865, 0x1000, 0x1 }, { 0xffff, 0xffff, 0xffff, 0xffff }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "Redhat QEMU PCI Serial" */ { PCI_VENDOR_REDHAT, PCI_PRODUCT_REDHAT_SERIAL, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0000 }, }, }, { /* "Redhat QEMU PCI Serial 2x" */ { PCI_VENDOR_REDHAT, PCI_PRODUCT_REDHAT_SERIAL2, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x10, 0x0008 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0008 }, }, }, { /* "Redhat QEMU PCI Serial 4x" */ { PCI_VENDOR_REDHAT, PCI_PRODUCT_REDHAT_SERIAL4, 0x0000, 0x0000 }, { 0xffff, 0xffff, 0x0000, 0x0000 }, { - { PUC_COM_POW2(0), 0x10, 0x0000 }, - { PUC_COM_POW2(0), 0x10, 0x0008 }, - { PUC_COM_POW2(0), 0x10, 0x0010 }, - { PUC_COM_POW2(0), 0x10, 0x0018 }, + { PUC_PORT_COM, 0x10, 0x0000 }, + { PUC_PORT_COM, 0x10, 0x0008 }, + { PUC_PORT_COM, 0x10, 0x0010 }, + { PUC_PORT_COM, 0x10, 0x0018 }, }, }, }; diff --git a/sys/dev/pci/pucvar.h b/sys/dev/pci/pucvar.h index 2b1745806e2..78824f3fd65 100644 --- a/sys/dev/pci/pucvar.h +++ b/sys/dev/pci/pucvar.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pucvar.h,v 1.13 2011/11/15 22:27:53 deraadt Exp $ */ +/* $OpenBSD: pucvar.h,v 1.14 2018/04/15 00:10:59 jcs Exp $ */ /* $NetBSD: pucvar.h,v 1.2 1999/02/06 06:29:54 cgd Exp $ */ /* @@ -38,6 +38,8 @@ * Author: Christopher G. Demetriou, May 14, 1998. */ +#include <dev/ic/comreg.h> + #define PUC_MAX_PORTS 16 struct puc_device_description { @@ -50,20 +52,30 @@ struct puc_device_description { } ports[PUC_MAX_PORTS]; }; -/* - * For serial ports, the type field also encodes a multiplier - * of the speed. - */ -#define PUC_LPT (0x00 | 0x40) -#define PUC_COM_MUL(mul) (0x80 | 0x40 | (mul)) -#define PUC_COM_POW2(pow2) (0x80 | (pow2)) +struct puc_port_type { + enum { + PUC_PORT_LPT = 1, + PUC_PORT_COM, + PUC_PORT_COM_MUL4, + PUC_PORT_COM_MUL8, + PUC_PORT_COM_MUL10, + PUC_PORT_COM_MUL128, + PUC_PORT_COM_125MHZ, + } type; + u_int32_t freq; +}; -#define PUC_IS_LPT(type) (((type) & 0xc0) == 0x40) -#define PUC_IS_COM(type) (((type) & 0x80) == 0x80) +static const struct puc_port_type puc_port_types[] = { + { PUC_PORT_LPT, 0 }, + { PUC_PORT_COM, COM_FREQ }, + { PUC_PORT_COM_MUL4, COM_FREQ * 4 }, + { PUC_PORT_COM_MUL8, COM_FREQ * 8 }, + { PUC_PORT_COM_MUL10, COM_FREQ * 10 }, + { PUC_PORT_COM_MUL128, COM_FREQ * 128 }, +}; -#define PUC_IS_COM_MUL(type) ((type) & 0x40) -#define PUC_COM_GET_MUL(type) ((type) & 0x3f) -#define PUC_COM_GET_POW2(type) ((type) & 0x3f) +#define PUC_IS_LPT(type) ((type) == PUC_PORT_LPT) +#define PUC_IS_COM(type) ((type) != PUC_PORT_LPT) #define PUC_PORT_BAR_INDEX(bar) (((bar) - PCI_MAPREG_START) / 4) diff --git a/sys/dev/puc/com_puc.c b/sys/dev/puc/com_puc.c index 93947a28126..33a434fba23 100644 --- a/sys/dev/puc/com_puc.c +++ b/sys/dev/puc/com_puc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: com_puc.c,v 1.23 2017/12/30 20:46:59 guenther Exp $ */ +/* $OpenBSD: com_puc.c,v 1.24 2018/04/15 00:10:59 jcs Exp $ */ /* * Copyright (c) 1997 - 1999, Jason Downs. All rights reserved. @@ -82,6 +82,7 @@ com_puc_attach(parent, self, aux) struct com_softc *sc = (void *)self; struct puc_attach_args *pa = aux; const char *intrstr; + int i; /* Grab a PCI interrupt. */ intrstr = pa->intr_string(pa); @@ -99,10 +100,14 @@ com_puc_attach(parent, self, aux) sc->sc_iot = pa->t; sc->sc_ioh = pa->h; sc->sc_iobase = pa->a; - if (PUC_IS_COM_MUL(pa->type)) - sc->sc_frequency = COM_FREQ * PUC_COM_GET_MUL(pa->type); - else - sc->sc_frequency = COM_FREQ * (1 << PUC_COM_GET_POW2(pa->type)); + + sc->sc_frequency = COM_FREQ; + + for (i = 0; i < nitems(puc_port_types); i++) + if (puc_port_types[i].type == pa->type) { + sc->sc_frequency = puc_port_types[i].freq; + break; + } com_attach_subr(sc); } |