diff options
| author | Brad Smith <brad@cvs.openbsd.org> | 2004-12-11 02:06:48 +0000 |
|---|---|---|
| committer | Brad Smith <brad@cvs.openbsd.org> | 2004-12-11 02:06:48 +0000 |
| commit | b04ba64d0d548aba0f6a2887458c06a5de25a17f (patch) | |
| tree | c381fa58c72696854ea5382379fd23bcfa1b05da /sys | |
| parent | c74ab1dd3c68b5bc3acfc22fdb4904bfa45f2f0a (diff) | |
rev 1.51
When reading PHY regs over the i2c bus, the turnaround ACK bit
is read one clock edge too late. This bit is driven low by
slave (as any other input data bits from slave) when the clock
is LOW. The current code did read the bit after the clock was
driven high again.
From FreeBSD
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/pci/if_wb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/dev/pci/if_wb.c b/sys/dev/pci/if_wb.c index 0a3da2f3919..18acb268d39 100644 --- a/sys/dev/pci/if_wb.c +++ b/sys/dev/pci/if_wb.c @@ -1,4 +1,4 @@ -/* $OpenBSD: if_wb.c,v 1.25 2004/09/28 04:37:33 brad Exp $ */ +/* $OpenBSD: if_wb.c,v 1.26 2004/12/11 02:06:47 brad Exp $ */ /* * Copyright (c) 1997, 1998 @@ -379,9 +379,9 @@ int wb_mii_readreg(sc, frame) /* Check for ack */ SIO_CLR(WB_SIO_MII_CLK); DELAY(1); + ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; SIO_SET(WB_SIO_MII_CLK); DELAY(1); - ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; SIO_CLR(WB_SIO_MII_CLK); DELAY(1); SIO_SET(WB_SIO_MII_CLK); |