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authorTheo de Raadt <deraadt@cvs.openbsd.org>2011-04-12 20:29:36 +0000
committerTheo de Raadt <deraadt@cvs.openbsd.org>2011-04-12 20:29:36 +0000
commitb8e52d1ec89088cdfac56aaa08a8e430b1d6d553 (patch)
treece6dea9ea7ee7ed0e9a4d7ee90a94f5a4b3bc5b6 /sys
parentbee5ffa37a4893b46f23549a9bbbb5bbc1be1c5c (diff)
We need to delay 10msec after changing to/from D3 state. note: There are
some broken intel chipsets that require longer delays, we will cope with that later hopefully. ok kettenis
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/pci/pci.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index c073ac705f7..016406167e2 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pci.c,v 1.88 2010/12/30 00:58:22 kettenis Exp $ */
+/* $OpenBSD: pci.c,v 1.89 2011/04/12 20:29:35 deraadt Exp $ */
/* $NetBSD: pci.c,v 1.31 1997/06/06 23:48:04 thorpej Exp $ */
/*
@@ -571,9 +571,14 @@ pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, int state)
}
reg = pci_conf_read(pc, tag, offset + PCI_PMCSR);
if ((reg & PCI_PMCSR_STATE_MASK) != state) {
+ int ostate = reg & PCI_PMCSR_STATE_MASK;
+
pci_conf_write(pc, tag, offset + PCI_PMCSR,
(reg & ~PCI_PMCSR_STATE_MASK) | state);
- return (reg & PCI_PMCSR_STATE_MASK);
+ if (state == PCI_PMCSR_STATE_D3 ||
+ ostate == PCI_PMCSR_STATE_D3)
+ delay(10 * 1000);
+ return (ostate);
}
}
return (state);