Spacing.

3 files changed, 100 insertions, 104 deletions

diff --git a/sys/dev/ic/bwi.c b/sys/dev/ic/bwi.c
index 50822a1c516..6e6e6e20876 100644
--- a/sys/dev/ic/bwi.c
+++ b/sys/dev/ic/bwi.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bwi.c,v 1.47 2007/09/27 05:58:57 mglocker Exp $	*/
+/*	$OpenBSD: bwi.c,v 1.48 2007/09/27 09:19:21 mglocker Exp $	*/
 
 /*
  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
@@ -398,7 +398,7 @@ static const uint32_t	bwi_phy_delay_11g_rev1[] =
 /* RF */
 #define RF_LO_WRITE(mac, lo)	bwi_rf_lo_write((mac), (lo))
 
-#define BWI_RF_2GHZ_CHAN(chan)			\
+#define BWI_RF_2GHZ_CHAN(chan) \
 	(ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
 
 #define BWI_DEFAULT_IDLE_TSSI	52
@@ -3928,7 +3928,6 @@ bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
 #define MAP_MAX	10
 		static const uint16_t map[MAP_MAX] =
 		{ 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
-
 #if 0
 		KKASSERT(rf_atten < MAP_MAX);
 		rf_atten = map[rf_atten];
@@ -7821,9 +7820,9 @@ bwi_ack_rate(struct ieee80211_node *ni, u_int8_t rate)
 	return ack_rate;
 }
 
-#define IEEE80211_OFDM_TXTIME(kbps, frmlen) \
-	(IEEE80211_OFDM_PREAMBLE_TIME + \
-	 IEEE80211_OFDM_SIGNAL_TIME + \
+#define IEEE80211_OFDM_TXTIME(kbps, frmlen)	\
+	(IEEE80211_OFDM_PREAMBLE_TIME +		\
+	 IEEE80211_OFDM_SIGNAL_TIME +		\
 	(IEEE80211_OFDM_NSYMS((kbps), (frmlen)) * IEEE80211_OFDM_SYM_TIME))
 
 #define IEEE80211_OFDM_SYM_TIME			4
@@ -7834,19 +7833,19 @@ bwi_ack_rate(struct ieee80211_node *ni, u_int8_t rate)
 #define IEEE80211_OFDM_PLCP_SERVICE_NBITS	16
 #define IEEE80211_OFDM_TAIL_NBITS		6	
 
-#define IEEE80211_OFDM_NBITS(frmlen) \
-	(IEEE80211_OFDM_PLCP_SERVICE_NBITS + \
-	 ((frmlen) * NBBY) + \
+#define IEEE80211_OFDM_NBITS(frmlen)		\
+	(IEEE80211_OFDM_PLCP_SERVICE_NBITS +	\
+	 ((frmlen) * NBBY) +			\
 	 IEEE80211_OFDM_TAIL_NBITS)
 
-#define IEEE80211_OFDM_NBITS_PER_SYM(kbps) \
+#define IEEE80211_OFDM_NBITS_PER_SYM(kbps)	\
 	(((kbps) * IEEE80211_OFDM_SYM_TIME) / 1000)
 
-#define IEEE80211_OFDM_NSYMS(kbps, frmlen) \
-	howmany(IEEE80211_OFDM_NBITS((frmlen)), \
-		IEEE80211_OFDM_NBITS_PER_SYM((kbps)))
+#define IEEE80211_OFDM_NSYMS(kbps, frmlen)	\
+	howmany(IEEE80211_OFDM_NBITS((frmlen)),	\
+	IEEE80211_OFDM_NBITS_PER_SYM((kbps)))
 
-#define IEEE80211_CCK_TXTIME(kbps, frmlen) \
+#define IEEE80211_CCK_TXTIME(kbps, frmlen)	\
 	(((IEEE80211_CCK_NBITS((frmlen)) * 1000) + (kbps) - 1) / (kbps))
 
 #define IEEE80211_CCK_PREAMBLE_LEN		144
diff --git a/sys/dev/ic/bwireg.h b/sys/dev/ic/bwireg.h
index cd5622c14ed..1d7aa5dd8a6 100644
--- a/sys/dev/ic/bwireg.h
+++ b/sys/dev/ic/bwireg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bwireg.h,v 1.3 2007/09/27 05:58:57 mglocker Exp $	*/
+/*	$OpenBSD: bwireg.h,v 1.4 2007/09/27 09:19:21 mglocker Exp $	*/
 
 /*
  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
@@ -76,7 +76,6 @@
 #define BWI_CONF_LO_REQTO_MASK		0x00000070	/* request timeout */
 #define BWI_CONF_LO_REQTO		3
 
-
 #define BWI_ID_LO			0xff8
 #define BWI_ID_LO_BUSREV_MASK		0xf0000000
 /* Bus revision */
@@ -181,6 +180,7 @@
 #define BWI_MOBJ_CTRL_VAL(objid, ofs)	((objid) << 16 | (ofs))
 #define BWI_MOBJ_DATA			0x164
 #define BWI_MOBJ_DATA_UNALIGN		0x166
+
 /*
  * Memory object IDs
  */
@@ -272,7 +272,7 @@
 #define BWI_PHYINFO_TYPE_11N		5
 #define BWI_PHYINFO_VER_MASK		0xf000
 
-#define BWI_RF_ANTDIV			0x3e2	/* Antenna Diversity?? */
+#define BWI_RF_ANTDIV			0x3e2	/* Antenna Diversity ?? */
 
 #define BWI_PHY_MAGIC_REG1		0x3e4
 #define BWI_PHY_MAGIC_REG1_VAL1		0x3000
@@ -352,11 +352,11 @@
 #define BWI_PCI_SUBDEVICE_BU4306	0x416
 #define BWI_PCI_SUBDEVICE_BCM4309G	0x421
 
-#define BWI_IS_BRCM_BU4306(sc) \
-	((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \
+#define BWI_IS_BRCM_BU4306(sc)					\
+	((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM &&		\
 	 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306)
-#define BWI_IS_BRCM_BCM4309G(sc) \
-	((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \
+#define BWI_IS_BRCM_BCM4309G(sc)				\
+	((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM &&		\
 	 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G)
 
 /*
@@ -385,7 +385,7 @@
  * SPROM card flags
  */
 #define BWI_CARD_F_PA_GPIO9		(1 << 1)	/* GPIO 9 controls PA */
-#define BWI_CARD_F_SW_NRSSI		(1 << 3)	
+#define BWI_CARD_F_SW_NRSSI		(1 << 3)
 #define BWI_CARD_F_NO_SLOWCLK		(1 << 5)	/* no slow clock */
 #define BWI_CARD_F_EXT_LNA		(1 << 12)	/* external LNA */
 #define BWI_CARD_F_ALT_IQ		(1 << 15)	/* alternate I/Q */
@@ -415,19 +415,19 @@
 #define BWI_INTR_TBTT			(1 << 2)
 #define BWI_INTR_EO_ATIM		(1 << 5)	/* End of ATIM */
 #define BWI_INTR_PMQ			(1 << 6)	/* XXX?? */
-#define BWI_INTR_MAC_TXERR		(1 << 9)	
+#define BWI_INTR_MAC_TXERR		(1 << 9)
 #define BWI_INTR_PHY_TXERR		(1 << 11)
 #define BWI_INTR_TIMER1			(1 << 14)
 #define BWI_INTR_RX_DONE		(1 << 15)
 #define BWI_INTR_TX_FIFO		(1 << 16)	/* XXX?? */
-#define BWI_INTR_NOISE			(1 << 18)	
+#define BWI_INTR_NOISE			(1 << 18)
 #define BWI_INTR_RF_DISABLED		(1 << 28)
 #define BWI_INTR_TX_DONE		(1 << 29)
 
-#define BWI_INIT_INTRS \
-	(BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT | \
-	 BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR | \
-	 BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO | \
+#define BWI_INIT_INTRS							\
+	(BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT |		\
+	 BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR |		\
+	 BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO |	\
 	 BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE)
 #define BWI_ALL_INTRS			0xffffffff
 
@@ -463,7 +463,7 @@
  * http://bcm-specs.sipsolutions.net/APHYSetup/FineFrequency
  * G PHY
  */
-#define BWI_PHY_FREQ_11G_REV1 \
+#define BWI_PHY_FREQ_11G_REV1						\
 	0x0089,	0x02e9,	0x0409,	0x04e9,	0x05a9,	0x0669,	0x0709,	0x0789,	\
 	0x0829,	0x08a9,	0x0929,	0x0989,	0x0a09,	0x0a69,	0x0ac9,	0x0b29,	\
 	0x0ba9,	0x0be9,	0x0c49,	0x0ca9,	0x0d09,	0x0d69,	0x0da9,	0x0e09,	\
@@ -511,7 +511,7 @@
  * http://bcm-specs.sipsolutions.net/APHYSetup/rotor_table
  * G PHY Revision 1
  */
-#define BWI_PHY_ROTOR_11G_REV1 \
+#define BWI_PHY_ROTOR_11G_REV1				\
 	0xfeb93ffd, 0xfec63ffd, 0xfed23ffd, 0xfedf3ffd,	\
 	0xfeec3ffe, 0xfef83ffe, 0xff053ffe, 0xff113ffe,	\
 	0xff1e3ffe, 0xff2a3fff, 0xff373fff, 0xff443fff,	\
@@ -531,19 +531,19 @@
  * http://bcm-specs.sipsolutions.net/APHYSetup/noise_scale_table
  */
 /* G PHY Revision [0,2] */
-#define BWI_PHY_NOISE_SCALE_11G_REV2 \
+#define BWI_PHY_NOISE_SCALE_11G_REV2					\
 	0x6c77,	0x5162,	0x3b40,	0x3335,	0x2f2d,	0x2a2a,	0x2527,	0x1f21,	\
 	0x1a1d,	0x1719,	0x1616,	0x1414,	0x1414,	0x1400,	0x1414,	0x1614,	\
 	0x1716,	0x1a19,	0x1f1d,	0x2521,	0x2a27,	0x2f2a,	0x332d,	0x3b35,	\
 	0x5140,	0x6c62,	0x0077
 /* G PHY Revsion 7 */
-#define BWI_PHY_NOISE_SCALE_11G_REV7 \
+#define BWI_PHY_NOISE_SCALE_11G_REV7					\
 	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	\
 	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa400,	0xa4a4,	0xa4a4,	\
 	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	0xa4a4,	\
 	0xa4a4,	0xa4a4,	0x00a4
 /* G PHY generic */
-#define BWI_PHY_NOISE_SCALE_11G \
+#define BWI_PHY_NOISE_SCALE_11G						\
 	0xd8dd,	0xcbd4,	0xbcc0,	0xb6b7,	0xb2b0,	0xadad,	0xa7a9,	0x9fa1,	\
 	0x969b,	0x9195,	0x8f8f,	0x8a8a,	0x8a8a,	0x8a00,	0x8a8a,	0x8f8a,	\
 	0x918f,	0x9695,	0x9f9b,	0xa7a1,	0xada9,	0xb2ad,	0xb6b0,	0xbcb7,	\
@@ -553,7 +553,7 @@
  * http://bcm-specs.sipsolutions.net/APHYSetup/sigma_square_table
  */
 /* G PHY Revision 2 */
-#define BWI_PHY_SIGMA_SQ_11G_REV2 \
+#define BWI_PHY_SIGMA_SQ_11G_REV2					\
 	0x007a,	0x0075,	0x0071,	0x006c,	0x0067,	0x0063,	0x005e,	0x0059,	\
 	0x0054,	0x0050,	0x004b,	0x0046,	0x0042,	0x003d,	0x003d,	0x003d,	\
 	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	0x003d,	\
@@ -562,7 +562,7 @@
 	0x0042,	0x0046,	0x004b,	0x0050,	0x0054,	0x0059,	0x005e,	0x0063,	\
 	0x0067,	0x006c,	0x0071,	0x0075,	0x007a
 /* G PHY Revision (2,7] */
-#define BWI_PHY_SIGMA_SQ_11G_REV7 \
+#define BWI_PHY_SIGMA_SQ_11G_REV7					\
 	0x00de,	0x00dc,	0x00da,	0x00d8,	0x00d6,	0x00d4,	0x00d2,	0x00cf,	\
 	0x00cd,	0x00ca,	0x00c7,	0x00c4,	0x00c1,	0x00be,	0x00be,	0x00be,	\
 	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	0x00be,	\
@@ -575,7 +575,7 @@
  * http://bcm-specs.sipsolutions.net/APHYSetup/retard_table
  * G PHY
  */
-#define BWI_PHY_DELAY_11G_REV1 \
+#define BWI_PHY_DELAY_11G_REV1				\
 	0xdb93cb87, 0xd666cf64, 0xd1fdd358, 0xcda6d826,	\
 	0xca38dd9f, 0xc729e2b4, 0xc469e88e, 0xc26aee2b,	\
 	0xc0def46c, 0xc073fa62, 0xc01d00d5, 0xc0760743,	\
@@ -609,7 +609,7 @@
  * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
  * B PHY
  */
-#define BWI_TXPOWER_MAP_11B \
+#define BWI_TXPOWER_MAP_11B						\
 	0x4d,	0x4c,	0x4b,	0x4a,	0x4a,	0x49,	0x48,	0x47,	\
 	0x47,	0x46,	0x45,	0x45,	0x44,	0x43,	0x42,	0x42,	\
 	0x41,	0x40,	0x3f,	0x3e,	0x3d,	0x3c,	0x3b,	0x3a,	\
@@ -622,7 +622,7 @@
  * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
  * G PHY
  */
-#define BWI_TXPOWER_MAP_11G \
+#define BWI_TXPOWER_MAP_11G						\
 	77,	77,	77,	76,	76,	76,	75,	75,	\
 	74,	74,	73,	73,	73,	72,	72,	71,	\
 	71,	70,	70,	69,	68,	68,	67,	67,	\
diff --git a/sys/dev/ic/bwivar.h b/sys/dev/ic/bwivar.h
index 053d0c824b8..2ec1a91b910 100644
--- a/sys/dev/ic/bwivar.h
+++ b/sys/dev/ic/bwivar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bwivar.h,v 1.13 2007/09/27 05:58:57 mglocker Exp $	*/
+/*	$OpenBSD: bwivar.h,v 1.14 2007/09/27 09:19:21 mglocker Exp $	*/
 
 /*
  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
@@ -57,19 +57,19 @@
 #define BWI_SHRETRY_FB		3
 #define BWI_LGRETRY_FB		2
 
-#define CSR_READ_4(sc, reg)		\
+#define CSR_READ_4(sc, reg)			\
 	bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
-#define CSR_READ_2(sc, reg)		\
+#define CSR_READ_2(sc, reg)			\
 	bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
 
-#define CSR_WRITE_4(sc, reg, val)	\
+#define CSR_WRITE_4(sc, reg, val)		\
 	bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
-#define CSR_WRITE_2(sc, reg, val)	\
+#define CSR_WRITE_2(sc, reg, val)		\
 	bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
 
-#define CSR_SETBITS_4(sc, reg, bits)	\
+#define CSR_SETBITS_4(sc, reg, bits)		\
 	CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
-#define CSR_SETBITS_2(sc, reg, bits)	\
+#define CSR_SETBITS_2(sc, reg, bits)		\
 	CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
 
 #define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
@@ -77,9 +77,9 @@
 #define CSR_FILT_SETBITS_2(sc, reg, filt, bits)	\
 	CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
 
-#define CSR_CLRBITS_4(sc, reg, bits)	\
+#define CSR_CLRBITS_4(sc, reg, bits)		\
 	CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
-#define CSR_CLRBITS_2(sc, reg, bits)	\
+#define CSR_CLRBITS_2(sc, reg, bits)		\
 	CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
 
 struct bwi_desc32 {
@@ -169,23 +169,23 @@ struct bwi_txstats {
 	uint8_t		txs_pad2[2];
 	uint16_t	txs_seq;
 	uint16_t	txs_unknown;
-	uint8_t		txs_pad3[2];		/* Padded to 16bytes */
+	uint8_t		txs_pad3[2];	/* Padded to 16bytes */
 } __packed;
 
 struct bwi_ring_data {
-	uint32_t		rdata_txrx_ctrl;
-	bus_dma_segment_t	rdata_seg;
-	bus_dmamap_t		rdata_dmap;
-	bus_addr_t		rdata_paddr;
+	uint32_t		 rdata_txrx_ctrl;
+	bus_dma_segment_t	 rdata_seg;
+	bus_dmamap_t		 rdata_dmap;
+	bus_addr_t		 rdata_paddr;
 	void			*rdata_desc;
 };
 
 struct bwi_txbuf {
 	struct mbuf		*tb_mbuf;
-	bus_dmamap_t		tb_dmap;
+	bus_dmamap_t		 tb_dmap;
 
 	struct ieee80211_node	*tb_ni;
-	int			tb_rate_idx[2];
+	int			 tb_rate_idx[2];
 };
 
 struct bwi_txbuf_data {
@@ -196,8 +196,8 @@ struct bwi_txbuf_data {
 
 struct bwi_rxbuf {
 	struct mbuf		*rb_mbuf;
-	bus_addr_t		rb_paddr;
-	bus_dmamap_t		rb_dmap;
+	bus_addr_t		 rb_paddr;
+	bus_dmamap_t		 rb_dmap;
 };
 
 struct bwi_rxbuf_data {
@@ -207,18 +207,18 @@ struct bwi_rxbuf_data {
 };
 
 struct bwi_txstats_data {
-	bus_dma_segment_t	stats_ring_seg;
-	bus_dmamap_t		stats_ring_dmap;
-	bus_addr_t		stats_ring_paddr;
+	bus_dma_segment_t	 stats_ring_seg;
+	bus_dmamap_t		 stats_ring_dmap;
+	bus_addr_t		 stats_ring_paddr;
 	void			*stats_ring;
 
-	bus_dma_segment_t	stats_seg;
-	bus_dmamap_t		stats_dmap;
-	bus_addr_t		stats_paddr;
+	bus_dma_segment_t	 stats_seg;
+	bus_dmamap_t		 stats_dmap;
+	bus_addr_t		 stats_paddr;
 	struct bwi_txstats	*stats;
 
-	uint32_t		stats_ctrl_base;
-	int			stats_idx;
+	uint32_t		 stats_ctrl_base;
+	int			 stats_idx;
 };
 
 struct bwi_fwhdr {
@@ -280,9 +280,9 @@ do {						\
 } while (0)
 
 #define BWI_REGWIN_EXIST(rw)	((rw)->rw_flags & BWI_REGWIN_F_EXIST)
-#define BWI_GPIO_REGWIN(sc) \
-	(BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
-		&(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
+#define BWI_GPIO_REGWIN(sc)				\
+	(BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ?	\
+	&(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
 
 struct bwi_mac;
 
@@ -381,19 +381,18 @@ struct bwi_rf {
 struct fw_image;
 
 struct bwi_mac {
-	struct bwi_regwin	mac_regwin;	/* MUST be first field */
-#define mac_rw_flags	mac_regwin.rw_flags
-#define mac_type	mac_regwin.rw_type
-#define mac_id		mac_regwin.rw_id
-#define mac_rev		mac_regwin.rw_rev
-
+	struct bwi_regwin	 mac_regwin;	/* MUST be first field */
+#define mac_rw_flags		 mac_regwin.rw_flags
+#define mac_type		 mac_regwin.rw_type
+#define mac_id			 mac_regwin.rw_id
+#define mac_rev			 mac_regwin.rw_rev
 	struct bwi_softc	*mac_sc;
 
-	struct bwi_phy		mac_phy;	/* PHY I/F */
-	struct bwi_rf		mac_rf;		/* RF I/F */
+	struct bwi_phy		 mac_phy;	/* PHY I/F */
+	struct bwi_rf		 mac_rf;	/* RF I/F */
 
-	struct bwi_tpctl	mac_tpctl;	/* TX power control */
-	uint32_t		mac_flags;	/* BWI_MAC_F_ */
+	struct bwi_tpctl	 mac_tpctl;	/* TX power control */
+	uint32_t		 mac_flags;	/* BWI_MAC_F_ */
 
 	uint8_t			*mac_ucode;
 	size_t			 mac_ucode_size;
@@ -416,9 +415,7 @@ struct bwi_mac {
 #define BWI_CREATE_MAC(mac, sc, id, rev)	\
 do {						\
 	BWI_CREATE_REGWIN(&(mac)->mac_regwin,	\
-			  (id),			\
-			  BWI_REGWIN_T_MAC,	\
-			  (rev));		\
+	    (id), BWI_REGWIN_T_MAC, (rev));	\
 	(mac)->mac_sc = (sc);			\
 } while (0)
 
@@ -546,25 +543,25 @@ struct bwi_softc {
 	uint32_t		 (*sc_conf_read)(void *, uint32_t);
 
 	/* Sysctl variables */
-	int			sc_fw_version;	/* BWI_FW_VERSION[34] */
-	int			sc_dwell_time;	/* milliseconds */
+	int			 sc_fw_version;	/* BWI_FW_VERSION[34] */
+	int			 sc_dwell_time;	/* milliseconds */
 
 #if NBPFILTER > 0
-        caddr_t                 sc_drvbpf;
+        caddr_t                  sc_drvbpf;
  
         union {
                 struct bwi_rx_radiotap_hdr th;
                 uint8_t pad[64];
-        }                       sc_rxtapu;
-#define sc_rxtap                sc_rxtapu.th
-        int                     sc_rxtap_len;
+        }                        sc_rxtapu;
+#define sc_rxtap                 sc_rxtapu.th
+        int                      sc_rxtap_len;
  
         union {
                 struct bwi_tx_radiotap_hdr th;
                 uint8_t pad[64];
-        }                       sc_txtapu;
-#define sc_txtap                sc_txtapu.th
-        int                     sc_txtap_len;
+        }                        sc_txtapu;
+#define sc_txtap                 sc_txtapu.th
+        int                      sc_txtap_len;
 #endif
 };
 
@@ -573,33 +570,33 @@ struct bwi_softc {
 
 #define abs(a)	__builtin_abs(a)
 
-#define MOBJ_WRITE_2(mac, objid, ofs, val)	\
+#define MOBJ_WRITE_2(mac, objid, ofs, val)			\
 	bwi_memobj_write_2((mac), (objid), (ofs), (val))
-#define MOBJ_WRITE_4(mac, objid, ofs, val)	\
+#define MOBJ_WRITE_4(mac, objid, ofs, val)			\
 	bwi_memobj_write_4((mac), (objid), (ofs), (val))
-#define MOBJ_READ_2(mac, objid, ofs)		\
+#define MOBJ_READ_2(mac, objid, ofs)				\
 	bwi_memobj_read_2((mac), (objid), (ofs))
-#define MOBJ_READ_4(mac, objid, ofs)		\
+#define MOBJ_READ_4(mac, objid, ofs)				\
 	bwi_memobj_read_4((mac), (objid), (ofs))
 
-#define MOBJ_SETBITS_4(mac, objid, ofs, bits)	\
-	MOBJ_WRITE_4((mac), (objid), (ofs),	\
-		     MOBJ_READ_4((mac), (objid), (ofs)) | (bits))
-#define MOBJ_CLRBITS_4(mac, objid, ofs, bits)	\
-	MOBJ_WRITE_4((mac), (objid), (ofs),	\
-		     MOBJ_READ_4((mac), (objid), (ofs)) & ~(bits))
+#define MOBJ_SETBITS_4(mac, objid, ofs, bits)			\
+	MOBJ_WRITE_4((mac), (objid), (ofs),			\
+	MOBJ_READ_4((mac), (objid), (ofs)) | (bits))
+#define MOBJ_CLRBITS_4(mac, objid, ofs, bits)			\
+	MOBJ_WRITE_4((mac), (objid), (ofs),			\
+	MOBJ_READ_4((mac), (objid), (ofs)) & ~(bits))
 
-#define MOBJ_FILT_SETBITS_2(mac, objid, ofs, filt, bits) \
-	MOBJ_WRITE_2((mac), (objid), (ofs),	\
-		     (MOBJ_READ_2((mac), (objid), (ofs)) & (filt)) | (bits))
+#define MOBJ_FILT_SETBITS_2(mac, objid, ofs, filt, bits)	\
+	MOBJ_WRITE_2((mac), (objid), (ofs),			\
+	(MOBJ_READ_2((mac), (objid), (ofs)) & (filt)) | (bits))
 
 #define TMPLT_WRITE_4(mac, ofs, val)	bwi_tmplt_write_4((mac), (ofs), (val))
 
 #define HFLAGS_WRITE(mac, flags)	bwi_hostflags_write((mac), (flags))
 #define HFLAGS_READ(mac)		bwi_hostflags_read((mac))
-#define HFLAGS_CLRBITS(mac, bits)	\
+#define HFLAGS_CLRBITS(mac, bits)				\
 	HFLAGS_WRITE((mac), HFLAGS_READ((mac)) | (bits))
-#define HFLAGS_SETBITS(mac, bits)	\
+#define HFLAGS_SETBITS(mac, bits)				\
 	HFLAGS_WRITE((mac), HFLAGS_READ((mac)) & ~(bits))
 
 /* PHY */