diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2022-06-21 09:46:34 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2022-06-21 09:46:34 +0000 |
| commit | de15e28a04f51c3150b749406134c12fb1bbe97f (patch) | |
| tree | e9ee10c0ef9af797cb7625eb718a73334f1bbac8 /sys | |
| parent | 2c4996bd801d0f1adabe59891da5d4b1cb96a959 (diff) | |
drm/i915/adlp: Implement workaround 16013190616
From Jose Roberto de Souza
9556829ce4d0618ae4295af8e4b3dd7e38f43598 in mainline linux
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/pci/drm/i915/display/intel_display_power.c | 5 | ||||
| -rw-r--r-- | sys/dev/pci/drm/i915/i915_reg.h | 7 |
2 files changed, 9 insertions, 3 deletions
diff --git a/sys/dev/pci/drm/i915/display/intel_display_power.c b/sys/dev/pci/drm/i915/display/intel_display_power.c index a6314e0fe61..06c97616337 100644 --- a/sys/dev/pci/drm/i915/display/intel_display_power.c +++ b/sys/dev/pci/drm/i915/display/intel_display_power.c @@ -433,6 +433,11 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : SKL_PW_CTL_IDX_TO_PG(pw_idx); + + /* Wa_16013190616:adlp */ + if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); + /* * For PW1 we have to wait both for the PW0/PG0 fuse state * before enabling the power well and PW1/PG1's own fuse diff --git a/sys/dev/pci/drm/i915/i915_reg.h b/sys/dev/pci/drm/i915/i915_reg.h index 3c70aa5229e..9846d9a373e 100644 --- a/sys/dev/pci/drm/i915/i915_reg.h +++ b/sys/dev/pci/drm/i915/i915_reg.h @@ -8304,9 +8304,10 @@ enum { #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) -#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) -#define ICL_DELAY_PMRSP (1 << 22) -#define MASK_WAKEMEM (1 << 13) +#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) +#define ICL_DELAY_PMRSP REG_BIT(22) +#define DISABLE_FLR_SRC REG_BIT(15) +#define MASK_WAKEMEM REG_BIT(13) #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) |