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authorPatrick Wildt <patrick@cvs.openbsd.org>2024-04-01 11:16:12 +0000
committerPatrick Wildt <patrick@cvs.openbsd.org>2024-04-01 11:16:12 +0000
commitf978ecb677dc0f6ca2d5e4645363dc2e6cb164c3 (patch)
tree47e866cfc7fb4eed241fd73baec52130f8508e3a /sys
parent3aec8e77314a8e38fc6bd092ca11c7fac19da713 (diff)
Add clocks for the RK3588 PWM controller.
ok kettenis@
Diffstat (limited to 'sys')
-rw-r--r--sys/dev/fdt/rkclock.c17
-rw-r--r--sys/dev/fdt/rkclock_clocks.h3
2 files changed, 19 insertions, 1 deletions
diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index e7ee863951c..81aca118463 100644
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: rkclock.c,v 1.87 2024/03/06 14:55:22 kettenis Exp $ */
+/* $OpenBSD: rkclock.c,v 1.88 2024/04/01 11:16:11 patrick Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
@@ -3918,6 +3918,21 @@ rk3568_pmu_reset(void *cookie, uint32_t *cells, int on)
const struct rkclock rk3588_clocks[] = {
{
+ RK3588_CLK_PWM1, RK3588_CRU_CLKSEL_CON(59),
+ SEL(13, 12), 0,
+ { RK3588_CLK_100M_SRC, RK3588_CLK_50M_SRC, RK3588_XIN24M },
+ },
+ {
+ RK3588_CLK_PWM2, RK3588_CRU_CLKSEL_CON(59),
+ SEL(15, 14), 0,
+ { RK3588_CLK_100M_SRC, RK3588_CLK_50M_SRC, RK3588_XIN24M },
+ },
+ {
+ RK3588_CLK_PWM3, RK3588_CRU_CLKSEL_CON(60),
+ SEL(1, 0), 0,
+ { RK3588_CLK_100M_SRC, RK3588_CLK_50M_SRC, RK3588_XIN24M },
+ },
+ {
RK3588_ACLK_BUS_ROOT, RK3588_CRU_CLKSEL_CON(38),
SEL(5, 5), DIV(4, 0),
{ RK3588_PLL_GPLL, RK3588_PLL_CPLL }
diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 7a593c44791..793c1a02103 100644
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -410,6 +410,9 @@
#define RK3588_PLL_NPLL 7
#define RK3588_PLL_PPLL 8
+#define RK3588_CLK_PWM1 76
+#define RK3588_CLK_PWM2 79
+#define RK3588_CLK_PWM3 82
#define RK3588_ACLK_BUS_ROOT 113
#define RK3588_CLK_I2C1 131
#define RK3588_CLK_I2C2 132