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authorTheo de Raadt <deraadt@cvs.openbsd.org>2017-03-16 22:05:47 +0000
committerTheo de Raadt <deraadt@cvs.openbsd.org>2017-03-16 22:05:47 +0000
commit3252c560587e11ada3fac69f4f550beb56bbfd57 (patch)
tree72f25576a4432971786b9776212f75e77e01d356 /usr.sbin/pcidump
parentca25d08645729bc2922115d6893f39a4c8396aef (diff)
Print PCIe Extended Capabilities, from Simon Mages
ok kettenis mlarkin
Diffstat (limited to 'usr.sbin/pcidump')
-rw-r--r--usr.sbin/pcidump/pcidump.c68
1 files changed, 66 insertions, 2 deletions
diff --git a/usr.sbin/pcidump/pcidump.c b/usr.sbin/pcidump/pcidump.c
index 395d780dbbc..73d9e7c24e9 100644
--- a/usr.sbin/pcidump/pcidump.c
+++ b/usr.sbin/pcidump/pcidump.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pcidump.c,v 1.41 2017/01/04 03:35:29 dlg Exp $ */
+/* $OpenBSD: pcidump.c,v 1.42 2017/03/16 22:05:46 deraadt Exp $ */
/*
* Copyright (c) 2006, 2007 David Gwynne <loki@animata.net>
@@ -102,6 +102,39 @@ const char *pci_capnames[] = {
"PCI Advanced Features"
};
+const char *pci_enhanced_capnames[] = {
+ "Unknown",
+ "Advanced Error Reporting",
+ "Virtual Channel Capability",
+ "Device Serial Number",
+ "Power Budgeting",
+ "Root Complex Link Declaration",
+ "Root Complex Internal Link Control",
+ "Root Complex Event Collector",
+ "Multi-Function VC Capability",
+ "Virtual Channel Capability",
+ "Root Complex/Root Bridge",
+ "Vendor-Specific",
+ "Config Access",
+ "Access Control Services",
+ "Alternate Routing ID",
+ "Address Translation Services",
+ "Single Root I/O Virtualization",
+ "Multi Root I/O Virtualization",
+ "Multicast",
+ "Page Request Interface",
+ "Reserved for AMD",
+ "Resizable BAR",
+ "Dynamic Power Allocation",
+ "TPH Requester",
+ "Latency Tolerance Reporting",
+ "Secondary PCIe Capability",
+ "Protocol Multiplexing",
+ "Process Address Space ID",
+ "Downstream Port Containment",
+ "Precision Time Measurement",
+};
+
int
main(int argc, char *argv[])
{
@@ -356,6 +389,35 @@ dump_pcie_linkspeed(int bus, int dev, int func, uint8_t ptr)
}
void
+dump_pcie_enhanced_caplist(int bus, int dev, int func)
+{
+ u_int32_t reg;
+ u_int16_t ptr;
+ u_int16_t ecap;
+
+ ptr = PCI_PCIE_ECAP;
+
+ do {
+ if (pci_read(bus, dev, func, ptr, &reg) != 0)
+ return;
+
+ if (PCI_PCIE_ECAP_ID(reg) == 0xffff &&
+ PCI_PCIE_ECAP_NEXT(reg) == PCI_PCIE_ECAP_LAST)
+ return;
+
+ ecap = PCI_PCIE_ECAP_ID(reg);
+ if (ecap >= nitems(pci_enhanced_capnames))
+ ecap = 0;
+
+ printf("\t0x%04x: Enhanced Capability 0x%02x: ", ptr, ecap);
+ printf("%s\n", pci_enhanced_capnames[ecap]);
+
+ ptr = PCI_PCIE_ECAP_NEXT(reg);
+
+ } while (ptr != PCI_PCIE_ECAP_LAST);
+}
+
+void
dump_caplist(int bus, int dev, int func, u_int8_t ptr)
{
u_int32_t reg;
@@ -379,8 +441,10 @@ dump_caplist(int bus, int dev, int func, u_int8_t ptr)
printf("%s\n", pci_capnames[cap]);
if (cap == PCI_CAP_PWRMGMT)
dump_pci_powerstate(bus, dev, func, ptr);
- if (cap == PCI_CAP_PCIEXPRESS)
+ if (cap == PCI_CAP_PCIEXPRESS) {
dump_pcie_linkspeed(bus, dev, func, ptr);
+ dump_pcie_enhanced_caplist(bus, dev, func);
+ }
ptr = PCI_CAPLIST_NEXT(reg);
}
}