diff options
25 files changed, 2194 insertions, 172 deletions
diff --git a/sys/arch/m68k/060sp/Makefile.inc b/sys/arch/m68k/060sp/Makefile.inc index 3134896ea45..2c764e653c8 100644 --- a/sys/arch/m68k/060sp/Makefile.inc +++ b/sys/arch/m68k/060sp/Makefile.inc @@ -1,13 +1,13 @@ # -# $OpenBSD: Makefile.inc,v 1.2 1996/05/30 22:13:56 niklas Exp $ -# $NetBSD: Makefile.inc,v 1.1 1996/05/15 21:06:19 is Exp $ +# $OpenBSD: Makefile.inc,v 1.3 1997/07/06 07:46:18 downsj Exp $ +# $NetBSD: Makefile.inc,v 1.2 1997/05/07 07:15:43 mycroft Exp $ # # NOTE: $S must correspond to the top of the `sys' tree 060SPSRCDIR= $S/arch/m68k/060sp 060SPOBJDIR!= cd $(060SPSRCDIR); \ - printf "xxx:\n\techo \$${.OBJDIR}\n" | $(MAKE) -r -s -f - xxx + printf "xxx: .MAKE\n\t@echo \$${.OBJDIR}\n" | $(MAKE) -s -f- 060SPOBJ= $(060SPOBJDIR)/060sp.o diff --git a/sys/arch/m68k/060sp/netbsd.S b/sys/arch/m68k/060sp/netbsd.S index dec9149c86a..fe9e15449f1 100644 --- a/sys/arch/m68k/060sp/netbsd.S +++ b/sys/arch/m68k/060sp/netbsd.S @@ -1,6 +1,6 @@ # -# $OpenBSD: netbsd.S,v 1.2 1996/05/30 22:15:02 niklas Exp $ -# $NetBSD: netbsd.S,v 1.1 1996/05/15 21:06:24 is Exp $ +# $OpenBSD: netbsd.S,v 1.3 1997/07/06 07:46:19 downsj Exp $ +# $NetBSD: netbsd.S,v 1.3 1997/06/27 23:32:09 is Exp $ # #~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP @@ -94,19 +94,19 @@ # .global _060_dmem_write _060_dmem_write: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state beqs user_write super_write: - moveb a0@+,a1@+ |# copy 1 byte + moveb a0@+,a1@+ |# copy 1 byte subql #0x1,d0 |# decr byte counter - bnes super_write |# quit if ctr = 0 + bnes super_write |# quit if ctr = 0 clrl d1 |# return success rts user_write: movel d0,sp@- |# pass: counter movel a1,sp@- |# pass: user dst movel a0,sp@- |# pass: supervisor src - bsrl _copyout |# write byte to user mem + bsrl _copyout |# write byte to user mem movel d0,d1 |# return success addl #0xc,sp |# clear 3 lw params rts @@ -128,12 +128,12 @@ user_write: .global _060_dmem_read _060_imem_read: _060_dmem_read: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state beqs user_read super_read: - moveb a0@+,a1@+ |# copy 1 byte + moveb a0@+,a1@+ |# copy 1 byte subql #0x1,d0 |# decr byte counter - bnes super_read |# quit if ctr = 0 + bnes super_read |# quit if ctr = 0 clrl d1 |# return success rts user_read: @@ -159,12 +159,12 @@ user_read: # .global _060_dmem_read_byte _060_dmem_read_byte: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state bnes dmrbs |# supervisor dmrbu: clrl sp@- |# clear space on stack for result - movel #0x1,sp@- |# pass: # bytes to copy - pea sp@(0x7) |# pass: dst addr (stack) + movel #0x1,sp@- |# pass: # bytes to copy + pea sp@(0x7) |# pass: dst addr (stack) movel a0,sp@- |# pass: src addr (user mem) bsrl _copyin |# "copy in" the data movel d0,d1 |# return success @@ -196,12 +196,12 @@ dmrbs: _060_imem_read_word: _060_dmem_read_word: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state bnes dmrws |# supervisor dmrwu: clrl sp@- |# clear result space on stack - movel #0x2,sp@- |# pass: # bytes to copy - pea sp@(0x6) |# pass: dst addr (stack) + movel #0x2,sp@- |# pass: # bytes to copy + pea sp@(0x6) |# pass: dst addr (stack) movel a0,sp@- |# pass: src addr (user mem) bsrl _copyin |# "copy in" the data movel d0,d1 |# return success @@ -236,12 +236,12 @@ dmrws: _060_imem_read_long: _060_dmem_read_long: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state bnes dmrls |# supervisor dmrlu: subql #0x4,sp |# clear result space on stack - movel #0x4,sp@- |# pass: # bytes to copy - pea sp@(0x4) |# pass: dst addr (stack) + movel #0x4,sp@- |# pass: # bytes to copy + pea sp@(0x4) |# pass: dst addr (stack) movel a0,sp@- |# pass: src addr (user mem) bsrl _copyin |# "copy in" the data movel d0,d1 |# return success @@ -267,16 +267,16 @@ dmrls: # .global _060_dmem_write_byte _060_dmem_write_byte: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state bnes dmwbs |# supervisor dmwbu: movel d0,sp@- |# put src on stack - movel #0x1,sp@- |# pass: # bytes to copy + movel #0x1,sp@- |# pass: # bytes to copy movel a0,sp@- |# pass: dst addr (user mem) - pea sp@(0xb) |# pass: src addr (stack) - bsrl _copyout |# "copy out" the data + pea sp@(0xb) |# pass: src addr (stack) + bsrl _copyout |# "copy out" the data movel d0,d1 |# return success - addl #0x10,sp |# delete params + src + addl #0x10,sp |# delete params + src rts dmwbs: moveb d0,a0@ |# store super byte @@ -297,16 +297,16 @@ dmwbs: # .global _060_dmem_write_word _060_dmem_write_word: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state bnes dmwws |# supervisor dmwwu: movel d0,sp@- |# put src on stack - movel #0x2,sp@- |# pass: # bytes to copy + movel #0x2,sp@- |# pass: # bytes to copy movel a0,sp@- |# pass: dst addr (user mem) - pea sp@(0xa) |# pass: src addr (stack) - bsrl _copyout |# "copy out" the data + pea sp@(0xa) |# pass: src addr (stack) + bsrl _copyout |# "copy out" the data movel d0,d1 |# return success - addl #0x10,sp |# delete params + src + addl #0x10,sp |# delete params + src rts dmwws: movew d0,a0@ |# store super word @@ -327,16 +327,16 @@ dmwws: # .global _060_dmem_write_long _060_dmem_write_long: - btst #0x5,a6@(0x4) |# check for supervisor state + btst #0x5,a6@(0x4) |# check for supervisor state bnes dmwls |# supervisor dmwlu: movel d0,sp@- |# put src on stack - movel #0x4,sp@- |# pass: # bytes to copy + movel #0x4,sp@- |# pass: # bytes to copy movel a0,sp@- |# pass: dst addr (user mem) - pea sp@(0x8) |# pass: src addr (stack) - bsrl _copyout |# "copy out" the data + pea sp@(0x8) |# pass: src addr (stack) + bsrl _copyout |# "copy out" the data movel d0,d1 |# return success - addl #0x10,sp |# delete params + src + addl #0x10,sp |# delete params + src rts dmwls: movel d0,a0@ |# store super longword @@ -354,9 +354,9 @@ dmwls: # # The sample code below simply executes an "rte". # - .global _060_real_trace + .global _060_real_trace,_trace _060_real_trace: - rte + jra _trace # # _060_real_access(): @@ -366,14 +366,12 @@ _060_real_trace: # handler for access error exceptions. The exception stack frame is an # 8-word access error frame. # -# The sample routine below simply executes an "rte" instruction which -# is most likely the incorrect thing to do and could put the system -# into an infinite loop. +# We jump directly to the 68060 buserr handler. +# If we had a sane ld, we could use use that entry point directly... # - .global _060_real_access + .globl _060_real_access,_buserr60 _060_real_access: - .globl _buserr - jmp _buserr + jra _buserr60 .include "inetbsd.S" .include "fnetbsd.S" diff --git a/sys/arch/m68k/conf/files.m68k b/sys/arch/m68k/conf/files.m68k index 26908c6e68e..48c49bcf276 100644 --- a/sys/arch/m68k/conf/files.m68k +++ b/sys/arch/m68k/conf/files.m68k @@ -1,11 +1,12 @@ -# $OpenBSD: files.m68k,v 1.7 1997/03/26 08:23:52 downsj Exp $ -# $NetBSD: files.m68k,v 1.16 1997/02/12 01:01:07 gwr Exp $ +# $OpenBSD: files.m68k,v 1.8 1997/07/06 07:46:20 downsj Exp $ +# $NetBSD: files.m68k,v 1.18 1997/06/06 23:15:28 veego Exp $ # file arch/m68k/m68k/db_disasm.c ddb file arch/m68k/m68k/db_interface.c ddb file arch/m68k/m68k/db_trace.c ddb file arch/m68k/m68k/in_cksum.c inet file arch/m68k/m68k/kgdb_m68k.c kgdb +file arch/m68k/m68k/m68k_machdep.c file arch/m68k/m68k/mappedcopy.c mappedcopy file arch/m68k/m68k/ns_cksum.c ns file arch/m68k/m68k/oc_cksum.s inet diff --git a/sys/arch/m68k/fpsp/Makefile b/sys/arch/m68k/fpsp/Makefile index 813d9f2a9ec..b277eb8b951 100644 --- a/sys/arch/m68k/fpsp/Makefile +++ b/sys/arch/m68k/fpsp/Makefile @@ -1,5 +1,5 @@ -# $OpenBSD: Makefile,v 1.12 1997/03/25 14:31:07 niklas Exp $ -# $NetBSD: Makefile,v 1.4 1994/10/26 07:48:46 cgd Exp $ +# $OpenBSD: Makefile,v 1.13 1997/07/06 07:46:20 downsj Exp $ +# $NetBSD: Makefile,v 1.6 1997/04/25 22:17:33 veego Exp $ # MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP # M68000 Hi-Performance Microprocessor Division @@ -39,7 +39,7 @@ TARGET = fpsp -AS ?= as -m68040 +AS = cc -x assembler-with-cpp -traditional-cpp -c -m68040 -I${.CURDIR} LD ?= ld # diff --git a/sys/arch/m68k/fpsp/Makefile.inc b/sys/arch/m68k/fpsp/Makefile.inc index 7ecc5ee709a..d1c2f782316 100644 --- a/sys/arch/m68k/fpsp/Makefile.inc +++ b/sys/arch/m68k/fpsp/Makefile.inc @@ -1,12 +1,12 @@ -# $OpenBSD: Makefile.inc,v 1.3 1997/01/13 11:51:08 niklas Exp $ -# $NetBSD: Makefile.inc,v 1.4 1996/10/29 00:11:27 scottr Exp $ +# $OpenBSD: Makefile.inc,v 1.4 1997/07/06 07:46:21 downsj Exp $ +# $NetBSD: Makefile.inc,v 1.5 1997/05/07 07:15:44 mycroft Exp $ # # NOTE: $S must correspond to the top of the `sys' tree FPSPSRCDIR= $S/arch/m68k/fpsp FPSPOBJDIR!= cd $(FPSPSRCDIR); \ - printf "xxx:\n\techo \$${.OBJDIR}\n" | $(MAKE) -r -s -f - xxx + printf "xxx: .MAKE\n\t@echo \$${.OBJDIR}\n" | $(MAKE) -s -f- FPSPOBJ= $(FPSPOBJDIR)/fpsp.o diff --git a/sys/arch/m68k/fpsp/netbsd.sa b/sys/arch/m68k/fpsp/netbsd.sa index 013d372c8f9..6fa7c6b7d5d 100644 --- a/sys/arch/m68k/fpsp/netbsd.sa +++ b/sys/arch/m68k/fpsp/netbsd.sa @@ -1,5 +1,5 @@ -* $OpenBSD: netbsd.sa,v 1.2 1996/05/29 21:05:32 niklas Exp $ -* $NetBSD: netbsd.sa,v 1.2 1994/10/26 07:49:19 cgd Exp $ +* $OpenBSD: netbsd.sa,v 1.3 1997/07/06 07:46:21 downsj Exp $ +* $NetBSD: netbsd.sa,v 1.3 1997/04/25 02:26:04 thorpej Exp $ * MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP * M68000 Hi-Performance Microprocessor Division @@ -71,8 +71,13 @@ SKELETON IDNT 2,1 Motorola 040 Floating Point Software Package include fpsp.h +* +* XXX Note, this is NOT valid Motorola syntax, but what else can we do? +* +#include "../include/asm.h" + xref b1238_fix - xref _mmutype + xref _C_LABEL(mmutype) * * Divide by Zero exception @@ -82,15 +87,15 @@ SKELETON IDNT 2,1 Motorola 040 Floating Point Software Package xdef dz xdef real_dz dz: - cmp.l #-2,_mmutype - bne.l _fpfault + cmp.l #-2,_C_LABEL(mmutype) + bne.l _C_LABEL(fpfault) real_dz: link a6,#-LOCAL_SIZE fsave -(sp) bclr.b #E1,E_BYTE(a6) frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * Inexact exception @@ -116,8 +121,8 @@ real_dz: xdef real_inex xdef inex inex: - cmp.l #-2,_mmutype - bne.l _fpfault + cmp.l #-2,_C_LABEL(mmutype) + bne.l _C_LABEL(fpfault) link a6,#-LOCAL_SIZE fsave -(sp) cmpi.b #VER_40,(sp) ;test version number @@ -176,7 +181,7 @@ inex_cke1: inex_done: frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * Overflow exception @@ -185,9 +190,9 @@ inex_done: xdef real_ovfl xdef ovfl ovfl: - cmp.l #-2,_mmutype + cmp.l #-2,_C_LABEL(mmutype) beq.l fpsp_ovfl - jmp _fpfault + jmp _C_LABEL(fpfault) real_ovfl: link a6,#-LOCAL_SIZE fsave -(sp) @@ -197,7 +202,7 @@ real_ovfl: ovfl_done: frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * Underflow exception @@ -206,9 +211,9 @@ ovfl_done: xdef real_unfl xdef unfl unfl: - cmp.l #-2,_mmutype + cmp.l #-2,_C_LABEL(mmutype) beq.l fpsp_unfl - jmp _fpfault + jmp _C_LABEL(fpfault) real_unfl: link a6,#-LOCAL_SIZE fsave -(sp) @@ -218,7 +223,7 @@ real_unfl: unfl_done: frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * Signalling NAN exception @@ -227,16 +232,16 @@ unfl_done: xdef real_snan xdef snan snan: - cmp.l #-2,_mmutype + cmp.l #-2,_C_LABEL(mmutype) beq.l fpsp_snan - jmp _fpfault + jmp _C_LABEL(fpfault) real_snan: link a6,#-LOCAL_SIZE fsave -(sp) bclr.b #E1,E_BYTE(a6) ;snan is always an E1 exception frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * Operand Error exception @@ -245,16 +250,16 @@ real_snan: xdef real_operr xdef operr operr: - cmp.l #-2,_mmutype + cmp.l #-2,_C_LABEL(mmutype) beq.l fpsp_operr - jmp _fpfault + jmp _C_LABEL(fpfault) real_operr: link a6,#-LOCAL_SIZE fsave -(sp) bclr.b #E1,E_BYTE(a6) ;operr is always an E1 exception frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * BSUN exception @@ -265,9 +270,9 @@ real_operr: xdef real_bsun xdef bsun bsun: - cmp.l #-2,_mmutype + cmp.l #-2,_C_LABEL(mmutype) beq.l fpsp_bsun - jmp _fpfault + jmp _C_LABEL(fpfault) real_bsun: link a6,#-LOCAL_SIZE fsave -(sp) @@ -277,7 +282,7 @@ real_bsun: fmove.l (sp)+,FPSR frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * F-line exception @@ -290,11 +295,11 @@ real_bsun: xdef real_fline xdef fline fline: - cmp.l #-2,_mmutype + cmp.l #-2,_C_LABEL(mmutype) beq.l fpsp_fline - jmp _fpfault + jmp _C_LABEL(fpfault) real_fline: - jmp _fpfault + jmp _C_LABEL(fpfault) * * Unsupported data type exception @@ -303,16 +308,16 @@ real_fline: xdef real_unsupp xdef unsupp unsupp: - cmp.l #-2,_mmutype + cmp.l #-2,_C_LABEL(mmutype) beq.l fpsp_unsupp - jmp _fpfault + jmp _C_LABEL(fpfault) real_unsupp: link a6,#-LOCAL_SIZE fsave -(sp) bclr.b #E1,E_BYTE(a6) ;unsupp is always an E1 exception frestore (sp)+ unlk a6 - jmp _fpfault + jmp _C_LABEL(fpfault) * * Trace exception @@ -340,7 +345,7 @@ real_trace: xdef fpsp_fmt_error fpsp_fmt_error: pea 1f - jsr _panic + jsr _C_LABEL(panic) dc.l $f27f0000 ;f-line illegal 1: .asciz "bad floating point stack frame" @@ -354,10 +359,10 @@ fpsp_fmt_error: * to execute before we do. If there is, do it now. * * - xref rei + xref _ASM_LABEL(rei) xdef fpsp_done fpsp_done: - jmp rei + jmp _ASM_LABEL(rei) * * mem_write --- write to user or supervisor address space @@ -395,7 +400,7 @@ user_write: move.l d0,-(sp) move.l a1,-(sp) move.l a0,-(sp) - jsr _copyout + jsr _C_LABEL(copyout) add.l #12,sp move.l (sp)+,d1 rts @@ -435,7 +440,7 @@ user_read: move.l d0,-(sp) move.l a1,-(sp) move.l a0,-(sp) - jsr _copyin + jsr _C_LABEL(copyin) add.l #12,sp move.l (sp)+,d1 rts diff --git a/sys/arch/m68k/include/asm.h b/sys/arch/m68k/include/asm.h index c5d656fadd9..d0035d409c2 100644 --- a/sys/arch/m68k/include/asm.h +++ b/sys/arch/m68k/include/asm.h @@ -1,7 +1,8 @@ -/* $OpenBSD: asm.h,v 1.3 1997/01/13 11:51:09 niklas Exp $ */ -/* $NetBSD: asm.h,v 1.12 1996/11/30 02:49:00 jtc Exp $ */ +/* $OpenBSD: asm.h,v 1.4 1997/07/06 07:46:22 downsj Exp $ */ +/* $NetBSD: asm.h,v 1.13 1997/04/24 22:49:39 thorpej Exp $ */ /* + * Copyright (c) 1997 Jason R. Thorpe. All rights reserved. * Copyright (c) 1994 Allen Briggs * All rights reserved. * @@ -46,10 +47,11 @@ #define _ASM_H_ #ifdef __STDC__ -#define _C_LABEL(name) _ ## name +#define _C_LABEL(name) _ ## name #else -#define _C_LABEL(name) _/**/name -#endif +#define _C_LABEL(name) _/**/name +#endif /* __STDC__ */ + #define _ASM_LABEL(name) name #ifndef _KERNEL @@ -69,6 +71,9 @@ #define ENTRY(name) _ENTRY(_C_LABEL(name)) _PROF_PROLOG #define ASENTRY(name) _ENTRY(_ASM_LABEL(name)) _PROF_PROLOG +#define ENTRY_NOPROFILE(name) _ENTRY(_C_LABEL(name)) +#define ASENTRY_NOPROFILE(name) _ENTRY(_ASM_LABEL(name)) + /* * The m68k ALTENTRY macro is very different than the traditional * implementation used by other OpenBSD ports. Usually ALTENTRY @@ -88,6 +93,62 @@ #define ALTENTRY(name, rname) _ENTRY(_C_LABEL(name)) #endif -#define RCSID(x) .text; .asciz x +#define RCSID(x) .text ; \ + .asciz x ; \ + .even + +/* + * Global variables of whatever sort. + */ +#define GLOBAL(x) \ + .globl _C_LABEL(x) ; \ + _C_LABEL(x): + +#define ASGLOBAL(x) \ + .globl _ASM_LABEL(x) ; \ + _ASM_LABEL(x): + +/* + * ...and local variables. + */ +#define LOCAL(x) \ + _C_LABEL(x): + +#define ASLOCAL(x) \ + _ASM_LABEL(x): + +/* + * Items in the BSS segment. + */ +#define BSS(name, size) \ + .comm _C_LABEL(name),size + +#define ASBSS(name, size) \ + .comm _ASM_LABEL(name),size + +#ifdef _KERNEL +/* + * Shorthand for calling panic(). + * Note the side-effect: it uses up the 9: label, so be careful! + */ +#define PANIC(x) \ + pea 9f ; \ + jbsr _C_LABEL(panic) ; \ + 9: .asciz x ; \ + .even + +/* + * Shorthand for defining vectors for the vector table. + */ +#define VECTOR(x) \ + .long _C_LABEL(x) + +#define ASVECTOR(x) \ + .long _ASM_LABEL(x) + +#define VECTOR_UNUSED \ + .long 0 + +#endif /* _KERNEL */ #endif /* _ASM_H_ */ diff --git a/sys/arch/m68k/include/cacheops.h b/sys/arch/m68k/include/cacheops.h new file mode 100644 index 00000000000..0e4cdc4e1a9 --- /dev/null +++ b/sys/arch/m68k/include/cacheops.h @@ -0,0 +1,171 @@ +/* $OpenBSD: cacheops.h,v 1.1 1997/07/06 07:46:23 downsj Exp $ */ +/* $NetBSD: cacheops.h,v 1.1 1997/06/02 20:26:37 leo Exp $ */ + +/*- + * Copyright (c) 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Leo Weppelman + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if notyet /* XXX */ +#include <machine/cpuconf.h> +#endif + +#include <m68k/cacheops_20.h> +#include <m68k/cacheops_30.h> +#include <m68k/cacheops_40.h> +#include <m68k/cacheops_60.h> + +#if defined(M68020) && !(defined(M68030)||defined(M68040)||defined(M68060)) + +#define TBIA() TBIA_20() +#define TBIS(va) TBIS_20((va)) +#define TBIAS() TBIAS_20() +#define TBIAU() TBIAU_20() +#define ICIA() ICIA_20() +#define ICPA() ICPA_20() +#define DCIA() DCIA_20() +#define DCIS() DCIS_20() +#define DCIU() DCIU_20() +#define DCIAS() DCIAS_20() +#define PCIA() PCIA_20() + +#elif defined(M68030) && !(defined(M68020)||defined(M68040)||defined(M68060)) + +#define TBIS(va) TBIS_30((va)) +#define TBIAS() TBIAS_30() +#define TBIAU() TBIAU_30() +#define ICIA() ICIA_30() +#define ICPA() ICPA_30() +#define DCIA() DCIA_30() +#define DCIS() DCIS_30() +#define DCIU() DCIU_30() +#define DCIAS() DCIAS_30() +#define PCIA() PCIA_30() + +#elif defined(M68040) && !(defined(M68020)||defined(M68030)||defined(M68060)) + +#define TBIA() TBIA_40() +#define TBIS(va) TBIS_40((va)) +#define TBIAS() TBIAS_40() +#define TBIAU() TBIAU_40() +#define ICIA() ICIA_40() +#define ICPA() ICPA_40() +#define DCIA() DCIA_40() +#define DCIS() DCIS_40() +#define DCIU() DCIU_40() +#define DCIAS(va) DCIAS_40((va)) +#define PCIA() PCIA_40() +#define ICPL(va) ICPL_40((va)) +#define ICPP(va) ICPP_40((va)) +#define DCPL(va) DCPL_40((va)) +#define DCPP(va) DCPP_40((va)) +#define DCPA() DCPA_40() +#define DCFL(va) DCFL_40((va)) +#define DCFP(va) DCFP_40((va)) + +#elif defined(M68060) && !(defined(M68020)||defined(M68030)||defined(M68040)) + +#define TBIA() TBIA_60() +#define TBIS(va) TBIS_60((va)) +#define TBIAS() TBIAS_60() +#define TBIAU() TBIAU_60() +#define ICIA() ICIA_60() +#define ICPA() ICPA_60() +#define DCIA() DCIA_60() +#define DCIS() DCIS_60() +#define DCIU() DCIU_60() +#define DCIAS(va) DCIAS_60((va)) +#define PCIA() PCIA_60() +#define ICPL(va) ICPL_60((va)) +#define ICPP(va) ICPP_60((va)) +#define DCPL(va) DCPL_60((va)) +#define DCPP(va) DCPP_60((va)) +#define DCPA() DCPA_60() +#define DCFL(va) DCFL_60((va)) +#define DCFP(va) DCFP_60((va)) + +#else /* Multi-CPU config */ + +/* XXX: From cpuconf.h? */ +#ifndef _MULTI_CPU +#define _MULTI_CPU +#endif + +void _TBIA __P((void)); +void _TBIS __P((vm_offset_t)); +void _TBIAS __P((void)); +void _TBIAU __P((void)); +void _ICIA __P((void)); +void _ICPA __P((void)); +void _DCIA __P((void)); +void _DCIS __P((void)); +void _DCIU __P((void)); +void _DCIAS __P((vm_offset_t)); + +#define TBIA() _TBIA() +#define TBIS(va) _TBIS((va)) +#define TBIAS() _TBIAS() +#define TBIAU() _TBIAU() +#define ICIA() _ICIA() +#define ICPA() _ICPA() +#define DCIA() _DCIA() +#define DCIS() _DCIS() +#define DCIU() _DCIU() +#define DCIAS(va) _DCIAS((va)) + +#if defined(M68040)||defined(M68060) + +void _PCIA __P((void)); +void _DCFA __P((void)); +void _ICPL __P((vm_offset_t)); +void _ICPP __P((vm_offset_t)); +void _DCPL __P((vm_offset_t)); +void _DCPP __P((vm_offset_t)); +void _DCPA __P((void)); +void _DCFL __P((vm_offset_t)); +void _DCFP __P((vm_offset_t)); + +#define PCIA() _PCIA() +#define DCFA() _DCFA() +#define ICPL(va) _ICPL((va)) +#define ICPP(va) _ICPP((va)) +#define DCPL(va) _DCPL((va)) +#define DCPP(va) _DCPP((va)) +#define DCPA() _DCPA() +#define DCFL(va) _DCFL((va)) +#define DCFP(va) _DCFP((va)) + +#endif /* defined(M68040)||defined(M68060) */ + +#endif diff --git a/sys/arch/m68k/include/cacheops_20.h b/sys/arch/m68k/include/cacheops_20.h new file mode 100644 index 00000000000..5dc67cd4e22 --- /dev/null +++ b/sys/arch/m68k/include/cacheops_20.h @@ -0,0 +1,116 @@ +/* $OpenBSD: cacheops_20.h,v 1.1 1997/07/06 07:46:23 downsj Exp $ */ +/* $NetBSD: cacheops_20.h,v 1.1 1997/06/02 20:26:39 leo Exp $ */ + +/*- + * Copyright (c) 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Leo Weppelman + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Invalidate entire TLB. + */ +void TBIA_20 __P((void)); +extern inline void +TBIA_20() +{ + __asm __volatile (" pflusha"); +} + +/* + * Invalidate any TLB entry for given VA (TB Invalidate Single) + */ +void TBIS_20 __P((void *)); +extern inline void +TBIS_20(va) + void *va; +{ + + __asm __volatile (" pflushs #0,#0,%0@" : : "a" (va) ); +} + +/* + * Invalidate supervisor side of TLB + */ +void TBIAS_20 __P((void)); +extern inline void +TBIAS_20() +{ + __asm __volatile (" pflushs #4,#4"); +} + +/* + * Invalidate user side of TLB + */ +void TBIAU_20 __P((void)); +extern inline void +TBIAU_20() +{ + __asm __volatile (" pflushs #0,#4;"); +} + +/* + * Invalidate instruction cache + */ +void ICIA_20 __P((void)); +extern inline void +ICIA_20() +{ + __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); +} + +void ICPA_20 __P((void)); +extern inline void +ICPA_20() +{ + __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); +} + +/* + * Invalidate data cache. + * NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing + * problems with DC_WA. The only cases we have to worry about are context + * switch and TLB changes, both of which are handled "in-line" in resume + * and TBI*. + */ +#define DCIA_20() +#define DCIS_20() +#define DCIU_20() +#define DCIAS_20() + +void PCIA_20 __P((void)); +extern inline void +PCIA_20() +{ + __asm __volatile (" movc %0,cacr;" : : "d" (DC_CLEAR)); +} diff --git a/sys/arch/m68k/include/cacheops_30.h b/sys/arch/m68k/include/cacheops_30.h new file mode 100644 index 00000000000..6a9f782361d --- /dev/null +++ b/sys/arch/m68k/include/cacheops_30.h @@ -0,0 +1,122 @@ +/* $OpenBSD: cacheops_30.h,v 1.1 1997/07/06 07:46:24 downsj Exp $ */ +/* $NetBSD: cacheops_30.h,v 1.1 1997/06/02 20:26:40 leo Exp $ */ + +/*- + * Copyright (c) 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Leo Weppelman + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Invalidate entire TLB. + */ +void TBIA_30 __P((void)); +extern inline void +TBIA_30() +{ + int tmp = DC_CLEAR; + + __asm __volatile (" pflusha;" + " movc %0,cacr" : : "d" (tmp)); +} + +/* + * Invalidate any TLB entry for given VA (TB Invalidate Single) + */ +void TBIS_30 __P((vm_offset_t)); +extern inline void +TBIS_30(va) + vm_offset_t va; +{ + __asm __volatile (" pflush #0,#0,%0@;" + " movc %1,cacr" : : "a" (va), "d" (DC_CLEAR)); +} + +/* + * Invalidate supervisor side of TLB + */ +void TBIAS_30 __P((void)); +extern inline void +TBIAS_30() +{ + __asm __volatile (" pflush #4,#4;" + " movc %0,cacr;" :: "d" (DC_CLEAR)); +} + +/* + * Invalidate user side of TLB + */ +void TBIAU_30 __P((void)); +extern inline void +TBIAU_30() +{ + __asm __volatile (" pflush #0,#4;" + " movc %0,cacr;" :: "d" (DC_CLEAR)); +} + +/* + * Invalidate instruction cache + */ +void ICIA_30 __P((void)); +extern inline void +ICIA_30() +{ + __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); +} + +void ICPA_30 __P((void)); +extern inline void +ICPA_30() +{ + __asm __volatile (" movc %0,cacr;" : : "d" (IC_CLEAR)); +} + +/* + * Invalidate data cache. + * NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing + * problems with DC_WA. The only cases we have to worry about are context + * switch and TLB changes, both of which are handled "in-line" in resume + * and TBI*. + */ +#define DCIA_30() +#define DCIS_30() +#define DCIU_30() +#define DCIAS_30(va) + + +void PCIA_30 __P((void)); +extern inline void +PCIA_30() +{ + __asm __volatile (" movc %0,cacr;" : : "d" (DC_CLEAR)); +} diff --git a/sys/arch/m68k/include/cacheops_40.h b/sys/arch/m68k/include/cacheops_40.h new file mode 100644 index 00000000000..845c9550161 --- /dev/null +++ b/sys/arch/m68k/include/cacheops_40.h @@ -0,0 +1,232 @@ +/* $OpenBSD: cacheops_40.h,v 1.1 1997/07/06 07:46:24 downsj Exp $ */ +/* $NetBSD: cacheops_40.h,v 1.1 1997/06/02 20:26:41 leo Exp $ */ + +/*- + * Copyright (c) 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Leo Weppelman + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Invalidate entire TLB. + */ +void TBIA_40 __P((void)); +extern inline void +TBIA_40() +{ + __asm __volatile (" .word 0xf518" ); /* pflusha */ +} + +/* + * Invalidate any TLB entry for given VA (TB Invalidate Single) + */ +void TBIS_40 __P((vm_offset_t)); +extern inline void +TBIS_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + int tmp; + + __asm __volatile (" movc %1, dfc;" /* select supervisor */ + " .word 0xf508;" /* pflush a0@ */ + " moveq %3, %1;" /* select user */ + " movc %1, dfc;" + " .word 0xf508;" : "=d" (tmp) : + "0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD)); +} + +/* + * Invalidate supervisor side of TLB + */ +void TBIAS_40 __P((void)); +extern inline void +TBIAS_40() +{ + /* + * Cannot specify supervisor/user on pflusha, so we flush all + */ + __asm __volatile (" .word 0xf518;"); +} + +/* + * Invalidate user side of TLB + */ +void TBIAU_40 __P((void)); +extern inline void +TBIAU_40() +{ + /* + * Cannot specify supervisor/user on pflusha, so we flush all + */ + __asm __volatile (" .word 0xf518;"); +} + +/* + * Invalidate instruction cache + */ +void ICIA_40 __P((void)); +extern inline void +ICIA_40() +{ + __asm __volatile (" .word 0xf498;"); /* cinva ic */ +} + +void ICPA_40 __P((void)); +extern inline void +ICPA_40() +{ + __asm __volatile (" .word 0xf498;"); /* cinva ic */ +} + +/* + * Invalidate data cache. + */ +void DCIA_40 __P((void)); +extern inline void +DCIA_40() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCIS_40 __P((void)); +extern inline void +DCIS_40() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCIU_40 __P((void)); +extern inline void +DCIU_40() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCIAS_40 __P((vm_offset_t)); +extern inline void +DCIAS_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */ +} + +void PCIA_40 __P((void)); +extern inline void +PCIA_40() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCFA_40 __P((void)); +extern inline void +DCFA_40() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +/* invalidate instruction physical cache line */ +void ICPL_40 __P((vm_offset_t)); +extern inline void +ICPL_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf488;" : : "a" (r_va)); /* cinvl ic,a0@ */ +} + +/* invalidate instruction physical cache page */ +void ICPP_40 __P((vm_offset_t)); +extern inline void +ICPP_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf490;" : : "a" (r_va)); /* cinvp ic,a0@ */ +} + +/* invalidate data physical cache line */ +void DCPL_40 __P((vm_offset_t)); +extern inline void +DCPL_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf448;" : : "a" (r_va)); /* cinvl dc,a0@ */ +} + +/* invalidate data physical cache page */ +void DCPP_40 __P((vm_offset_t)); +extern inline void +DCPP_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf450;" : : "a" (r_va)); /* cinvp dc,a0@ */ +} + +/* invalidate data physical all */ +void DCPA_40 __P((void)); +extern inline void +DCPA_40() +{ + __asm __volatile (" .word 0xf458;"); /* cinva dc */ +} + +/* data cache flush line */ +void DCFL_40 __P((vm_offset_t)); +extern inline void +DCFL_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */ +} + +/* data cache flush page */ +void DCFP_40 __P((vm_offset_t)); +extern inline void +DCFP_40(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf470;" : : "a" (r_va)); /* cpushp dc,a0@ */ +} diff --git a/sys/arch/m68k/include/cacheops_60.h b/sys/arch/m68k/include/cacheops_60.h new file mode 100644 index 00000000000..1c7f8c5983f --- /dev/null +++ b/sys/arch/m68k/include/cacheops_60.h @@ -0,0 +1,248 @@ +/* $OpenBSD: cacheops_60.h,v 1.1 1997/07/06 07:46:25 downsj Exp $ */ +/* $NetBSD: cacheops_60.h,v 1.1 1997/06/02 20:26:43 leo Exp $ */ + +/*- + * Copyright (c) 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Leo Weppelman + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Invalidate entire TLB. + */ +void TBIA_60 __P((void)); +extern inline void +TBIA_60() +{ + __asm __volatile (" .word 0xf518" ); /* pflusha */ +} + +/* + * Invalidate any TLB entry for given VA (TB Invalidate Single) + */ +void TBIS_60 __P((vm_offset_t)); +extern inline void +TBIS_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + int tmp; + + __asm __volatile (" movc %1, dfc;" /* select supervisor */ + " .word 0xf508;" /* pflush a0@ */ + " moveq %3, %1;" /* select user */ + " movc %1, dfc;" + " .word 0xf508;" /* pflush a0@ */ + " movc cacr,%1;" + " orl %4,%1;" + " movc %1,cacr" : "=d" (tmp) : + "0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD), + "i" (IC60_CABC)); +} + +/* + * Invalidate supervisor side of TLB + */ +void TBIAS_60 __P((void)); +extern inline void +TBIAS_60() +{ + int tmp; + /* + * Cannot specify supervisor/user on pflusha, so we flush all + */ + __asm __volatile (" .word 0xf518;" + " movc cacr,%0;" + " orl %1,%0;" + " movc %0,cacr" /* clear all branch cache entries */ + : "=d" (tmp) : "i" (IC60_CABC) ); +} + +/* + * Invalidate user side of TLB + */ +void TBIAU_60 __P((void)); +extern inline void +TBIAU_60() +{ + int tmp; + /* + * Cannot specify supervisor/user on pflusha, so we flush all + */ + __asm __volatile (" .word 0xf518;" + " movc cacr,%0;" + " orl %1,%0;" + " movc %0,cacr" /* clear all branch cache entries */ + : "=d" (tmp) : "i" (IC60_CUBC) ); +} + +/* + * Invalidate instruction cache + */ +void ICIA_60 __P((void)); +extern inline void +ICIA_60() +{ + /* inva ic (also clears branch cache) */ + __asm __volatile (" .word 0xf498;"); +} + +void ICPA_60 __P((void)); +extern inline void +ICPA_60() +{ + /* inva ic (also clears branch cache) */ + __asm __volatile (" .word 0xf498;"); +} + +/* + * Invalidate data cache. + */ +void DCIA_60 __P((void)); +extern inline void +DCIA_60() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCIS_60 __P((void)); +extern inline void +DCIS_60() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCIU_60 __P((void)); +extern inline void +DCIU_60() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCIAS_60 __P((vm_offset_t)); +extern inline void +DCIAS_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */ +} + +void PCIA_60 __P((void)); +extern inline void +PCIA_60() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +void DCFA_60 __P((void)); +extern inline void +DCFA_60() +{ + __asm __volatile (" .word 0xf478;"); /* cpusha dc */ +} + +/* invalidate instruction physical cache line */ +void ICPL_60 __P((vm_offset_t)); +extern inline void +ICPL_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf488;" : : "a" (r_va)); /* cinvl ic,a0@ */ +} + +/* invalidate instruction physical cache page */ +void ICPP_60 __P((vm_offset_t)); +extern inline void +ICPP_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf490;" : : "a" (r_va)); /* cinvp ic,a0@ */ +} + +/* invalidate data physical cache line */ +void DCPL_60 __P((vm_offset_t)); +extern inline void +DCPL_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf448;" : : "a" (r_va)); /* cinvl dc,a0@ */ +} + +/* invalidate data physical cache page */ +void DCPP_60 __P((vm_offset_t)); +extern inline void +DCPP_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf450;" : : "a" (r_va)); /* cinvp dc,a0@ */ +} + +/* invalidate data physical all */ +void DCPA_60 __P((void)); +extern inline void +DCPA_60() +{ + __asm __volatile (" .word 0xf458;"); /* cinva dc */ +} + +/* data cache flush line */ +void DCFL_60 __P((vm_offset_t)); +extern inline void +DCFL_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */ +} + +/* data cache flush page */ +void DCFP_60 __P((vm_offset_t)); +extern inline void +DCFP_60(va) + vm_offset_t va; +{ + register vm_offset_t r_va __asm("a0") = va; + + __asm __volatile (" .word 0xf470;" : : "a" (r_va)); /* cpushp dc,a0@ */ +} diff --git a/sys/arch/m68k/include/db_machdep.h b/sys/arch/m68k/include/db_machdep.h index de2907190e3..fcf4b0e09dd 100644 --- a/sys/arch/m68k/include/db_machdep.h +++ b/sys/arch/m68k/include/db_machdep.h @@ -1,5 +1,5 @@ -/* $OpenBSD: db_machdep.h,v 1.4 1997/03/21 00:36:36 niklas Exp $ */ -/* $NetBSD: db_machdep.h,v 1.19 1997/02/18 22:29:58 gwr Exp $ */ +/* $OpenBSD: db_machdep.h,v 1.5 1997/07/06 07:46:25 downsj Exp $ */ +/* $NetBSD: db_machdep.h,v 1.20 1997/06/26 01:26:58 thorpej Exp $ */ /* * Mach Operating System @@ -102,4 +102,9 @@ int kdb_trap __P((int, db_regs_t *)); #endif /* _KERNEL */ +/* + * We use a.out symbols in DDB. + */ +#define DB_AOUT_SYMBOLS + #endif /* _M68K_DB_MACHDEP_H_ */ diff --git a/sys/arch/m68k/include/frame.h b/sys/arch/m68k/include/frame.h index 95d3a1ee6cd..77e6579ffda 100644 --- a/sys/arch/m68k/include/frame.h +++ b/sys/arch/m68k/include/frame.h @@ -1,5 +1,5 @@ -/* $OpenBSD: frame.h,v 1.4 1997/03/21 00:36:37 niklas Exp $ */ -/* $NetBSD: frame.h,v 1.13 1997/01/27 22:58:45 gwr Exp $ */ +/* $OpenBSD: frame.h,v 1.5 1997/07/06 07:46:25 downsj Exp $ */ +/* $NetBSD: frame.h,v 1.15 1997/05/03 12:49:05 mycroft Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -55,7 +55,7 @@ struct frame { u_int tf_pc; u_short tf_format:4, tf_vector:12; - } F_t; + } __attribute__((packed)) F_t; union F_u { struct fmt2 { u_int f_iaddr; diff --git a/sys/arch/m68k/include/param.h b/sys/arch/m68k/include/param.h new file mode 100644 index 00000000000..76823a6a876 --- /dev/null +++ b/sys/arch/m68k/include/param.h @@ -0,0 +1,147 @@ +/* $OpenBSD: param.h,v 1.1 1997/07/06 07:46:26 downsj Exp $ */ +/* $NetBSD: param.h,v 1.2 1997/06/10 18:21:23 veego Exp $ */ + +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1982, 1986, 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah $Hdr: machparam.h 1.16 92/12/20$ + * + * @(#)param.h 8.1 (Berkeley) 6/10/93 + */ +#ifndef _M68K_PARAM_H_ +#define _M68K_PARAM_H_ + +/* + * Machine independent constants for m68k + */ +#define _MACHINE_ARCH m68k +#define MACHINE_ARCH "m68k" +#define MID_MACHINE MID_M68K + +/* + * Round p (pointer or byte index) up to a correctly-aligned value for all + * data types (int, long, ...). The result is u_int and must be cast to + * any desired pointer type. + * + * ALIGNED_POINTER is a boolean macro that checks whether an address + * is valid to fetch data elements of type t from on this architecture. + * This does not reflect the optimal alignment, just the possibility + * (within reasonable limits). + * + */ +#define ALIGNBYTES (sizeof(int) - 1) +#define ALIGN(p) (((u_int)(p) + ALIGNBYTES) &~ ALIGNBYTES) +#define ALIGNED_POINTER(p,t) ((((u_long)(p)) & (sizeof(t)-1)) == 0) + +#define NBPG (1 << PGSHIFT) /* bytes/page */ +#define PGOFSET (NBPG-1) /* byte offset into page */ +#define NPTEPG (NBPG/(sizeof (pt_entry_t))) + +#define BTOPKERNBASE ((u_long)KERNBASE >> PGSHIFT) + +#define DEV_BSHIFT 9 /* log2(DEV_BSIZE) */ +#define DEV_BSIZE (1 << DEV_BSHIFT) +#define BLKDEV_IOSIZE 2048 +#define MAXPHYS (64 * 1024) /* max raw I/O transfer size */ + +#define CLSIZELOG2 0 +#define CLSIZE (1 << CLSIZELOG2) + +/* NOTE: SSIZE, SINCR and UPAGES must be multiples of CLSIZE */ +#define SSIZE 1 /* initial stack size/NBPG */ +#define SINCR 1 /* increment of stack/NBPG */ + +/* mac68k, mvme68k and x68k 3 pages of u-area */ +#ifndef UPAGES +# define UPAGES 2 /* pages of u-area */ +#endif +#define USPACE (UPAGES * NBPG) + +/* + * Constants related to network buffer management. + * MCLBYTES must be no larger than CLBYTES (the software page size), and, + * on machines that exchange pages of input or output buffers with mbuf + * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple + * of the hardware page size. + */ +#define MSIZE 128 /* size of an mbuf */ + +#ifndef MCLSHIFT +# define MCLSHIFT 11 /* convert bytes to m_buf clusters */ +#endif /* MCLSHIFT */ + +#define MCLBYTES (1 << MCLSHIFT) +#define MCLOFSET (MCLBYTES - 1) +#ifndef NMBCLUSTERS +#ifdef GATEWAY +# define NMBCLUSTERS 512 /* map size, max cluster allocation */ +#else +# define NMBCLUSTERS 256 /* map size, max cluster allocation */ +#endif +#endif + +/* pages ("clicks") to disk blocks */ +#define ctod(x) ((x) << (PGSHIFT - DEV_BSHIFT)) +#define dtoc(x) ((x) >> (PGSHIFT - DEV_BSHIFT)) + +/* pages to bytes */ +#define ctob(x) ((x) << PGSHIFT) +#define btoc(x) (((x) + PGOFSET) >> PGSHIFT) + +/* bytes to disk blocks */ +#define btodb(x) ((x) >> DEV_BSHIFT) +#define dbtob(x) ((x) << DEV_BSHIFT) + +/* + * Map a ``block device block'' to a file system block. + * This should be device dependent, and should use the bsize + * field from the disk label. + * For now though just use DEV_BSIZE. + */ +#define bdbtofsb(bn) ((bn) / (BLKDEV_IOSIZE/DEV_BSIZE)) + +/* + * Mach derived conversion macros + */ +#define m68k_round_seg(x) ((((unsigned)(x)) + SEGOFSET) & ~SEGOFSET) +#define m68k_trunc_seg(x) ((unsigned)(x) & ~SEGOFSET) +#define m68k_round_page(x) ((((unsigned)(x)) + PGOFSET) & ~PGOFSET) +#define m68k_trunc_page(x) ((unsigned)(x) & ~PGOFSET) +#define m68k_btop(x) ((unsigned)(x) >> PGSHIFT) +#define m68k_ptob(x) ((unsigned)(x) << PGSHIFT) + +#endif /* !_M68K_PARAM_H_ */ diff --git a/sys/arch/m68k/m68k/cacheops.c b/sys/arch/m68k/m68k/cacheops.c new file mode 100644 index 00000000000..9392f33b3ca --- /dev/null +++ b/sys/arch/m68k/m68k/cacheops.c @@ -0,0 +1,499 @@ +/* $OpenBSD: cacheops.c,v 1.1 1997/07/06 07:46:27 downsj Exp $ */ +/* $NetBSD: cacheops.c,v 1.1 1997/06/02 20:26:57 leo Exp $ */ + +/*- + * Copyright (c) 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Leo Weppelman + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +#include <sys/types.h> +#include <m68k/cpu.h> +#include <m68k/cacheops.h> +#include <machine/cpu.h> + +#if defined(_MULTI_CPU) + +void _TBIA() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + TBIA_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + TBIA_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + TBIA_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + TBIA_60(); + break; +#endif + } +} + +void _TBIAS() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + TBIAS_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + TBIAS_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + TBIAS_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + TBIAS_60(); + break; +#endif + } +} + +void _TBIAU() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + TBIAU_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + TBIAU_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + TBIAU_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + TBIAU_60(); + break; +#endif + } +} + +void _ICIA() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + ICIA_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + ICIA_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + ICIA_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + ICIA_60(); + break; +#endif + } +} + +void _ICPA() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + ICPA_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + ICPA_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + ICPA_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + ICPA_60(); + break; +#endif + } +} + +void _DCIA() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + DCIA_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + DCIA_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + DCIA_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCIA_60(); + break; +#endif + } +} + +void _DCIS() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + DCIS_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + DCIS_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + DCIS_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCIS_60(); + break; +#endif + } +} + +void _DCIU() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + DCIU_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + DCIU_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + DCIU_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCIU_60(); + break; +#endif + } +} + +void _PCIA() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + PCIA_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + PCIA_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + PCIA_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + PCIA_60(); + break; +#endif + } +} + +void _DCFA() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + DCFA_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + DCFA_30(); + break; +#endif +#ifdef M68040 + case CPU_68040: + DCFA_40(); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCFA_60(); + break; +#endif + } +} + +void _TBIS(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + TBIS_20(va); + break; +#endif +#ifdef M68030 + case CPU_68030: + TBIS_30(va); + break; +#endif +#ifdef M68040 + case CPU_68040: + TBIS_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + TBIS_60(va); + break; +#endif + } +} + +void _DCIAS(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + DCIAS_20(va); + break; +#endif +#ifdef M68030 + case CPU_68030: + DCIAS_30(va); + break; +#endif +#ifdef M68040 + case CPU_68040: + DCIAS_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCIAS_60(va); + break; +#endif + } +} + +void _DCPA() +{ + switch (cputype) { + default: +#ifdef M68020 + case CPU_68020: + DCPA_20(); + break; +#endif +#ifdef M68030 + case CPU_68030: + DCPA_30(); + break; +#endif + } +} + +void _ICPL(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68040 + case CPU_68040: + ICPL_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + ICPL_60(va); + break; +#endif + } +} + +void _ICPP(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68040 + case CPU_68040: + ICPP_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + ICPP_60(va); + break; +#endif + } +} + +void _DCPL(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68040 + case CPU_68040: + DCPL_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCPL_60(va); + break; +#endif + } +} + +void _DCPP(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68040 + case CPU_68040: + DCPP_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCPP_60(va); + break; +#endif + } +} + +void _DCFL(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68040 + case CPU_68040: + DCFL_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCFL_60(va); + break; +#endif + } +} + +void _DCFP(va) + vm_offset_t va; +{ + switch (cputype) { + default: +#ifdef M68040 + case CPU_68040: + DCFP_40(va); + break; +#endif +#ifdef M68060 + case CPU_68060: + DCFP_60(va); + break; +#endif + } +} + +#endif /* defined(_TBIA) */ diff --git a/sys/arch/m68k/m68k/copy.s b/sys/arch/m68k/m68k/copy.s index 4bfffe7988a..f26c88b931a 100644 --- a/sys/arch/m68k/m68k/copy.s +++ b/sys/arch/m68k/m68k/copy.s @@ -1,5 +1,5 @@ -/* $OpenBSD: copy.s,v 1.6 1997/03/26 08:23:54 downsj Exp $ */ -/* $NetBSD: copy.s,v 1.26 1997/03/17 19:46:36 gwr Exp $ */ +/* $OpenBSD: copy.s,v 1.7 1997/07/06 07:46:27 downsj Exp $ */ +/* $NetBSD: copy.s,v 1.28 1997/05/21 03:51:04 jeremy Exp $ */ /*- * Copyright (c) 1994, 1995 Charles Hannum. @@ -63,26 +63,16 @@ * The diagnostics: CHECK_SFC, CHECK_DFC * will verify that the sfc/dfc register values are correct. */ -Lbadfc_msg: - .asciz "copy.s: bad sfc or dfc" - .even -badfc: - pea Lbadfc_msg - jsr _panic - bra badfc -#define CHECK_SFC movec sfc,d0; subql #FC_USERD,d0; bne badfc -#define CHECK_DFC movec dfc,d0; subql #FC_USERD,d0; bne badfc +Lbadfc: + PANIC("copy.s: bad sfc or dfc") + bra Lbadfc +#define CHECK_SFC movec sfc,d0; subql #FC_USERD,d0; bne Lbadfc +#define CHECK_DFC movec dfc,d0; subql #FC_USERD,d0; bne Lbadfc #else /* DIAGNOSTIC */ #define CHECK_SFC #define CHECK_DFC #endif /* DIAGNOSTIC */ -#ifdef MAPPEDCOPY - .globl _mappedcopyin - .globl _mappedcopyout - .globl _mappedcopysize -#endif - /* * copyin(caddr_t from, caddr_t to, size_t len); * Copy len bytes from the user's address space. @@ -99,11 +89,11 @@ ENTRY(copyin) movl sp@(12),d0 | check count beq Lciret | == 0, don't do anything #ifdef MAPPEDCOPY - cmpl _mappedcopysize,d0 | size >= mappedcopysize - bcc _mappedcopyin | yes, go do it the new way + cmpl _C_LABEL(mappedcopysize),d0 | size >= mappedcopysize + bcc _C_LABEL(mappedcopyin) | yes, go do it the new way #endif movl d2,sp@- | save scratch register - movl _curpcb,a0 | set fault handler + movl _C_LABEL(curpcb),a0 | set fault handler movl #Lcifault,a0@(PCB_ONFAULT) movl sp@(8),a0 | src address movl sp@(12),a1 | dest address @@ -140,7 +130,7 @@ Lcibloop: bcc Lcibloop clrl d0 | no error Lcidone: - movl _curpcb,a0 | clear fault handler + movl _C_LABEL(curpcb),a0 | clear fault handler clrl a0@(PCB_ONFAULT) movl sp@+,d2 | restore scratch register Lciret: @@ -165,11 +155,11 @@ ENTRY(copyout) movl sp@(12),d0 | check count beq Lcoret | == 0, don't do anything #ifdef MAPPEDCOPY - cmpl _mappedcopysize,d0 | size >= mappedcopysize - bcc _mappedcopyout | yes, go do it the new way + cmpl _C_LABEL(mappedcopysize),d0 | size >= mappedcopysize + bcc _C_LABEL(mappedcopyout) | yes, go do it the new way #endif movl d2,sp@- | save scratch register - movl _curpcb,a0 | set fault handler + movl _C_LABEL(curpcb),a0 | set fault handler movl #Lcofault,a0@(PCB_ONFAULT) movl sp@(8),a0 | src address movl sp@(12),a1 | dest address @@ -206,7 +196,7 @@ Lcobloop: bcc Lcobloop clrl d0 | no error Lcodone: - movl _curpcb,a0 | clear fault handler + movl _C_LABEL(curpcb),a0 | clear fault handler clrl a0@(PCB_ONFAULT) movl sp@+,d2 | restore scratch register Lcoret: @@ -253,7 +243,7 @@ Lcsret: */ ENTRY(copyinstr) CHECK_SFC - movl _curpcb,a0 | set fault handler + movl _C_LABEL(curpcb),a0 | set fault handler movl #Lcisfault,a0@(PCB_ONFAULT) movl sp@(4),a0 | a0 = fromaddr movl sp@(8),a1 | a1 = toaddr @@ -276,7 +266,7 @@ Lcisdone: movl sp@(16),a1 | store at return location movl a0,a1@ Lcisexit: - movl _curpcb,a0 | clear fault handler + movl _C_LABEL(curpcb),a0 | clear fault handler clrl a0@(PCB_ONFAULT) rts Lcisfault: @@ -292,7 +282,7 @@ Lcisfault: */ ENTRY(copyoutstr) CHECK_DFC - movl _curpcb,a0 | set fault handler + movl _C_LABEL(curpcb),a0 | set fault handler movl #Lcosfault,a0@(PCB_ONFAULT) movl sp@(4),a0 | a0 = fromaddr movl sp@(8),a1 | a1 = toaddr @@ -315,7 +305,7 @@ Lcosdone: movl sp@(16),a1 | store at return location movl a0,a1@ Lcosexit: - movl _curpcb,a0 | clear fault handler + movl _C_LABEL(curpcb),a0 | clear fault handler clrl a0@(PCB_ONFAULT) rts Lcosfault: @@ -329,7 +319,7 @@ Lcosfault: ENTRY(fuword) CHECK_SFC movl sp@(4),a0 | address to read - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #Lferr,a1@(PCB_ONFAULT) movsl a0@,d0 | do read from user space bra Lfdone @@ -341,7 +331,7 @@ ENTRY(fuword) ENTRY(fusword) CHECK_SFC movl sp@(4),a0 | address to read - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #Lferr,a1@(PCB_ONFAULT) moveq #0,d0 movsw a0@,d0 | do read from user space @@ -355,7 +345,7 @@ ENTRY(fusword) ENTRY(fuswintr) CHECK_SFC movl sp@(4),a0 | address to read - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #_fubail,a1@(PCB_ONFAULT) moveq #0,d0 movsw a0@,d0 | do read from user space @@ -368,7 +358,7 @@ ENTRY(fuswintr) ENTRY(fubyte) CHECK_SFC movl sp@(4),a0 | address to read - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #Lferr,a1@(PCB_ONFAULT) moveq #0,d0 movsb a0@,d0 | do read from user space @@ -397,21 +387,21 @@ ENTRY(suword) CHECK_DFC movl sp@(4),a0 | address to write movl sp@(8),d0 | value to put there - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #Lserr,a1@(PCB_ONFAULT) movsl d0,a0@ | do write to user space moveq #0,d0 | indicate no fault bra Lsdone /* - * fusword(caddr_t uaddr); - * Fetch a short from the user's address space. + * susword(caddr_t uaddr, short x); + * Store a short in the user's address space. */ ENTRY(susword) CHECK_DFC movl sp@(4),a0 | address to write movw sp@(10),d0 | value to put there - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #Lserr,a1@(PCB_ONFAULT) movsw d0,a0@ | do write to user space moveq #0,d0 | indicate no fault @@ -426,7 +416,7 @@ ENTRY(suswintr) CHECK_DFC movl sp@(4),a0 | address to write movw sp@(10),d0 | value to put there - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #_subail,a1@(PCB_ONFAULT) movsw d0,a0@ | do write to user space moveq #0,d0 | indicate no fault @@ -440,7 +430,7 @@ ENTRY(subyte) CHECK_DFC movl sp@(4),a0 | address to write movb sp@(11),d0 | value to put there - movl _curpcb,a1 | set fault handler + movl _C_LABEL(curpcb),a1 | set fault handler movl #Lserr,a1@(PCB_ONFAULT) movsb d0,a0@ | do write to user space moveq #0,d0 | indicate no fault diff --git a/sys/arch/m68k/m68k/copypage.s b/sys/arch/m68k/m68k/copypage.s index 5483bf4981f..d1aedf9a207 100644 --- a/sys/arch/m68k/m68k/copypage.s +++ b/sys/arch/m68k/m68k/copypage.s @@ -1,12 +1,13 @@ -/* $OpenBSD: copypage.s,v 1.1 1997/03/26 08:23:54 downsj Exp $ */ -/* $NetBSD: copypage.s,v 1.1 1997/03/17 19:44:35 gwr Exp $ */ +/* $OpenBSD: copypage.s,v 1.2 1997/07/06 07:46:28 downsj Exp $ */ +/* $NetBSD: copypage.s,v 1.4 1997/05/30 01:34:49 jtc Exp $ */ /*- * Copyright (c) 1997 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation - * by J.T. Conklin + * by J.T. Conklin <jtc@netbsd.org> and + * by Hiroshi Horitomo <horimoto@cs-aoi.cs.sist.ac.jp> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -57,7 +58,7 @@ ENTRY(copypage040) movl sp@(4),a0 | source address movl sp@(8),a1 | destiniation address - movl #NBPG/32-1,d0 | number of 32 byte chunks - 1 + movw #NBPG/32-1,d0 | number of 32 byte chunks - 1 Lm16loop: .long 0xf6209000 | move16 a0@+,a1@+ .long 0xf6209000 | move16 a0@+,a1@+ @@ -73,7 +74,7 @@ Lm16loop: ENTRY(copypage) movl sp@(4),a0 | source address movl sp@(8),a1 | destiniation address - movl #NBPG/32-1,d0 | number of 32 byte chunks - 1 + movw #NBPG/32-1,d0 | number of 32 byte chunks - 1 Lmlloop: movl a0@+,a1@+ movl a0@+,a1@+ @@ -93,16 +94,26 @@ Lmlloop: */ ENTRY(zeropage) movl sp@(4),a0 | dest address - movl #NBPG/32-1,d0 | number of 32 byte chunks - 1 - movq #0,d1 + movql #NBPG/256-1,d0 | number of 256 byte chunks - 1 + movml d2-d7,sp@- + movql #0,d1 + movql #0,d2 + movql #0,d3 + movql #0,d4 + movql #0,d5 + movql #0,d6 + movql #0,d7 + movl d1,a1 + lea a0@(NBPG),a0 Lzloop: - movl d1,a0@+ - movl d1,a0@+ - movl d1,a0@+ - movl d1,a0@+ - movl d1,a0@+ - movl d1,a0@+ - movl d1,a0@+ - movl d1,a0@+ + movml d1-d7/a1,a0@- + movml d1-d7/a1,a0@- + movml d1-d7/a1,a0@- + movml d1-d7/a1,a0@- + movml d1-d7/a1,a0@- + movml d1-d7/a1,a0@- + movml d1-d7/a1,a0@- + movml d1-d7/a1,a0@- dbf d0,Lzloop + movml sp@+,d2-d7 rts diff --git a/sys/arch/m68k/m68k/m68k_machdep.c b/sys/arch/m68k/m68k/m68k_machdep.c new file mode 100644 index 00000000000..4b0c39194b8 --- /dev/null +++ b/sys/arch/m68k/m68k/m68k_machdep.c @@ -0,0 +1,44 @@ +/* $OpenBSD: m68k_machdep.c,v 1.1 1997/07/06 07:46:28 downsj Exp $ */ +/* $NetBSD: m68k_machdep.c,v 1.3 1997/06/12 09:57:04 veego Exp $ */ + +/*- + * Copyright (c) 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Bernd Ernesti. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/param.h> + +/* the following is used externally (sysctl_hw) */ +char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ + diff --git a/sys/arch/m68k/m68k/proc_subr.s b/sys/arch/m68k/m68k/proc_subr.s new file mode 100644 index 00000000000..254b453dbe7 --- /dev/null +++ b/sys/arch/m68k/m68k/proc_subr.s @@ -0,0 +1,133 @@ +/* $OpenBSD: proc_subr.s,v 1.1 1997/07/06 07:46:28 downsj Exp $ */ +/* $NetBSD: proc_subr.s,v 1.2 1997/04/25 02:22:01 thorpej Exp $ */ + +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1980, 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah $Hdr: locore.s 1.66 92/12/22$ + * + * @(#)locore.s 8.6 (Berkeley) 5/27/94 + */ + +/* + * Assembly routines related to process manipulation. + */ + +/* + * NOTICE: This is not a standalone file. To use it, #include it in + * your port's locore.s, like so: + * + * #include <m68k/m68k/proc_subr.s> + */ + +/* + * The following primitives manipulate the run queues. _whichqs tells which + * of the 32 queues _qs have processes in them. Setrunqueue puts processes + * into queues, remrunqueue removes them from queues. The running process is + * on no queue, other processes are on a queue related to p->p_priority, + * divided by 4 actually to shrink the 0-127 range of priorities into the 32 + * available queues. + */ + +/* + * Setrunqueue(p) + * + * Call should be made at spl6(), and p->p_stat should be SRUN + */ +ENTRY(setrunqueue) + movl sp@(4),a0 +#ifdef DIAGNOSTIC + tstl a0@(P_BACK) + jne Lset1 + tstl a0@(P_WCHAN) + jne Lset1 + cmpb #SRUN,a0@(P_STAT) + jne Lset1 +#endif + clrl d0 + movb a0@(P_PRIORITY),d0 + lsrb #2,d0 + movl _C_LABEL(whichqs),d1 + bset d0,d1 + movl d1,_C_LABEL(whichqs) + lslb #3,d0 + addl #_C_LABEL(qs),d0 + movl d0,a0@(P_FORW) + movl d0,a1 + movl a1@(P_BACK),a0@(P_BACK) + movl a0,a1@(P_BACK) + movl a0@(P_BACK),a1 + movl a0,a1@(P_FORW) + rts +#ifdef DIAGNOSTIC +Lset1: + PANIC("setrunqueue") +#endif + +/* + * remrunqueue(p) + * + * Call should be made at spl6(). + */ +ENTRY(remrunqueue) + movl sp@(4),a0 + movb a0@(P_PRIORITY),d0 +#ifdef DIAGNOSTIC + lsrb #2,d0 + movl _C_LABEL(whichqs),d1 + btst d0,d1 + jeq Lrem2 +#endif + movl a0@(P_BACK),a1 + clrl a0@(P_BACK) + movl a0@(P_FORW),a0 + movl a0,a1@(P_FORW) + movl a1,a0@(P_BACK) + cmpal a0,a1 + jne Lrem1 +#ifndef DIAGNOSTIC + lsrb #2,d0 + movl _C_LABEL(whichqs),d1 +#endif + bclr d0,d1 + movl d1,_C_LABEL(whichqs) +Lrem1: + rts +#ifdef DIAGNOSTIC +Lrem2: + PANIC("remrunqueue") +#endif diff --git a/sys/arch/m68k/m68k/random.s b/sys/arch/m68k/m68k/random.s index 5de3d8c21c8..aafc3fd40a2 100644 --- a/sys/arch/m68k/m68k/random.s +++ b/sys/arch/m68k/m68k/random.s @@ -1,5 +1,5 @@ -/* $OpenBSD: random.s,v 1.3 1996/08/10 21:41:08 deraadt Exp $ */ -/* $NetBSD: random.s,v 1.5 1995/01/15 22:32:35 mycroft Exp $ */ +/* $OpenBSD: random.s,v 1.4 1997/07/06 07:46:29 downsj Exp $ */ +/* $NetBSD: random.s,v 1.6 1997/04/25 02:22:02 thorpej Exp $ */ /* * Copyright (c) 1990,1993 The Regents of the University of California. @@ -44,18 +44,17 @@ #include <machine/asm.h> .data - .globl __randseed -__randseed: +GLOBAL(_randseed) .long 1 - .text + ENTRY(random) movl #16807, d0 - mulsl __randseed, d1:d0 + mulsl _C_LABEL(_randseed), d1:d0 lsll #1, d0 roxll #2, d1 addl d1, d0 moveql #1, d1 addxl d1, d0 lsrl #1, d0 - movl d0, __randseed + movl d0, _C_LABEL(_randseed) rts diff --git a/sys/arch/m68k/m68k/sig_machdep.c b/sys/arch/m68k/m68k/sig_machdep.c index 2e5dc68a2fd..68620bde6a6 100644 --- a/sys/arch/m68k/m68k/sig_machdep.c +++ b/sys/arch/m68k/m68k/sig_machdep.c @@ -1,5 +1,5 @@ -/* $OpenBSD: sig_machdep.c,v 1.1 1997/03/26 08:23:55 downsj Exp $ */ -/* $NetBSD: sig_machdep.c,v 1.2 1997/03/17 19:03:11 gwr Exp $ */ +/* $OpenBSD: sig_machdep.c,v 1.2 1997/07/06 07:46:29 downsj Exp $ */ +/* $NetBSD: sig_machdep.c,v 1.3 1997/04/30 23:28:03 gwr Exp $ */ /* * Copyright (c) 1997 Theo de Raadt @@ -168,7 +168,7 @@ sendsig(catcher, sig, mask, code, type, val) (void)grow(p, (unsigned)fp); #ifdef DEBUG if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid) - printf("sendsig(%d): sig %d ssp %x usp %x scp %x ft %d\n", + printf("sendsig(%d): sig %d ssp %p usp %p scp %p ft %d\n", p->p_pid, sig, &oonstack, fp, &fp->sf_sc, ft); #endif if (useracc((caddr_t)fp, fsize, B_WRITE) == 0) { @@ -242,7 +242,7 @@ sendsig(catcher, sig, mask, code, type, val) } #ifdef DEBUG if ((sigdebug & SDB_FPSTATE) && *(char *)&kfp->sf_state.ss_fpstate) - printf("sendsig(%d): copy out FP state (%x) to %x\n", + printf("sendsig(%d): copy out FP state (%x) to %p\n", p->p_pid, *(u_int *)&kfp->sf_state.ss_fpstate, &kfp->sf_state.ss_fpstate); #endif @@ -267,7 +267,7 @@ sendsig(catcher, sig, mask, code, type, val) frame->f_regs[SP] = (int)fp; #ifdef DEBUG if (sigdebug & SDB_FOLLOW) - printf("sendsig(%d): sig %d scp %x fp %x sc_sp %x sc_ap %x\n", + printf("sendsig(%d): sig %d scp %p fp %p sc_sp %x sc_ap %x\n", p->p_pid, sig, kfp->sf_scp, fp, kfp->sf_sc.sc_sp, kfp->sf_sc.sc_ap); #endif @@ -312,7 +312,7 @@ sys_sigreturn(p, v, retval) scp = SCARG(uap, sigcntxp); #ifdef DEBUG if (sigdebug & SDB_FOLLOW) - printf("sigreturn: pid %d, scp %x\n", p->p_pid, scp); + printf("sigreturn: pid %d, scp %p\n", p->p_pid, scp); #endif if ((int)scp & 1) return (EINVAL); @@ -366,7 +366,7 @@ sys_sigreturn(p, v, retval) return (EJUSTRETURN); #ifdef DEBUG if ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid) - printf("sigreturn(%d): ssp %x usp %x scp %x ft %d\n", + printf("sigreturn(%d): ssp %p usp %x scp %p ft %d\n", p->p_pid, &flags, scp->sc_sp, SCARG(uap, sigcntxp), (flags&SS_RTEFRAME) ? tstate.ss_frame.f_format : -1); #endif @@ -406,7 +406,7 @@ sys_sigreturn(p, v, retval) m68881_restore(&tstate.ss_fpstate); #ifdef DEBUG if ((sigdebug & SDB_FPSTATE) && *(char *)&tstate.ss_fpstate) - printf("sigreturn(%d): copied in FP state (%x) at %x\n", + printf("sigreturn(%d): copied in FP state (%x) at %p\n", p->p_pid, *(u_int *)&tstate.ss_fpstate, &tstate.ss_fpstate); if ((sigdebug & SDB_FOLLOW) || diff --git a/sys/arch/m68k/m68k/sigcode.s b/sys/arch/m68k/m68k/sigcode.s new file mode 100644 index 00000000000..042807fdb2e --- /dev/null +++ b/sys/arch/m68k/m68k/sigcode.s @@ -0,0 +1,81 @@ +/* $OpenBSD: sigcode.s,v 1.1 1997/07/06 07:46:30 downsj Exp $ */ +/* $NetBSD: sigcode.s,v 1.2 1997/04/25 02:22:03 thorpej Exp $ */ + +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1980, 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah $Hdr: locore.s 1.66 92/12/22$ + * + * @(#)locore.s 8.6 (Berkeley) 5/27/94 + */ + +/* + * NOTICE: This is not a standalone file. To use it, #include it in + * your port's locore.s, like so: + * + * #include <m68k/m68k/sigcode.s> + */ + +/* + * Signal "trampoline" code (18 bytes). Invoked from RTE setup by sendsig(). + * + * Stack looks like: + * + * sp+0 -> signal number + * sp+4 signal specific code + * sp+8 pointer to signal context frame (scp) + * sp+12 address of handler + * sp+16 saved hardware state + * . + * . + * . + * scp+0 -> beginning of signal context frame + */ + + .data + .align 2 +GLOBAL(sigcode) + movl sp@(12),a0 | signal handler addr (4 bytes) + jsr a0@ | call signal handler (2 bytes) + addql #4,sp | pop signal number (2 bytes) +GLOBAL(sigcodetrap) + trap #1 | special syscall entry (2 bytes) + movl d0,sp@(4) | save errno (4 bytes) + moveq #1,d0 | syscall == exit (2 bytes) + trap #0 | exit(errno) (2 bytes) + .align 2 +GLOBAL(esigcode) diff --git a/sys/arch/m68k/m68k/sigreturn.s b/sys/arch/m68k/m68k/sigreturn.s index 63017e36048..cb8ac5cc65b 100644 --- a/sys/arch/m68k/m68k/sigreturn.s +++ b/sys/arch/m68k/m68k/sigreturn.s @@ -1,5 +1,5 @@ -/* $OpenBSD: sigreturn.s,v 1.1 1996/05/03 08:44:33 niklas Exp $ */ -/* $NetBSD: sigreturn.s,v 1.1 1996/01/31 02:22:15 thorpej Exp $ */ +/* $OpenBSD: sigreturn.s,v 1.2 1997/07/06 07:46:30 downsj Exp $ */ +/* $NetBSD: sigreturn.s,v 1.2 1997/04/25 02:22:04 thorpej Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -55,7 +55,7 @@ * because we must open a hole in the stack to fill in the (possibly much * larger) original stack frame. */ -sigreturn: +ASENTRY_NOPROFILE(sigreturn) lea sp@(-84),sp | leave enough space for largest frame movl sp@(84),sp@ | move up current 8 byte frame movl sp@(88),sp@(4) @@ -64,7 +64,7 @@ sigreturn: movl usp,a0 | save the user SP movl a0,sp@(FR_SP) | in the savearea movl #SYS_sigreturn,sp@- | push syscall number - jbsr _syscall | handle it + jbsr _C_LABEL(syscall) | handle it addql #4,sp | pop syscall# movl sp@(FR_SP),a0 | grab and restore movl a0,usp | user SP @@ -85,4 +85,4 @@ Lsigr1: movl a1,sp@(FR_SP) | new SP value moveml sp@+,#0x7FFF | restore user registers movl sp@,sp | and our SP - jra rei | all done + jra _ASM_LABEL(rei) | all done diff --git a/sys/arch/m68k/m68k/trap_subr.s b/sys/arch/m68k/m68k/trap_subr.s new file mode 100644 index 00000000000..bb2a570b20d --- /dev/null +++ b/sys/arch/m68k/m68k/trap_subr.s @@ -0,0 +1,159 @@ +/* $OpenBSD: trap_subr.s,v 1.1 1997/07/06 07:46:31 downsj Exp $ */ +/* $NetBSD: trap_subr.s,v 1.2 1997/06/04 22:12:43 is Exp $ */ + +/* + * Copyright (c) 1988 University of Utah. + * Copyright (c) 1980, 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * the Systems Programming Group of the University of Utah Computer + * Science Department. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: Utah $Hdr: locore.s 1.66 92/12/22$ + * + * @(#)locore.s 8.6 (Berkeley) 5/27/94 + */ + +/* + * NOTICE: This is not a standalone file. To use it, #include it in + * your port's locore.s, like so: + * + * #include <m68k/m68k/trap_subr.s> + */ + +/* + * Common fault handling code. Called by exception vector handlers. + * Registers have been saved, and type for trap() placed in d0. + */ +ASENTRY_NOPROFILE(fault) + movl usp,a0 | get and save + movl a0,sp@(FR_SP) | the user stack pointer + clrl sp@- | no VA arg + clrl sp@- | or code arg + movl d0,sp@- | push trap type + jbsr _C_LABEL(trap) | handle trap + lea sp@(12),sp | pop value args + movl sp@(FR_SP),a0 | restore + movl a0,usp | user SP + moveml sp@+,#0x7FFF | restore most user regs + addql #8,sp | pop SP and stack adjust + jra _ASM_LABEL(rei) | all done + +/* + * Similar to above, but will tidy up the stack, if necessary. + */ +ASENTRY(faultstkadj) + jbsr _C_LABEL(trap) | handle the error +/* for 68060 Branch Prediction Error handler */ +_ASM_LABEL(faultstkadjnotrap): + lea sp@(12),sp | pop value args +/* for new 68060 Branch Prediction Error handler */ +_ASM_LABEL(faultstkadjnotrap2): + movl sp@(FR_SP),a0 | restore user SP + movl a0,usp | from save area + movw sp@(FR_ADJ),d0 | need to adjust stack? + jne 1f | yes, go to it + moveml sp@+,#0x7FFF | no, restore most user regs + addql #8,sp | toss SSP and stkadj + jra _ASM_LABEL(rei) | all done +1: + lea sp@(FR_HW),a1 | pointer to HW frame + addql #8,a1 | source pointer + movl a1,a0 | source + addw d0,a0 | + hole size = dest pointer + movl a1@-,a0@- | copy + movl a1@-,a0@- | 8 bytes + movl a0,sp@(FR_SP) | new SSP + moveml sp@+,#0x7FFF | restore user registers + movl sp@,sp | and our SP + jra _ASM_LABEL(rei) | all done + +/* + * The following exceptions only cause four and six word stack frames + * and require no post-trap stack adjustment. + */ +ENTRY_NOPROFILE(illinst) + clrl sp@- + moveml #0xFFFF,sp@- + moveq #T_ILLINST,d0 + jra _ASM_LABEL(fault) + +ENTRY_NOPROFILE(zerodiv) + clrl sp@- + moveml #0xFFFF,sp@- + moveq #T_ZERODIV,d0 + jra _ASM_LABEL(fault) + +ENTRY_NOPROFILE(chkinst) + clrl sp@- + moveml #0xFFFF,sp@- + moveq #T_CHKINST,d0 + jra _ASM_LABEL(fault) + +ENTRY_NOPROFILE(trapvinst) + clrl sp@- + moveml #0xFFFF,sp@- + moveq #T_TRAPVINST,d0 + jra _ASM_LABEL(fault) + +ENTRY_NOPROFILE(privinst) + clrl sp@- + moveml #0xFFFF,sp@- + moveq #T_PRIVINST,d0 + jra _ASM_LABEL(fault) + +/* + * Coprocessor and format errors can generate mid-instruction stack + * frames and cause signal delivery, hence we need to check for potential + * stack adjustment. + */ +ENTRY_NOPROFILE(coperr) + clrl sp@- | stack adjust count + moveml #0xFFFF,sp@- + movl usp,a0 | get and save + movl a0,sp@(FR_SP) | the user stack pointer + clrl sp@- | no VA arg + clrl sp@- | or code arg + movl #T_COPERR,sp@- | push trap type + jra _ASM_LABEL(faultstkadj) | call trap and deal with stack + | adjustments + +ENTRY_NOPROFILE(fmterr) + clrl sp@- | stack adjust count + moveml #0xFFFF,sp@- + movl usp,a0 | get and save + movl a0,sp@(FR_SP) | the user stack pointer + clrl sp@- | no VA arg + clrl sp@- | or code arg + movl #T_FMTERR,sp@- | push trap type + jra _ASM_LABEL(faultstkadj) | call trap and deal with stack + | adjustments |