diff options
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 19 |
1 files changed, 1 insertions, 18 deletions
diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 34701ffb864..8d3f8297ffb 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.92 2022/04/26 08:35:30 claudio Exp $ */ +/* $OpenBSD: specialreg.h,v 1.93 2022/08/20 19:26:00 daniel Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -53,23 +53,6 @@ #define CR0_CD 0x40000000 /* Cache Disable */ /* - * Cyrix 486 DLC special registers, accessible as IO ports. - */ -#define CCR0 0xc0 /* configuration control register 0 */ -#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ -#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ -#define CCR0_A20M 0x04 /* enables A20M# input pin */ -#define CCR0_KEN 0x08 /* enables KEN# input pin */ -#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ -#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ -#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ -#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ - -#define CCR1 0xc1 /* configuration control register 1 */ -#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ -/* the remaining 7 bits of this register are reserved */ - -/* * bits in CR3 */ #define CR3_PCID 0xfffULL |