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-rw-r--r--sys/arch/arm/arm/bcopyinout.S15
-rw-r--r--sys/arch/arm/arm/copystr.S7
-rw-r--r--sys/arch/arm/arm/cpufunc_asm.S29
-rw-r--r--sys/arch/arm/arm/cpufunc_asm_armv4.S13
-rw-r--r--sys/arch/arm/arm/cpufunc_asm_armv7.S75
-rw-r--r--sys/arch/arm/arm/cpufunc_asm_xscale.S89
-rw-r--r--sys/arch/arm/arm/cpuswitch.S5
-rw-r--r--sys/arch/arm/arm/cpuswitch7.S7
-rw-r--r--sys/arch/arm/arm/irq_dispatch.S5
-rw-r--r--sys/arch/arm/arm/locore.S9
-rw-r--r--sys/arch/arm/xscale/pxa2x0_apm_asm.S23
-rw-r--r--sys/arch/armish/armish/armish_start.S19
-rw-r--r--sys/arch/armv7/armv7/armv7_start.S15
-rw-r--r--sys/arch/zaurus/zaurus/zaurus_start.S19
14 files changed, 172 insertions, 158 deletions
diff --git a/sys/arch/arm/arm/bcopyinout.S b/sys/arch/arm/arm/bcopyinout.S
index 93ef118a1d4..4a6e727f5fe 100644
--- a/sys/arch/arm/arm/bcopyinout.S
+++ b/sys/arch/arm/arm/bcopyinout.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: bcopyinout.S,v 1.4 2016/04/04 09:13:44 patrick Exp $ */
+/* $OpenBSD: bcopyinout.S,v 1.5 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: bcopyinout.S,v 1.13 2003/10/31 16:54:05 scw Exp $ */
/*
@@ -39,6 +39,7 @@
#include "assym.h"
#include <machine/asm.h>
+#include <arm/sysreg.h>
#ifdef __XSCALE__
#include "bcopyinout_xscale.S"
@@ -85,7 +86,7 @@ ENTRY(copyin)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r4, c13, c0, 4
+ mrc CP15_TPIDRPRW(r4)
#else
ldr r4, .Lcpu_info_primary
#endif
@@ -304,7 +305,7 @@ ENTRY(copyout)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r4, c13, c0, 4
+ mrc CP15_TPIDRPRW(r4)
#else
ldr r4, .Lcpu_info_primary
#endif
@@ -513,7 +514,7 @@ ENTRY(kcopy)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r4, c13, c0, 4
+ mrc CP15_TPIDRPRW(r4)
#else
ldr r4, .Lcpu_info_primary
#endif
@@ -701,7 +702,7 @@ ENTRY(kcopy)
ENTRY(badaddr_read_1)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r2, c13, c0, 4
+ mrc CP15_TPIDRPRW(r2)
#else
ldr r2, .Lcpu_info_primary
#endif
@@ -730,7 +731,7 @@ ENTRY(badaddr_read_1)
ENTRY(badaddr_read_2)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r2, c13, c0, 4
+ mrc CP15_TPIDRPRW(r2)
#else
ldr r2, .Lcpu_info_primary
#endif
@@ -759,7 +760,7 @@ ENTRY(badaddr_read_2)
ENTRY(badaddr_read_4)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r2, c13, c0, 4
+ mrc CP15_TPIDRPRW(r2)
#else
ldr r2, .Lcpu_info_primary
#endif
diff --git a/sys/arch/arm/arm/copystr.S b/sys/arch/arm/arm/copystr.S
index d588c520971..e5004e2e61d 100644
--- a/sys/arch/arm/arm/copystr.S
+++ b/sys/arch/arm/arm/copystr.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: copystr.S,v 1.5 2016/04/04 09:13:44 patrick Exp $ */
+/* $OpenBSD: copystr.S,v 1.6 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: copystr.S,v 1.8 2002/10/13 14:54:48 bjh21 Exp $ */
/*
@@ -41,6 +41,7 @@
#include "assym.h"
#include <machine/asm.h>
+#include <arm/sysreg.h>
#include <sys/errno.h>
.text
@@ -106,7 +107,7 @@ ENTRY(copyinstr)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r4, c13, c0, 4
+ mrc CP15_TPIDRPRW(r4)
#else
ldr r4, .Lcpu_info_primary
#endif
@@ -158,7 +159,7 @@ ENTRY(copyoutstr)
#ifdef CPU_ARMv7
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r4, c13, c0, 4
+ mrc CP15_TPIDRPRW(r4)
#else
ldr r4, .Lcpu_info_primary
#endif
diff --git a/sys/arch/arm/arm/cpufunc_asm.S b/sys/arch/arm/arm/cpufunc_asm.S
index c23bc31e361..ba74c69699b 100644
--- a/sys/arch/arm/arm/cpufunc_asm.S
+++ b/sys/arch/arm/arm/cpufunc_asm.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpufunc_asm.S,v 1.3 2016/04/03 13:55:23 jsg Exp $ */
+/* $OpenBSD: cpufunc_asm.S,v 1.4 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $ */
/*
@@ -44,6 +44,7 @@
#include <machine/cpu.h>
#include <machine/asm.h>
+#include <arm/sysreg.h>
.text
.align 0
@@ -62,31 +63,31 @@ ENTRY(cpufunc_nullop)
*/
ENTRY(cpufunc_id)
- mrc p15, 0, r0, c0, c0, 0
+ mrc CP15_MIDR(r0)
mov pc, lr
ENTRY(cpu_get_control)
- mrc p15, 0, r0, c1, c0, 0
+ mrc CP15_SCTLR(r0)
mov pc, lr
ENTRY(cpu_read_cache_config)
- mrc p15, 0, r0, c0, c0, 1
+ mrc CP15_CTR(r0)
mov pc, lr
ENTRY(cpufunc_dfsr)
- mrc p15, 0, r0, c5, c0, 0
+ mrc CP15_DFSR(r0)
mov pc, lr
ENTRY(cpufunc_dfar)
- mrc p15, 0, r0, c6, c0, 0
+ mrc CP15_DFAR(r0)
mov pc, lr
ENTRY(cpufunc_ifsr)
- mrc p15, 0, r0, c5, c0, 1
+ mrc CP15_IFSR(r0)
mov pc, lr
ENTRY(cpufunc_ifar)
- mrc p15, 0, r0, c6, c0, 2
+ mrc CP15_IFAR(r0)
mov pc, lr
@@ -103,12 +104,12 @@ ENTRY(cpufunc_ifar)
#if 0 /* See below. */
ENTRY(cpufunc_control)
- mcr p15, 0, r0, c1, c0, 0
+ mcr CP15_SCTLR(r0)
mov pc, lr
#endif
ENTRY(cpufunc_domains)
- mcr p15, 0, r0, c3, c0, 0
+ mcr CP15_DACR(r0)
mov pc, lr
/*
@@ -122,22 +123,22 @@ ENTRY(cpufunc_domains)
*/
ENTRY(cpufunc_control)
- mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
+ mrc CP15_SCTLR(r3) /* Read the control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there is a change */
- mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
+ mcrne CP15_SCTLR(r2) /* Write new control register */
mov r0, r3 /* Return old value */
mov pc, lr
ENTRY(cpufunc_auxcontrol)
- mrc p15, 0, r3, c1, c0, 1 /* Read the aux control register */
+ mrc CP15_ACTLR(r3) /* Read the aux control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there is a change */
- mcrne p15, 0, r2, c1, c0, 1 /* Write new aux control register */
+ mcrne CP15_ACTLR(r2) /* Write new aux control register */
mov r0, r3 /* Return old value */
mov pc, lr
diff --git a/sys/arch/arm/arm/cpufunc_asm_armv4.S b/sys/arch/arm/arm/cpufunc_asm_armv4.S
index 35089398b4c..94edccb528e 100644
--- a/sys/arch/arm/arm/cpufunc_asm_armv4.S
+++ b/sys/arch/arm/arm/cpufunc_asm_armv4.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpufunc_asm_armv4.S,v 1.1 2004/02/01 05:09:48 drahn Exp $ */
+/* $OpenBSD: cpufunc_asm_armv4.S,v 1.2 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: cpufunc_asm_armv4.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $ */
/*
@@ -39,29 +39,30 @@
#include <machine/cpu.h>
#include <machine/asm.h>
+#include <arm/sysreg.h>
/*
* TLB functions
*/
ENTRY(armv4_tlb_flushID)
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
+ mcr CP15_TLBIALL(r0) /* flush I+D tlb */
mov pc, lr
ENTRY(armv4_tlb_flushI)
- mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
+ mcr CP15_ITLBIALL /* flush I tlb */
mov pc, lr
ENTRY(armv4_tlb_flushD)
- mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
+ mcr CP15_DTLBIALL /* flush D tlb */
mov pc, lr
ENTRY(armv4_tlb_flushD_SE)
- mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
+ mcr CP15_DTLBIMVA /* flush D tlb single entry */
mov pc, lr
/*
* Other functions
*/
ENTRY(armv4_drain_writebuf)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
mov pc, lr
diff --git a/sys/arch/arm/arm/cpufunc_asm_armv7.S b/sys/arch/arm/arm/cpufunc_asm_armv7.S
index 0d71331b5f9..6a6eeb16a9e 100644
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpufunc_asm_armv7.S,v 1.9 2016/04/04 09:06:28 patrick Exp $ */
+/* $OpenBSD: cpufunc_asm_armv7.S,v 1.10 2016/04/25 04:46:56 jsg Exp $ */
/*
* Copyright (c) 2008 Dale Rahn <drahn@openbsd.org>
*
@@ -17,6 +17,7 @@
#include <machine/cpu.h>
#include <machine/asm.h>
+#include <arm/sysreg.h>
ENTRY(armv7_cpu_sleep)
wfi
@@ -31,20 +32,20 @@ ENTRY(armv7_drain_writebuf)
* Function to read the MPCore base address
*/
ENTRY(armv7_periphbase)
- mrc p15, 4, r0, c15, c0, 0
+ mrc CP15_CBAR(r0)
mov pc, lr
/*
* Functions to set the MMU Translation Table Base register
*/
ENTRY(armv7_setttb)
- mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
- mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */
+ mcr CP15_ICIALLU /* Flush I cache */
+ mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
- mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ mcr CP15_TTBR0(r0) /* load new TTB */
+ mcr CP15_TLBIALL(r0) /* invalidate I+D TLBs */
dsb sy
isb sy
@@ -54,16 +55,16 @@ ENTRY(armv7_setttb)
* TLB functions
*/
ENTRY(armv7_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
- mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
- mcr p15, 0, r0, c7, c5, 7 /* flush va from BP */
+ mcr CP15_DTLBIMVA /* flush D tlb single entry */
+ mcr CP15_ITLBIMVA /* flush I tlb single entry */
+ mcr CP15_BPIMVA /* flush va from BP */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushI_SE)
- mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
- mcr p15, 0, r0, c7, c5, 7 /* flush va from BP */
+ mcr CP15_ITLBIMVA /* flush I tlb single entry */
+ mcr CP15_BPIMVA /* flush va from BP */
dsb sy
isb sy
mov pc, lr
@@ -72,27 +73,27 @@ ENTRY(armv7_tlb_flushI_SE)
* TLB functions
*/
ENTRY(armv7_tlb_flushID)
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
- mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */
+ mcr CP15_TLBIALL(r0) /* flush I+D tlb */
+ mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushI)
- mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
- mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */
+ mcr CP15_ITLBIALL /* flush I tlb */
+ mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushD)
- mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
+ mcr CP15_DTLBIALL /* flush D tlb */
dsb sy
isb sy
mov pc, lr
ENTRY(armv7_tlb_flushD_SE)
- mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
+ mcr CP15_DTLBIMVA /* flush D tlb single entry */
dsb sy
isb sy
mov pc, lr
@@ -124,12 +125,12 @@ ENTRY(armv7_icache_sync_range)
add r1, r1, r2
bic r0, r0, r3
1:
- mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
+ mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */
+ mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */
add r0, r0, ip
subs r1, r1, ip
bhi 1b
- mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */
+ mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
mov pc, lr
@@ -141,8 +142,8 @@ ENTRY(armv7_icache_sync_all)
* dcache, so that we can safely flush the Icache and fall through
* into the Dcache cleaning code.
*/
- mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
- mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */
+ mcr CP15_ICIALLU /* Flush I cache */
+ mcr CP15_BPIALL /* Flush BP cache */
isb sy
mov pc, lr
@@ -157,7 +158,7 @@ ENTRY(armv7_dcache_wb_range)
add r1, r1, r2
bic r0, r0, r3
1:
- mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
+ mcr CP15_DCCMVAC(r0) /* Clean D cache SE with VA */
add r0, r0, ip
subs r1, r1, ip
bhi 1b
@@ -176,13 +177,13 @@ ENTRY(armv7_idcache_wbinv_range)
add r1, r1, r2
bic r0, r0, r3
1:
- mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
+ mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */
+ mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */
+ mcr CP15_CNTPCT(r0, c7), 1 /* Purge D cache SE with VA */
add r0, r0, ip
subs r1, r1, ip
bhi 1b
- mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */
+ mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
mov pc, lr
@@ -198,9 +199,9 @@ ENTRY(armv7_dcache_wbinv_range)
add r1, r1, r2
bic r0, r0, r3
1:
- mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
+ mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */
+ mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */
+ mcr CP15_CNTPCT(r0, c7), 1 /* Purge D cache SE with VA */
add r0, r0, ip
subs r1, r1, ip
bhi 1b
@@ -219,9 +220,9 @@ ENTRY(armv7_dcache_inv_range)
add r1, r1, r2
bic r0, r0, r3
1:
- mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
+ mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */
+ mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */
+ mcr CP15_DCIMVAC(r0) /* Invalidate D cache SE with VA */
add r0, r0, ip
subs r1, r1, ip
bhi 1b
@@ -244,13 +245,13 @@ ENTRY(armv7_context_switch)
* We can assume that the caches will only contain kernel addresses
* at this point. So no need to flush them again.
*/
- mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
- mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */
+ mcr CP15_ICIALLU /* Flush I cache */
+ mcr CP15_BPIALL /* Flush BP cache */
dsb sy
isb sy
- mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
+ mcr CP15_TTBR0(r0) /* set the new TTB */
+ mcr CP15_TLBIALL(r0) /* and flush the I+D tlbs */
dsb sy
isb sy
mov pc, lr
diff --git a/sys/arch/arm/arm/cpufunc_asm_xscale.S b/sys/arch/arm/arm/cpufunc_asm_xscale.S
index 20d0153b88d..0677c0a1a59 100644
--- a/sys/arch/arm/arm/cpufunc_asm_xscale.S
+++ b/sys/arch/arm/arm/cpufunc_asm_xscale.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpufunc_asm_xscale.S,v 1.7 2016/01/31 00:14:50 jsg Exp $ */
+/* $OpenBSD: cpufunc_asm_xscale.S,v 1.8 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: cpufunc_asm_xscale.S,v 1.16 2002/08/17 16:36:32 thorpej Exp $ */
/*
@@ -74,6 +74,7 @@
#include <machine/cpu.h>
#include <machine/asm.h>
+#include <arm/sysreg.h>
/*
* Size of the XScale core caches.
@@ -90,14 +91,14 @@
sub pc, pc, #4
#define CPWAIT(tmp) \
- mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
+ mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\
mov tmp, tmp /* wait for it to complete */ ;\
CPWAIT_BRANCH /* branch to next insn */
#define CPWAIT_AND_RETURN_SHIFTER lsr #32
#define CPWAIT_AND_RETURN(tmp) \
- mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
+ mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\
/* Wait for it to complete and branch to the return address */ \
sub pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER
@@ -110,13 +111,13 @@ ENTRY(xscale_cpwait)
* changes in the control register.
*/
ENTRY(xscale_control)
- mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
+ mrc CP15_SCTLR(r3) /* Read the control register */
bic r2, r3, r0 /* Clear bits */
eor r2, r2, r1 /* XOR bits */
teq r2, r3 /* Only write if there was a change */
- mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */
- mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
+ mcrne CP15_BPIALL /* Invalidate the BTB */
+ mcrne CP15_SCTLR(r2) /* Write new control register */
mov r0, r3 /* Return old value */
CPWAIT_AND_RETURN(r1)
@@ -134,21 +135,21 @@ ENTRY(xscale_setttb)
stmfd sp!, {r0-r3, lr}
bl _C_LABEL(xscale_cache_cleanID)
- mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
- mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
+ mcr CP15_ICIALLU /* invalidate I$ and BTB */
+ mcr CP15_CP15DSB(r0) /* drain write and fill buffer */
CPWAIT(r0)
ldmfd sp!, {r0-r3, lr}
/* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0
+ mcr CP15_TTBR0(r0)
/* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
+ mcr CP15_TLBIALL(r0) /* invalidate I+D TLB */
/* The cleanID above means we only need to flush the I cache here */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
+ mcr CP15_ICIALLU /* invalidate I$ and BTB */
CPWAIT(r0)
@@ -162,8 +163,8 @@ ENTRY(xscale_setttb)
* TLB operations, because we expect a pmap_update() to follow.
*/
ENTRY(xscale_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
- mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
+ mcr CP15_DTLBIMVA /* flush D tlb single entry */
+ mcr CP15_ITLBIMVA /* flush I tlb single entry */
mov pc, lr
/*
@@ -174,7 +175,7 @@ ENTRY(xscale_cache_flushID)
CPWAIT_AND_RETURN(r0)
ENTRY(xscale_cache_flushI)
- mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
+ mcr CP15_ICIALLU /* flush I cache */
CPWAIT_AND_RETURN(r0)
ENTRY(xscale_cache_flushD)
@@ -182,7 +183,7 @@ ENTRY(xscale_cache_flushD)
CPWAIT_AND_RETURN(r0)
ENTRY(xscale_cache_flushI_SE)
- mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
+ mcr CP15_ICIMVAU(r0) /* flush I cache single entry */
CPWAIT_AND_RETURN(r0)
ENTRY(xscale_cache_flushD_SE)
@@ -191,12 +192,12 @@ ENTRY(xscale_cache_flushD_SE)
* before invalidate-dcache-line to an address, or dirty
* bits will not be cleared in the dcache array.
*/
- mcr p15, 0, r0, c7, c10, 1
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
+ mcr CP15_DCCMVAC(r0)
+ mcr CP15_DCIMVAC(r0) /* flush D cache single entry */
CPWAIT_AND_RETURN(r0)
ENTRY(xscale_cache_cleanD_E)
- mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
+ mcr CP15_DCCMVAC(r0) /* clean D cache entry */
CPWAIT_AND_RETURN(r0)
/*
@@ -275,7 +276,7 @@ _C_LABEL(xscale_cache_clean_size):
ENTRY_NP(xscale_cache_syncI)
ENTRY_NP(xscale_cache_purgeID)
- mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
+ mcr CP15_ICIALLU /* flush I cache (D cleaned below) */
ENTRY_NP(xscale_cache_cleanID)
ENTRY_NP(xscale_cache_purgeD)
ENTRY(xscale_cache_cleanD)
@@ -288,7 +289,7 @@ ENTRY(xscale_cache_cleanD)
CPWAIT(r0)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
CPWAIT(r0)
@@ -310,23 +311,23 @@ ENTRY(xscale_cache_clean_minidata)
subs r1, r1, #32
bne 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
CPWAIT_AND_RETURN(r1)
ENTRY(xscale_cache_purgeID_E)
- mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
+ mcr CP15_DCCMVAC(r0) /* clean D cache entry */
CPWAIT(r1)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
+ mcr CP15_ICIMVAU(r0) /* flush I cache single entry */
+ mcr CP15_DCIMVAC(r0) /* flush D cache single entry */
CPWAIT_AND_RETURN(r1)
ENTRY(xscale_cache_purgeD_E)
- mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
+ mcr CP15_DCCMVAC(r0) /* clean D cache entry */
CPWAIT(r1)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
+ mcr CP15_DCIMVAC(r0) /* flush D cache single entry */
CPWAIT_AND_RETURN(r1)
/*
@@ -343,14 +344,14 @@ ENTRY(xscale_cache_cleanD_rng)
add r1, r1, r2
bic r0, r0, #0x1f
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
+1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */
add r0, r0, #32
subs r1, r1, #32
bhi 1b
CPWAIT(r0)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
CPWAIT_AND_RETURN(r0)
@@ -362,16 +363,16 @@ ENTRY(xscale_cache_purgeID_rng)
add r1, r1, r2
bic r0, r0, #0x1f
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
- mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
+1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */
+ mcr CP15_DCIMVAC(r0) /* flush D cache single entry */
+ mcr CP15_ICIMVAU(r0) /* flush I cache single entry */
add r0, r0, #32
subs r1, r1, #32
bhi 1b
CPWAIT(r0)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
CPWAIT_AND_RETURN(r0)
@@ -383,15 +384,15 @@ ENTRY(xscale_cache_purgeD_rng)
add r1, r1, r2
bic r0, r0, #0x1f
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
+1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */
+ mcr CP15_DCIMVAC(r0) /* flush D cache single entry */
add r0, r0, #32
subs r1, r1, #32
bhi 1b
CPWAIT(r0)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
CPWAIT_AND_RETURN(r0)
@@ -403,15 +404,15 @@ ENTRY(xscale_cache_syncI_rng)
add r1, r1, r2
bic r0, r0, #0x1f
-1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
- mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
+1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */
+ mcr CP15_ICIMVAU(r0) /* flush I cache single entry */
add r0, r0, #32
subs r1, r1, #32
bhi 1b
CPWAIT(r0)
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
CPWAIT_AND_RETURN(r0)
@@ -423,12 +424,12 @@ ENTRY(xscale_cache_flushD_rng)
add r1, r1, r2
bic r0, r0, #0x1f
-1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
+1: mcr CP15_DCIMVAC(r0) /* flush D cache single entry */
add r0, r0, #32
subs r1, r1, #32
bhi 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
CPWAIT_AND_RETURN(r0)
@@ -450,10 +451,10 @@ ENTRY(xscale_context_switch)
*/
/* Write the TTB */
- mcr p15, 0, r0, c2, c0, 0
+ mcr CP15_TTBR0(r0)
/* If we have updated the TTB we must flush the TLB */
- mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
+ mcr CP15_TLBIALL(r0) /* flush the I+D tlb */
CPWAIT_AND_RETURN(r0)
diff --git a/sys/arch/arm/arm/cpuswitch.S b/sys/arch/arm/arm/cpuswitch.S
index 62a37e2383a..b76aa35d69e 100644
--- a/sys/arch/arm/arm/cpuswitch.S
+++ b/sys/arch/arm/arm/cpuswitch.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpuswitch.S,v 1.16 2016/04/24 01:31:02 patrick Exp $ */
+/* $OpenBSD: cpuswitch.S,v 1.17 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */
/*
@@ -83,6 +83,7 @@
#include <machine/frame.h>
#include <machine/intr.h>
#include <machine/asm.h>
+#include <arm/sysreg.h>
/* LINTSTUB: include <sys/param.h> */
@@ -338,7 +339,7 @@ ENTRY(cpu_switchto)
cmp r7, #0 /* No need to fixup vector table? */
ldrne r2, [r7] /* But if yes, fetch current value */
ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
- mcr p15, 0, r1, c3, c0, 0 /* Update DACR for new context */
+ mcr CP15_DACR(r1) /* Update DACR for new context */
cmpne r2, r0 /* Stuffing the same value? */
#ifndef PMAP_INCLUDE_PTE_SYNC
strne r0, [r7] /* Nope, update it */
diff --git a/sys/arch/arm/arm/cpuswitch7.S b/sys/arch/arm/arm/cpuswitch7.S
index 8ebcfacc031..e59fe027223 100644
--- a/sys/arch/arm/arm/cpuswitch7.S
+++ b/sys/arch/arm/arm/cpuswitch7.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpuswitch7.S,v 1.7 2016/04/24 01:31:02 patrick Exp $ */
+/* $OpenBSD: cpuswitch7.S,v 1.8 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */
/*
@@ -83,6 +83,7 @@
#include <machine/frame.h>
#include <machine/intr.h>
#include <machine/asm.h>
+#include <arm/sysreg.h>
/* LINTSTUB: include <sys/param.h> */
@@ -161,7 +162,7 @@ ENTRY(cpu_switchto)
sub sp, sp, #4
/* Get curcpu from TPIDRPRW. */
- mrc p15, 0, r3, c13, c0, 4
+ mrc CP15_TPIDRPRW(r3)
#ifdef MULTIPROCESSOR
str r3, [r1, #(P_CPU)]
#else
@@ -287,7 +288,7 @@ ENTRY(cpu_switchto)
cmp r7, #0 /* No need to fixup vector table? */
ldrne r2, [r7] /* But if yes, fetch current value */
ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
- mcr p15, 0, r1, c3, c0, 0 /* Update DACR for new context */
+ mcr CP15_DACR(r1) /* Update DACR for new context */
cmpne r2, r0 /* Stuffing the same value? */
#ifndef PMAP_INCLUDE_PTE_SYNC
strne r0, [r7] /* Nope, update it */
diff --git a/sys/arch/arm/arm/irq_dispatch.S b/sys/arch/arm/arm/irq_dispatch.S
index 2fc274bf391..bdcb08b824b 100644
--- a/sys/arch/arm/arm/irq_dispatch.S
+++ b/sys/arch/arm/arm/irq_dispatch.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: irq_dispatch.S,v 1.10 2016/04/04 09:13:44 patrick Exp $ */
+/* $OpenBSD: irq_dispatch.S,v 1.11 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: irq_dispatch.S,v 1.5 2003/10/30 08:57:24 scw Exp $ */
/*
@@ -71,6 +71,7 @@
#include "assym.h"
#include <machine/asm.h>
+#include <arm/sysreg.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <machine/intr.h>
@@ -106,7 +107,7 @@ ASENTRY_NP(irq_entry)
* r6 old value of curcpu()->ci_idepth
*/
#ifdef CPU_ARMv7
- mrc p15, 0, r5, c13, c0, 4 /* Get curcpu from TPIDRPRW. */
+ mrc CP15_TPIDRPRW(r5) /* Get curcpu from TPIDRPRW. */
#else
ldr r5, .Lcpu_info_primary
#endif
diff --git a/sys/arch/arm/arm/locore.S b/sys/arch/arm/arm/locore.S
index b91d060e74e..213479b8b0e 100644
--- a/sys/arch/arm/arm/locore.S
+++ b/sys/arch/arm/arm/locore.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.S,v 1.9 2016/04/04 09:13:44 patrick Exp $ */
+/* $OpenBSD: locore.S,v 1.10 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
/*
@@ -36,6 +36,7 @@
#include <sys/syscall.h>
#include <sys/errno.h>
#include <machine/asm.h>
+#include <arm/sysreg.h>
#include <machine/cpu.h>
#include <machine/frame.h>
@@ -59,7 +60,7 @@ ASENTRY_NP(start)
ldmia r1, {r1, r2, r8, sp} /* Set initial stack and */
#ifdef CPU_ARMv7
- mcr p15, 0, r8, c13, c0, 4 /* put curcpu into the TPIDRPRW */
+ mcr CP15_TPIDRPRW(r8) /* put curcpu into the TPIDRPRW */
#endif
sub r2, r2, r1 /* get zero init data */
@@ -141,8 +142,8 @@ ENTRY_NP(cpu_reset)
* Hurl ourselves into the ROM
*/
mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
- mcr p15, 0, r0, c1, c0, 0
- mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
+ mcr CP15_SCTLR(r0)
+ mcrne CP15_TLBIALL(r2) /* nail I+D TLB on ARMv4 and greater */
mov pc, r4
/*
diff --git a/sys/arch/arm/xscale/pxa2x0_apm_asm.S b/sys/arch/arm/xscale/pxa2x0_apm_asm.S
index 83907fea32d..7ed388e463e 100644
--- a/sys/arch/arm/xscale/pxa2x0_apm_asm.S
+++ b/sys/arch/arm/xscale/pxa2x0_apm_asm.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0_apm_asm.S,v 1.5 2016/01/31 00:14:50 jsg Exp $ */
+/* $OpenBSD: pxa2x0_apm_asm.S,v 1.6 2016/04/25 04:46:56 jsg Exp $ */
/*
* Copyright (c) 2005 Uwe Stuehler <uwe@openbsd.org>
@@ -17,6 +17,7 @@
*/
#include <machine/asm.h>
+#include <arm/sysreg.h>
#include <machine/cpu.h>
#include <arch/arm/xscale/pxa2x0reg.h>
@@ -147,19 +148,19 @@ ENTRY(pxa2x0_cpu_suspend)
ldr r2, =pxa2x0_cpu_resume_virt
str r2, [r3], #4
- mrc p15, 0, r2, c1, c0, 0 /* Load MMU control register. */
+ mrc CP15_SCTLR(r2) /* Load MMU control register. */
mov r0, #0xff000000
orr r0, r0, #0x00ff0000
bic r2, r2, r0 /* Clear undefined bits. */
str r2, [r3], #4 /* Save MMU control register. */
- mrc p15, 0, r2, c2, c0, 0 /* Load TTB address. */
+ mrc CP15_TTBR0(r2) /* Load TTB address. */
mov r0, #0x00003f00
orr r0, r0, #0x000000ff
bic r2, r2, r0 /* Clear undefined bits. */
str r2, [r3], #4 /* Save TTB address. */
- mrc p15, 0, r2, c3, c0, 0 /* Load domain access control. */
+ mrc CP15_DACR(r2) /* Load domain access control. */
str r2, [r3], #4 /* Save domain access control. */
mrs r2, spsr /* Load SVC saved CPSR. */
@@ -196,7 +197,7 @@ ENTRY(pxa2x0_cpu_suspend)
/* At this point all critical registers have been saved. */
mov r0, #0
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
mov r1, #DCACHE_CACHELINECOUNT
ldr r2, .Lxscale_cache_clean_addr
@@ -215,7 +216,7 @@ cache_flush_loop:
msr cpsr_c, r2 /* disable IRQ/FIQ */
mcr p15, 0, r0, c7, c2, 5 /* allocate cache line */
- mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
+ mcr CP15_DCIMVAC(r0) /* flush D cache single entry */
mrs r2, cpsr
and r2, r2, #~(PSR_I|PSR_F)
@@ -226,7 +227,7 @@ cache_flush_loop:
bne cache_flush_loop
mov r0, #0
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mcr CP15_CP15DSB(r0) /* drain write buffer */
b 1f
1:
@@ -305,11 +306,11 @@ ENTRY(pxa2x0_cpu_resume)
ldr r0, .Lsleepdata_phys /* Point to PA of saved data. */
ldmia r0!, {r7-r10}
- mcr p15, 0, r10, c3, c0, 0 /* Restore domain access control. */
- mcr p15, 0, r9, c2, c0, 0 /* Restore TTB address. */
- mcr p15, 0, r0, c8, c7, 0 /* Flush I+D TLBs. */
+ mcr CP15_DACR(r10) /* Restore domain access control. */
+ mcr CP15_TTBR0(r9) /* Restore TTB address. */
+ mcr CP15_TLBIALL(r0) /* Flush I+D TLBs. */
mcr p15, 0, r0, c7, c7, 0 /* Flush I+D BTB. */
- mcr p15, 0, r8, c1, c0, 0 /* Restore MMU control. */
+ mcr CP15_SCTLR(r8) /* Restore MMU control. */
mov pc, r7 /* Jump to virtual address. */
nop
nop
diff --git a/sys/arch/armish/armish/armish_start.S b/sys/arch/armish/armish/armish_start.S
index 16c2b4e5a25..91d72239c01 100644
--- a/sys/arch/armish/armish/armish_start.S
+++ b/sys/arch/armish/armish/armish_start.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: armish_start.S,v 1.2 2006/05/29 17:30:26 drahn Exp $ */
+/* $OpenBSD: armish_start.S,v 1.3 2016/04/25 04:46:56 jsg Exp $ */
/* $NetBSD: iq80321_start.S,v 1.4 2002/10/14 22:32:54 bjh21 Exp $ */
/*
@@ -37,6 +37,7 @@
*/
#include <machine/asm.h>
+#include <arm/sysreg.h>
#include <arm/armreg.h>
#include <arm/pte.h>
@@ -55,9 +56,9 @@ _C_LABEL(iq80321_start):
bic r8, r8, #0xff000000 /* clear upper 8 bits */
orr r8, r8, #0xa0000000 /* OR in physical base address */
- mrc p15, 0, r2, c1, c0, 0
+ mrc CP15_SCTLR(r2)
bic r2, r2, #CPU_CONTROL_MMU_ENABLE
- mcr p15, 0, r2, c1, c0, 0
+ mcr CP15_SCTLR(r2)
nop
nop
@@ -118,29 +119,29 @@ Lunmapped:
/* OK! Page table is set up. Give it to the CPU. */
adr r0, Ltable
ldr r0, [r0]
- mcr p15, 0, r0, c2, c0, 0
+ mcr CP15_TTBR0(r0)
/* Flush the old TLBs, just in case. */
- mcr p15, 0, r0, c8, c7, 0
+ mcr CP15_TLBIALL(r0)
/* Set the Domain Access register. Very important! */
mov r0, #1
- mcr p15, 0, r0, c3, c0, 0
+ mcr CP15_DACR(r0)
/* Get ready to jump to the "real" kernel entry point... */
ldr r0, Lstart
/* OK, let's enable the MMU. */
- mrc p15, 0, r2, c1, c0, 0
+ mrc CP15_SCTLR(r2)
orr r2, r2, #CPU_CONTROL_MMU_ENABLE
- mcr p15, 0, r2, c1, c0, 0
+ mcr CP15_SCTLR(r2)
nop
nop
nop
/* CPWAIT sequence to make sure the MMU is on... */
- mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */
+ mrc CP15_TTBR0(r2) /* arbitrary read of CP15 */
mov r2, r2 /* force it to complete */
mov pc, r0 /* leap to kernel entry point! */
diff --git a/sys/arch/armv7/armv7/armv7_start.S b/sys/arch/armv7/armv7/armv7_start.S
index 6ec8ef6280c..f78598eb2ce 100644
--- a/sys/arch/armv7/armv7/armv7_start.S
+++ b/sys/arch/armv7/armv7/armv7_start.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: armv7_start.S,v 1.5 2016/01/31 00:14:50 jsg Exp $ */
+/* $OpenBSD: armv7_start.S,v 1.6 2016/04/25 04:46:57 jsg Exp $ */
/* $NetBSD: lubbock_start.S,v 1.1 2003/06/18 10:51:15 bsh Exp $ */
/*
@@ -31,6 +31,7 @@
*/
#include <machine/asm.h>
+#include <arm/sysreg.h>
#include <arm/armreg.h>
#include <arm/pte.h>
@@ -50,7 +51,7 @@
sub pc, pc, #4
#define CPWAIT(tmp) \
- mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
+ mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\
mov tmp, tmp /* wait for it to complete */ ;\
CPWAIT_BRANCH /* branch to next insn */
@@ -146,17 +147,17 @@ _C_LABEL(bootstrap_start):
cmp r1, #0
bne 2b
- mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
- mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
+ mcr CP15_TTBR0(r0) /* Set TTB */
+ mcr CP15_TLBIALL(r0) /* Flush TLB */
/* Set the Domain Access register. Very important! */
mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
- mcr p15, 0, r0, c3, c0, 0
+ mcr CP15_DACR(r0)
/* Enable MMU */
- mrc p15, 0, r0, c1, c0, 0
+ mrc CP15_SCTLR(r0)
orr r0, r0, #CPU_CONTROL_MMU_ENABLE
- mcr p15, 0, r0, c1, c0, 0
+ mcr CP15_SCTLR(r0)
CPWAIT(r0)
/* Restore U-Boot arguments */
diff --git a/sys/arch/zaurus/zaurus/zaurus_start.S b/sys/arch/zaurus/zaurus/zaurus_start.S
index 228ec65cac7..8727992471f 100644
--- a/sys/arch/zaurus/zaurus/zaurus_start.S
+++ b/sys/arch/zaurus/zaurus/zaurus_start.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: zaurus_start.S,v 1.3 2014/02/12 05:31:58 miod Exp $ */
+/* $OpenBSD: zaurus_start.S,v 1.4 2016/04/25 04:46:57 jsg Exp $ */
/* $NetBSD: lubbock_start.S,v 1.1 2003/06/18 10:51:15 bsh Exp $ */
/*
@@ -31,6 +31,7 @@
*/
#include <machine/asm.h>
+#include <arm/sysreg.h>
#include <arm/armreg.h>
#include <arm/pte.h>
@@ -51,7 +52,7 @@
sub pc, pc, #4
#define CPWAIT(tmp) \
- mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
+ mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\
mov tmp, tmp /* wait for it to complete */ ;\
CPWAIT_BRANCH /* branch to next insn */
@@ -107,12 +108,12 @@ zaurus_start_ram:
* in VA 0xc0200000..
*/
- mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */
+ mrc CP15_TTBR0(r0) /* get ttb prepared by redboot */
adr r4, mmu_init_table2
#define BUILD_STARTUP_PAGETABLE
#ifdef BUILD_STARTUP_PAGETABLE
- mrc p15, 0, r2, c1, c0, 0
+ mrc CP15_SCTLR(r2)
mov r2, #0
tst r2, #CPU_CONTROL_MMU_ENABLE /* we already have a page table? */
bne 3f
@@ -134,17 +135,17 @@ zaurus_start_ram:
bne 2b
#endif
- mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
- mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
+ mcr CP15_TTBR0(r0) /* Set TTB */
+ mcr CP15_TLBIALL(r0) /* Flush TLB */
/* Set the Domain Access register. Very important! */
mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
- mcr p15, 0, r0, c3, c0, 0
+ mcr CP15_DACR(r0)
/* Enable MMU */
- mrc p15, 0, r0, c1, c0, 0
+ mrc CP15_SCTLR(r0)
orr r0, r0, #CPU_CONTROL_MMU_ENABLE
- mcr p15, 0, r0, c1, c0, 0
+ mcr CP15_SCTLR(r0)
CPWAIT(r0)
/* Jump to kernel code in TRUE VA */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 23:47:11 +0000