diff options
35 files changed, 168 insertions, 168 deletions
diff --git a/sys/arch/arm/arm/arm32_machdep.c b/sys/arch/arm/arm/arm32_machdep.c index 4fc89d541d4..0149df78c68 100644 --- a/sys/arch/arm/arm/arm32_machdep.c +++ b/sys/arch/arm/arm/arm32_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: arm32_machdep.c,v 1.47 2015/01/12 16:33:31 deraadt Exp $ */ +/* $OpenBSD: arm32_machdep.c,v 1.48 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: arm32_machdep.c,v 1.42 2003/12/30 12:33:15 pk Exp $ */ /* @@ -204,7 +204,7 @@ bootsync(int howto) bootsyncdone = 1; /* Make sure we can still manage to do things */ - if (__get_cpsr() & I32_bit) { + if (__get_cpsr() & PSR_I) { /* * If we get here then boot has been called without RB_NOSYNC * and interrupts were disabled. This means the boot() call diff --git a/sys/arch/arm/arm/cpufunc_asm_sa1.S b/sys/arch/arm/arm/cpufunc_asm_sa1.S index d729af49985..079cc9d1768 100644 --- a/sys/arch/arm/arm/cpufunc_asm_sa1.S +++ b/sys/arch/arm/arm/cpufunc_asm_sa1.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc_asm_sa1.S,v 1.5 2015/01/18 14:55:02 jsg Exp $ */ +/* $OpenBSD: cpufunc_asm_sa1.S,v 1.6 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: cpufunc_asm_sa1.S,v 1.8 2002/08/17 16:36:32 thorpej Exp $ */ /* @@ -47,7 +47,7 @@ */ ENTRY(sa1_setttb) mrs r3, cpsr - orr r1, r3, #(I32_bit | F32_bit) + orr r1, r3, #(PSR_I | PSR_F) msr cpsr_c, r1 stmfd sp!, {r0-r3, lr} @@ -132,7 +132,7 @@ _C_LABEL(sa1_cache_clean_size): #define SA1_CACHE_CLEAN_BLOCK \ mrs r3, cpsr ; \ - orr r0, r3, #(I32_bit | F32_bit) ; \ + orr r0, r3, #(PSR_I | PSR_F) ; \ msr cpsr_c, r0 #define SA1_CACHE_CLEAN_UNBLOCK \ diff --git a/sys/arch/arm/arm/cpufunc_asm_xscale.S b/sys/arch/arm/arm/cpufunc_asm_xscale.S index fc0c81ff050..20d0153b88d 100644 --- a/sys/arch/arm/arm/cpufunc_asm_xscale.S +++ b/sys/arch/arm/arm/cpufunc_asm_xscale.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc_asm_xscale.S,v 1.6 2015/01/18 14:55:02 jsg Exp $ */ +/* $OpenBSD: cpufunc_asm_xscale.S,v 1.7 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: cpufunc_asm_xscale.S,v 1.16 2002/08/17 16:36:32 thorpej Exp $ */ /* @@ -129,7 +129,7 @@ ENTRY(xscale_control) */ ENTRY(xscale_setttb) mrs r3, cpsr - orr r1, r3, #(I32_bit | F32_bit) + orr r1, r3, #(PSR_I | PSR_F) msr cpsr_c, r1 stmfd sp!, {r0-r3, lr} @@ -245,7 +245,7 @@ _C_LABEL(xscale_cache_clean_size): #define XSCALE_CACHE_CLEAN_BLOCK \ mrs r3, cpsr ; \ - orr r0, r3, #(I32_bit | F32_bit) ; \ + orr r0, r3, #(PSR_I | PSR_F) ; \ msr cpsr_c, r0 #define XSCALE_CACHE_CLEAN_UNBLOCK \ diff --git a/sys/arch/arm/arm/cpuswitch.S b/sys/arch/arm/arm/cpuswitch.S index 563500d47e6..98e2dbe6969 100644 --- a/sys/arch/arm/arm/cpuswitch.S +++ b/sys/arch/arm/arm/cpuswitch.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cpuswitch.S,v 1.14 2013/09/12 11:43:51 patrick Exp $ */ +/* $OpenBSD: cpuswitch.S,v 1.15 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ /* @@ -95,12 +95,12 @@ */ #define IRQdisableALL \ mrs r14, cpsr ; \ - orr r14, r14, #(I32_bit | F32_bit) ; \ + orr r14, r14, #(PSR_I | PSR_F) ; \ msr cpsr_c, r14 #define IRQenableALL \ mrs r14, cpsr ; \ - bic r14, r14, #(I32_bit | F32_bit) ; \ + bic r14, r14, #(PSR_I | PSR_F) ; \ msr cpsr_c, r14 .text @@ -236,7 +236,7 @@ ENTRY(cpu_switchto) */ mrs r3, cpsr bic r2, r3, #(PSR_MODE) - orr r2, r2, #(PSR_UND32_MODE | I32_bit) + orr r2, r2, #(PSR_UND32_MODE | PSR_I) msr cpsr_c, r2 #ifdef notworthit @@ -489,7 +489,7 @@ ENTRY(proc_trampoline) /* Kill irq's */ mrs r0, cpsr - orr r0, r0, #(I32_bit) + orr r0, r0, #(PSR_I) msr cpsr_c, r0 PULLFRAME diff --git a/sys/arch/arm/arm/cpuswitch7.S b/sys/arch/arm/arm/cpuswitch7.S index 33dbc7fe11d..126b41aa14c 100644 --- a/sys/arch/arm/arm/cpuswitch7.S +++ b/sys/arch/arm/arm/cpuswitch7.S @@ -1,4 +1,4 @@ -/* $OpenBSD: cpuswitch7.S,v 1.3 2013/09/12 11:43:51 patrick Exp $ */ +/* $OpenBSD: cpuswitch7.S,v 1.4 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ /* @@ -95,12 +95,12 @@ */ #define IRQdisableALL \ mrs r14, cpsr ; \ - orr r14, r14, #(I32_bit | F32_bit) ; \ + orr r14, r14, #(PSR_I | PSR_F) ; \ msr cpsr_c, r14 #define IRQenableALL \ mrs r14, cpsr ; \ - bic r14, r14, #(I32_bit | F32_bit) ; \ + bic r14, r14, #(PSR_I | PSR_F) ; \ msr cpsr_c, r14 .text @@ -230,7 +230,7 @@ ENTRY(cpu_switchto) */ mrs r3, cpsr bic r2, r3, #(PSR_MODE) - orr r2, r2, #(PSR_UND32_MODE | I32_bit) + orr r2, r2, #(PSR_UND32_MODE | PSR_I) msr cpsr_c, r2 #ifdef notworthit @@ -434,7 +434,7 @@ ENTRY(proc_trampoline) /* Kill irq's */ mrs r0, cpsr - orr r0, r0, #(I32_bit) + orr r0, r0, #(PSR_I) msr cpsr_c, r0 PULLFRAME diff --git a/sys/arch/arm/arm/fault.c b/sys/arch/arm/arm/fault.c index dad72fba6fe..de7bf69966c 100644 --- a/sys/arch/arm/arm/fault.c +++ b/sys/arch/arm/arm/fault.c @@ -1,4 +1,4 @@ -/* $OpenBSD: fault.c,v 1.18 2014/11/16 12:30:56 deraadt Exp $ */ +/* $OpenBSD: fault.c,v 1.19 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: fault.c,v 1.46 2004/01/21 15:39:21 skrll Exp $ */ /* @@ -221,8 +221,8 @@ data_abort_handler(trapframe_t *tf) uvmexp.traps++; /* Re-enable interrupts if they were enabled previously */ - if (__predict_true((tf->tf_spsr & I32_bit) == 0)) - enable_interrupts(I32_bit); + if (__predict_true((tf->tf_spsr & PSR_I) == 0)) + enable_interrupts(PSR_I); /* Get the current proc structure or proc0 if there is none */ p = (curproc != NULL) ? curproc : &proc0; @@ -665,8 +665,8 @@ prefetch_abort_handler(trapframe_t *tf) * from user mode so we know interrupts were not disabled. * But we check anyway. */ - if (__predict_true((tf->tf_spsr & I32_bit) == 0)) - enable_interrupts(I32_bit); + if (__predict_true((tf->tf_spsr & PSR_I) == 0)) + enable_interrupts(PSR_I); /* Get fault address */ p = curproc; diff --git a/sys/arch/arm/arm/fiq.c b/sys/arch/arm/arm/fiq.c index d0ee0182aee..7201ee5607e 100644 --- a/sys/arch/arm/arm/fiq.c +++ b/sys/arch/arm/arm/fiq.c @@ -1,4 +1,4 @@ -/* $OpenBSD: fiq.c,v 1.6 2014/11/16 12:30:56 deraadt Exp $ */ +/* $OpenBSD: fiq.c,v 1.7 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: fiq.c,v 1.5 2002/04/03 23:33:27 thorpej Exp $ */ /* @@ -48,8 +48,8 @@ TAILQ_HEAD(, fiqhandler) fiqhandler_stack = extern char fiqvector[]; extern char fiq_nullhandler[], fiq_nullhandler_end[]; -#define IRQ_BIT I32_bit -#define FIQ_BIT F32_bit +#define IRQ_BIT PSR_I +#define FIQ_BIT PSR_F /* * fiq_installhandler: diff --git a/sys/arch/arm/arm/locore.S b/sys/arch/arm/arm/locore.S index da97cea1fb6..6fb7b6276d1 100644 --- a/sys/arch/arm/arm/locore.S +++ b/sys/arch/arm/arm/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.7 2015/06/05 05:39:54 jsg Exp $ */ +/* $OpenBSD: locore.S,v 1.8 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */ /* @@ -110,7 +110,7 @@ ENTRY_NP(cpu_reset) mrs r2, cpsr bic r2, r2, #(PSR_MODE) orr r2, r2, #(PSR_SVC32_MODE) - orr r2, r2, #(I32_bit | F32_bit) + orr r2, r2, #(PSR_I | PSR_F) msr cpsr_c, r2 ldr r4, .Lcpu_reset_address diff --git a/sys/arch/arm/arm/pmap.c b/sys/arch/arm/arm/pmap.c index d9a794cbeec..7603fde46ab 100644 --- a/sys/arch/arm/arm/pmap.c +++ b/sys/arch/arm/arm/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.56 2015/09/08 21:28:36 kettenis Exp $ */ +/* $OpenBSD: pmap.c,v 1.57 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $ */ /* @@ -2858,7 +2858,7 @@ pmap_activate(struct proc *p) } s = splhigh(); - disable_interrupts(I32_bit | F32_bit); + disable_interrupts(PSR_I | PSR_F); /* * We MUST, I repeat, MUST fix up the L1 entry corresponding @@ -2878,7 +2878,7 @@ pmap_activate(struct proc *p) cpu_domains(pcb->pcb_dacr); cpu_setttb(pcb->pcb_pagedir); - enable_interrupts(I32_bit | F32_bit); + enable_interrupts(PSR_I | PSR_F); /* * Flag any previous userland pmap as being NOT @@ -2989,11 +2989,11 @@ pmap_destroy(pmap_t pm) * number. This will ensure pmap_remove() does not * pull the current vector page out from under us. */ - disable_interrupts(I32_bit | F32_bit); + disable_interrupts(PSR_I | PSR_F); *pcb->pcb_pl1vec = pcb->pcb_l1vec; cpu_domains(pcb->pcb_dacr); cpu_setttb(pcb->pcb_pagedir); - enable_interrupts(I32_bit | F32_bit); + enable_interrupts(PSR_I | PSR_F); } /* Remove the vector page mapping */ diff --git a/sys/arch/arm/arm/pmap7.c b/sys/arch/arm/arm/pmap7.c index ee771e92609..4ee104bda2b 100644 --- a/sys/arch/arm/arm/pmap7.c +++ b/sys/arch/arm/arm/pmap7.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap7.c,v 1.21 2015/09/08 21:28:36 kettenis Exp $ */ +/* $OpenBSD: pmap7.c,v 1.22 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $ */ /* @@ -2177,7 +2177,7 @@ pmap_activate(struct proc *p) } s = splhigh(); - disable_interrupts(I32_bit | F32_bit); + disable_interrupts(PSR_I | PSR_F); /* * We MUST, I repeat, MUST fix up the L1 entry corresponding @@ -2197,7 +2197,7 @@ pmap_activate(struct proc *p) cpu_domains(pcb->pcb_dacr); cpu_setttb(pcb->pcb_pagedir); - enable_interrupts(I32_bit | F32_bit); + enable_interrupts(PSR_I | PSR_F); splx(s); } diff --git a/sys/arch/arm/arm/process_machdep.c b/sys/arch/arm/arm/process_machdep.c index 90de0e298a0..fd15facb547 100644 --- a/sys/arch/arm/arm/process_machdep.c +++ b/sys/arch/arm/arm/process_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: process_machdep.c,v 1.4 2011/09/20 22:02:11 miod Exp $ */ +/* $OpenBSD: process_machdep.c,v 1.5 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: process_machdep.c,v 1.11 2003/08/07 16:26:52 agc Exp $ */ /* @@ -135,7 +135,7 @@ process_read_regs(struct proc *p, struct reg *regs) #ifdef DIAGNOSTIC if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE - && tf->tf_spsr & I32_bit) + && tf->tf_spsr & PSR_I) panic("process_read_regs: Interrupts blocked in user process"); #endif @@ -166,7 +166,7 @@ process_write_regs(struct proc *p, struct reg *regs) tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS; #ifdef DIAGNOSTIC if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE - && tf->tf_spsr & I32_bit) + && tf->tf_spsr & PSR_I) panic("process_write_regs: Interrupts blocked in user process"); #endif diff --git a/sys/arch/arm/arm/sig_machdep.c b/sys/arch/arm/arm/sig_machdep.c index 77f19178d33..abd1bd494a3 100644 --- a/sys/arch/arm/arm/sig_machdep.c +++ b/sys/arch/arm/arm/sig_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sig_machdep.c,v 1.11 2014/03/26 05:23:42 guenther Exp $ */ +/* $OpenBSD: sig_machdep.c,v 1.12 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: sig_machdep.c,v 1.22 2003/10/08 00:28:41 thorpej Exp $ */ /* @@ -205,7 +205,7 @@ sys_sigreturn(struct proc *p, void *v, register_t *retval) * interrupts have not been disabled. */ if ((context.sc_spsr & PSR_MODE) != PSR_USR32_MODE || - (context.sc_spsr & (I32_bit | F32_bit)) != 0) + (context.sc_spsr & (PSR_I | PSR_F)) != 0) return (EINVAL); /* Restore register context. */ diff --git a/sys/arch/arm/arm/syscall.c b/sys/arch/arm/arm/syscall.c index 302a2b01baf..7ffa07e22bb 100644 --- a/sys/arch/arm/arm/syscall.c +++ b/sys/arch/arm/arm/syscall.c @@ -1,4 +1,4 @@ -/* $OpenBSD: syscall.c,v 1.17 2014/05/11 00:05:38 guenther Exp $ */ +/* $OpenBSD: syscall.c,v 1.18 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: syscall.c,v 1.24 2003/11/14 19:03:17 scw Exp $ */ /*- @@ -104,8 +104,8 @@ swi_handler(trapframe_t *frame) uvmexp.syscalls++; /* Re-enable interrupts if they were enabled previously */ - if (__predict_true((frame->tf_spsr & I32_bit) == 0)) - enable_interrupts(I32_bit); + if (__predict_true((frame->tf_spsr & PSR_I) == 0)) + enable_interrupts(PSR_I); p->p_addr->u_pcb.pcb_tf = frame; @@ -153,7 +153,7 @@ swi_handler(trapframe_t *frame) frame->tf_r0 = rval[0]; frame->tf_r1 = rval[1]; - frame->tf_spsr &= ~PSR_C_bit; /* carry bit */ + frame->tf_spsr &= ~PSR_C; /* carry bit */ break; case ERESTART: @@ -170,7 +170,7 @@ swi_handler(trapframe_t *frame) default: bad: frame->tf_r0 = error; - frame->tf_spsr |= PSR_C_bit; /* carry bit */ + frame->tf_spsr |= PSR_C; /* carry bit */ break; } @@ -185,7 +185,7 @@ child_return(arg) struct trapframe *frame = p->p_addr->u_pcb.pcb_tf; frame->tf_r0 = 0; - frame->tf_spsr &= ~PSR_C_bit; /* carry bit */ + frame->tf_spsr &= ~PSR_C; /* carry bit */ mi_child_return(p); } diff --git a/sys/arch/arm/arm/undefined.c b/sys/arch/arm/arm/undefined.c index 23ef6539c0c..5ec5b4f0c17 100644 --- a/sys/arch/arm/arm/undefined.c +++ b/sys/arch/arm/arm/undefined.c @@ -1,4 +1,4 @@ -/* $OpenBSD: undefined.c,v 1.6 2014/07/12 18:44:41 tedu Exp $ */ +/* $OpenBSD: undefined.c,v 1.7 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: undefined.c,v 1.22 2003/11/29 22:21:29 bjh21 Exp $ */ /* @@ -154,8 +154,8 @@ undefinedinstruction(trapframe_t *frame) union sigval sv; /* Enable interrupts if they were enabled before the exception. */ - if (!(frame->tf_spsr & I32_bit)) - enable_interrupts(I32_bit); + if (!(frame->tf_spsr & PSR_I)) + enable_interrupts(PSR_I); frame->tf_pc -= INSN_SIZE; fault_pc = frame->tf_pc; diff --git a/sys/arch/arm/cortex/ampintc.c b/sys/arch/arm/cortex/ampintc.c index fb8daabc5a2..774b909b537 100644 --- a/sys/arch/arm/cortex/ampintc.c +++ b/sys/arch/arm/cortex/ampintc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ampintc.c,v 1.8 2015/11/05 19:54:17 miod Exp $ */ +/* $OpenBSD: ampintc.c,v 1.9 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2007,2009,2011 Dale Rahn <drahn@openbsd.org> * @@ -298,7 +298,7 @@ ampintc_attach(struct device *parent, struct device *self, void *args) /* enable interrupts */ bus_space_write_4(iot, d_ioh, ICD_DCR, 3); bus_space_write_4(iot, p_ioh, ICPICR, 1); - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); } void @@ -325,7 +325,7 @@ ampintc_setipl(int new) int psw; /* disable here is only to keep hardware in sync with ci->ci_cpl */ - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); ci->ci_cpl = new; /* low values are higher priority thus IPL_HIGH - pri */ @@ -555,7 +555,7 @@ ampintc_intr_establish(int irqno, int level, int (*func)(void *), ih->ih_irq = irqno; ih->ih_name = name; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); TAILQ_INSERT_TAIL(&sc->sc_ampintc_handler[irqno].iq_list, ih, ih_list); @@ -579,7 +579,7 @@ ampintc_intr_disestablish(void *cookie) int psw; struct intrhand *ih = cookie; int irqno = ih->ih_irq; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); TAILQ_REMOVE(&sc->sc_ampintc_handler[irqno].iq_list, ih, ih_list); if (ih->ih_name != NULL) evcount_detach(&ih->ih_count); diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h index 203b1c84c11..4cdbfcdcc7a 100644 --- a/sys/arch/arm/include/armreg.h +++ b/sys/arch/arm/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.17 2016/01/23 15:38:48 jsg Exp $ */ +/* $OpenBSD: armreg.h,v 1.18 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ /* @@ -63,19 +63,19 @@ */ #define PSR_FLAGS 0xf0000000 /* flags */ -#define PSR_N_bit (1U << 31) /* negative */ -#define PSR_Z_bit (1 << 30) /* zero */ -#define PSR_C_bit (1 << 29) /* carry */ -#define PSR_V_bit (1 << 28) /* overflow */ +#define PSR_N (1U << 31) /* negative */ +#define PSR_Z (1 << 30) /* zero */ +#define PSR_C (1 << 29) /* carry */ +#define PSR_V (1 << 28) /* overflow */ -#define PSR_Q_bit (1 << 27) /* saturation */ +#define PSR_Q (1 << 27) /* saturation */ -#define A32_bit (1 << 8) /* Asynchronous abort disable */ -#define I32_bit (1 << 7) /* IRQ disable */ -#define F32_bit (1 << 6) /* FIQ disable */ +#define PSR_A (1 << 8) /* Asynchronous abort disable */ +#define PSR_I (1 << 7) /* IRQ disable */ +#define PSR_F (1 << 6) /* FIQ disable */ -#define PSR_T_bit (1 << 5) /* Thumb state */ -#define PSR_J_bit (1 << 24) /* Java mode */ +#define PSR_T (1 << 5) /* Thumb state */ +#define PSR_J (1 << 24) /* Java mode */ #define PSR_MODE 0x0000001f /* mode mask */ #define PSR_USR26_MODE 0x00000000 diff --git a/sys/arch/arm/include/atomic.h b/sys/arch/arm/include/atomic.h index c31d91af207..a57d0f49808 100644 --- a/sys/arch/arm/include/atomic.h +++ b/sys/arch/arm/include/atomic.h @@ -1,4 +1,4 @@ -/* $OpenBSD: atomic.h,v 1.12 2015/09/12 16:12:50 miod Exp $ */ +/* $OpenBSD: atomic.h,v 1.13 2016/01/31 00:14:50 jsg Exp $ */ /* Public Domain */ @@ -25,7 +25,7 @@ _atomic_cas_uint(volatile unsigned int *uip, unsigned int o, unsigned int n) unsigned int cpsr; unsigned int rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip; if (rv == o) *uip = n; @@ -41,7 +41,7 @@ _atomic_cas_ulong(volatile unsigned long *uip, unsigned long o, unsigned long n) unsigned int cpsr; unsigned long rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip; if (rv == o) *uip = n; @@ -58,7 +58,7 @@ _atomic_cas_ptr(volatile void *uip, void *o, void *n) void * volatile *uipp = (void * volatile *)uip; void *rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uipp; if (rv == o) *uipp = n; @@ -74,7 +74,7 @@ _atomic_swap_uint(volatile unsigned int *uip, unsigned int n) unsigned int cpsr; unsigned int rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip; *uip = n; restore_interrupts(cpsr); @@ -89,7 +89,7 @@ _atomic_swap_ulong(volatile unsigned long *uip, unsigned long n) unsigned int cpsr; unsigned long rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip; *uip = n; restore_interrupts(cpsr); @@ -105,7 +105,7 @@ _atomic_swap_ptr(volatile void *uip, void *n) void * volatile *uipp = (void * volatile *)uip; void *rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uipp; *uipp = n; restore_interrupts(cpsr); @@ -120,7 +120,7 @@ _atomic_add_int_nv(volatile unsigned int *uip, unsigned int v) unsigned int cpsr; unsigned int rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip + v; *uip = rv; restore_interrupts(cpsr); @@ -135,7 +135,7 @@ _atomic_add_long_nv(volatile unsigned long *uip, unsigned long v) unsigned int cpsr; unsigned long rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip + v; *uip = rv; restore_interrupts(cpsr); @@ -150,7 +150,7 @@ _atomic_sub_int_nv(volatile unsigned int *uip, unsigned int v) unsigned int cpsr; unsigned int rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip - v; *uip = rv; restore_interrupts(cpsr); @@ -165,7 +165,7 @@ _atomic_sub_long_nv(volatile unsigned long *uip, unsigned long v) unsigned int cpsr; unsigned long rv; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); rv = *uip - v; *uip = rv; restore_interrupts(cpsr); @@ -179,7 +179,7 @@ atomic_setbits_int(volatile unsigned int *uip, unsigned int v) { unsigned int cpsr; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); *uip |= v; restore_interrupts(cpsr); } @@ -189,7 +189,7 @@ atomic_clearbits_int(volatile unsigned int *uip, unsigned int v) { unsigned int cpsr; - cpsr = disable_interrupts(I32_bit|F32_bit); + cpsr = disable_interrupts(PSR_I|PSR_F); *uip &= ~v; restore_interrupts(cpsr); } diff --git a/sys/arch/arm/include/cpu.h b/sys/arch/arm/include/cpu.h index f00363cac0c..25879915982 100644 --- a/sys/arch/arm/include/cpu.h +++ b/sys/arch/arm/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.39 2014/07/11 10:53:07 uebayasi Exp $ */ +/* $OpenBSD: cpu.h,v 1.40 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: cpu.h,v 1.34 2003/06/23 11:01:08 martin Exp $ */ /* @@ -112,20 +112,20 @@ extern int cpu_do_powersave; #define IRQdisable \ stmfd sp!, {r0} ; \ mrs r0, cpsr ; \ - orr r0, r0, #(I32_bit) ; \ + orr r0, r0, #(PSR_I) ; \ msr cpsr_c, r0 ; \ ldmfd sp!, {r0} #define IRQenable \ stmfd sp!, {r0} ; \ mrs r0, cpsr ; \ - bic r0, r0, #(I32_bit) ; \ + bic r0, r0, #(PSR_I) ; \ msr cpsr_c, r0 ; \ ldmfd sp!, {r0} #else -#define IRQdisable __set_cpsr_c(I32_bit, I32_bit); -#define IRQenable __set_cpsr_c(I32_bit, 0); +#define IRQdisable __set_cpsr_c(PSR_I, PSR_I); +#define IRQenable __set_cpsr_c(PSR_I, 0); #endif /* _LOCORE */ #ifndef _LOCORE diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h index 43753ac52ab..9de47c4d725 100644 --- a/sys/arch/arm/include/cpufunc.h +++ b/sys/arch/arm/include/cpufunc.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpufunc.h,v 1.15 2014/03/29 18:09:28 guenther Exp $ */ +/* $OpenBSD: cpufunc.h,v 1.16 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ /* @@ -501,14 +501,14 @@ __get_cpsr() } #define disable_interrupts(mask) \ - (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ - (mask) & (I32_bit | F32_bit))) + (__set_cpsr_c((mask) & (PSR_I | PSR_F), \ + (mask) & (PSR_I | PSR_F))) #define enable_interrupts(mask) \ - (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) + (__set_cpsr_c((mask) & (PSR_I | PSR_F), 0)) #define restore_interrupts(old_cpsr) \ - (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) + (__set_cpsr_c((PSR_I | PSR_F), (old_cpsr) & (PSR_I | PSR_F))) /* * Functions to manipulate cpu r13 diff --git a/sys/arch/arm/include/frame.h b/sys/arch/arm/include/frame.h index 9f2adffef58..31b2936a865 100644 --- a/sys/arch/arm/include/frame.h +++ b/sys/arch/arm/include/frame.h @@ -1,4 +1,4 @@ -/* $OpenBSD: frame.h,v 1.6 2015/01/18 16:26:39 jsg Exp $ */ +/* $OpenBSD: frame.h,v 1.7 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: frame.h,v 1.9 2003/12/01 08:48:33 scw Exp $ */ /* @@ -176,8 +176,8 @@ struct frame { teq r0, #(PSR_USR32_MODE) ;\ ldreq r5, .Laflt_astpending ;\ bne 2f /* Nope, get out now */ ;\ - bic r4, r4, #(I32_bit) ;\ -1: orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ + bic r4, r4, #(PSR_I) ;\ +1: orr r0, r4, #(PSR_I) /* Disable IRQs */ ;\ msr cpsr_c, r0 ;\ ldr r1, [r5] /* Pending AST? */ ;\ teq r1, #0x00000000 ;\ diff --git a/sys/arch/arm/sa11x0/sa11x0_ost.c b/sys/arch/arm/sa11x0/sa11x0_ost.c index 3f566aa20bc..1741972a647 100644 --- a/sys/arch/arm/sa11x0/sa11x0_ost.c +++ b/sys/arch/arm/sa11x0/sa11x0_ost.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sa11x0_ost.c,v 1.8 2008/05/15 22:17:08 brad Exp $ */ +/* $OpenBSD: sa11x0_ost.c,v 1.9 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: sa11x0_ost.c,v 1.11 2003/07/15 00:24:51 lukem Exp $ */ /* @@ -271,7 +271,7 @@ gettick() { int counter; u_int savedints; - savedints = disable_interrupts(I32_bit); + savedints = disable_interrupts(PSR_I); counter = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_CR); diff --git a/sys/arch/arm/xscale/i80321_clock.c b/sys/arch/arm/xscale/i80321_clock.c index 1df195b3423..1417b089992 100644 --- a/sys/arch/arm/xscale/i80321_clock.c +++ b/sys/arch/arm/xscale/i80321_clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: i80321_clock.c,v 1.10 2015/06/13 07:16:36 jsg Exp $ */ +/* $OpenBSD: i80321_clock.c,v 1.11 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2006 Dale Rahn <drahn@openbsd.org> @@ -285,7 +285,7 @@ cpu_initclocks() int new_tps; int tps_diff; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); first_sec = rtctime.tv_sec; do { diff --git a/sys/arch/arm/xscale/i80321_intr.c b/sys/arch/arm/xscale/i80321_intr.c index 0f829563f6d..d77944d6891 100644 --- a/sys/arch/arm/xscale/i80321_intr.c +++ b/sys/arch/arm/xscale/i80321_intr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: i80321_intr.c,v 1.16 2014/04/03 10:17:34 mpi Exp $ */ +/* $OpenBSD: i80321_intr.c,v 1.17 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2006 Dale Rahn <drahn@openbsd.org> @@ -104,7 +104,7 @@ i80321intc_setipl(int new) { int psw; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); current_ipl_level = new; i80321intc_write_intctl(i80321intc_imask[new]); restore_interrupts(psw); @@ -177,7 +177,7 @@ i80321intc_do_pending(void) static int processing = 0; int oldirqstate, spl_save; - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); spl_save = current_ipl_level; @@ -194,7 +194,7 @@ i80321intc_do_pending(void) i80321intc_setipl(ipl); \ restore_interrupts(oldirqstate); \ softintr_dispatch(si); \ - oldirqstate = disable_interrupts(I32_bit); \ + oldirqstate = disable_interrupts(PSR_I); \ i80321intc_setipl(spl_save); \ } @@ -253,7 +253,7 @@ _setsoftintr(int si) { int oldirqstate; - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); softint_pending |= SI_TO_IRQBIT(si); restore_interrupts(oldirqstate); @@ -296,7 +296,7 @@ i80321intc_init(void) i80321intc_calc_mask(); /* Enable IRQs (don't yet use FIQs). */ - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); } void * @@ -328,7 +328,7 @@ i80321_intr_establish(int irq, int ipl, int (*func)(void *), void *arg, /* All IOP321 interrupts are level-triggered. */ iq->iq_ist = IST_LEVEL; - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); @@ -347,7 +347,7 @@ i80321_intr_disestablish(void *cookie) struct intrq *iq = &i80321_handler[ih->ih_irq]; int oldirqstate; - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); TAILQ_REMOVE(&iq->iq_list, ih, ih_list); if (ih->ih_name != NULL) @@ -380,14 +380,14 @@ i80321_irq_handler(void *arg) i80321intc_setipl(i80321_handler[irq].iq_irq); /* Enable interrupt */ - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); TAILQ_FOREACH(ih, &i80321_handler[irq].iq_list, ih_list) { if ((ih->ih_func)( ih->ih_arg == 0 ? frame : ih->ih_arg)) ih->ih_count.ec_count++; } /* Disable interrupt */ - disable_interrupts(I32_bit); + disable_interrupts(PSR_I); hwpend &= ~(1<<irq); } uvmexp.intrs++; diff --git a/sys/arch/arm/xscale/i80321_pci.c b/sys/arch/arm/xscale/i80321_pci.c index a1c33ecf8bf..cf2ce32f62f 100644 --- a/sys/arch/arm/xscale/i80321_pci.c +++ b/sys/arch/arm/xscale/i80321_pci.c @@ -1,4 +1,4 @@ -/* $OpenBSD: i80321_pci.c,v 1.4 2010/12/04 17:06:31 miod Exp $ */ +/* $OpenBSD: i80321_pci.c,v 1.5 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: i80321_pci.c,v 1.7 2005/12/15 01:44:00 briggs Exp $ */ /* @@ -67,7 +67,7 @@ int i80321_pci_conf_size(void *, pcitag_t); pcireg_t i80321_pci_conf_read(void *, pcitag_t, int); void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t); -#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit) +#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I) #define PCI_CONF_UNLOCK(s) restore_interrupts((s)) void diff --git a/sys/arch/arm/xscale/pxa2x0.c b/sys/arch/arm/xscale/pxa2x0.c index e550efb2cff..baefb42bf37 100644 --- a/sys/arch/arm/xscale/pxa2x0.c +++ b/sys/arch/arm/xscale/pxa2x0.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pxa2x0.c,v 1.19 2014/10/18 12:21:56 miod Exp $ */ +/* $OpenBSD: pxa2x0.c,v 1.20 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: pxa2x0.c,v 1.5 2003/12/12 16:42:44 thorpej Exp $ */ /* @@ -285,7 +285,7 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc) int irq; ioh = sc->sc_bush_rtc; - irq = disable_interrupts(I32_bit|F32_bit); + irq = disable_interrupts(PSR_I|PSR_F); __asm volatile( "mrc p14, 0, %0, c0, c1, 0" : "=r" (pmcr_save)); /* Enable clock counter */ diff --git a/sys/arch/arm/xscale/pxa2x0_apm.c b/sys/arch/arm/xscale/pxa2x0_apm.c index 71561fed1be..10dc039297f 100644 --- a/sys/arch/arm/xscale/pxa2x0_apm.c +++ b/sys/arch/arm/xscale/pxa2x0_apm.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pxa2x0_apm.c,v 1.43 2014/09/20 09:28:24 kettenis Exp $ */ +/* $OpenBSD: pxa2x0_apm.c,v 1.44 2016/01/31 00:14:50 jsg Exp $ */ /*- * Copyright (c) 2001 Alexander Guy. All rights reserved. @@ -900,7 +900,7 @@ pxa2x0_apm_sleep(struct pxa2x0_apm_softc *sc) goto out; } - save = disable_interrupts(I32_bit|F32_bit); + save = disable_interrupts(PSR_I|PSR_F); sd.sd_oscr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR0); sd.sd_oscr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR4); @@ -1483,7 +1483,7 @@ pxa2x0_setperf(int speed) DPRINTF(("setperf speed %d newfreq %d, maxfreq %d\n", speed, newfreq, xscale_maxspeed)); - s = disable_interrupts(I32_bit|F32_bit); + s = disable_interrupts(PSR_I|PSR_F); if (newfreq == 91) { if (freq > 91) { diff --git a/sys/arch/arm/xscale/pxa2x0_apm_asm.S b/sys/arch/arm/xscale/pxa2x0_apm_asm.S index 72caf0d2b85..83907fea32d 100644 --- a/sys/arch/arm/xscale/pxa2x0_apm_asm.S +++ b/sys/arch/arm/xscale/pxa2x0_apm_asm.S @@ -1,4 +1,4 @@ -/* $OpenBSD: pxa2x0_apm_asm.S,v 1.4 2007/11/02 05:18:25 miod Exp $ */ +/* $OpenBSD: pxa2x0_apm_asm.S,v 1.5 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2005 Uwe Stuehler <uwe@openbsd.org> @@ -166,31 +166,31 @@ ENTRY(pxa2x0_cpu_suspend) str r2, [r3], #4 /* Save SVC saved CPSR. */ str sp, [r3], #4 /* Save SVC stack pointer. */ - mov r1, #(PSR_FIQ32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_FIQ32_MODE | PSR_I | PSR_F) msr cpsr, r1 /* Enter FIQ mode. */ mrs r2, spsr /* Load FIQ mode saved CPSR. */ stmia r3!, {r2, r8-r12, sp, lr} /* Save FIQ mode registers. */ - mov r1, #(PSR_IRQ32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_IRQ32_MODE | PSR_I | PSR_F) msr cpsr, r1 /* Enter IRQ mode. */ mrs r0, spsr /* Load IRQ mode saved CPSR. */ stmia r3!, {r0, sp, lr} /* Save IRQ mode registers. */ - mov r1, #(PSR_ABT32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_ABT32_MODE | PSR_I | PSR_F) msr cpsr, r1 /* Enter ABT mode. */ mrs r0, spsr /* Load ABT mode saved CPSR. */ stmia r3!, {r0, sp, lr} /* Save ABT mode registers. */ - mov r1, #(PSR_UND32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_UND32_MODE | PSR_I | PSR_F) msr cpsr, r1 /* Enter UND mode. */ mrs r0, spsr /* Load UND mode saved CPSR. */ stmia r3!, {r0, sp, lr} /* Save UND mode registers. */ - mov r1, #(PSR_SYS32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_SYS32_MODE | PSR_I | PSR_F) msr cpsr, r1 /* Enter SYS mode. */ stmia r3!, {sp, lr} /* Save SYS mode registers. */ - mov r1, #(PSR_SVC32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_SVC32_MODE | PSR_I | PSR_F) msr cpsr, r1 /* Return to SVC mode. */ /* At this point all critical registers have been saved. */ @@ -211,14 +211,14 @@ ENTRY(pxa2x0_cpu_suspend) cache_flush_loop: mrs r2, cpsr - orr r2, r2, #(I32_bit|F32_bit) + orr r2, r2, #(PSR_I|PSR_F) msr cpsr_c, r2 /* disable IRQ/FIQ */ mcr p15, 0, r0, c7, c2, 5 /* allocate cache line */ mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ mrs r2, cpsr - and r2, r2, #~(I32_bit|F32_bit) + and r2, r2, #~(PSR_I|PSR_F) msr cpsr_c, r2 /* enable IRQ/FIQ */ add r0, r0, #CACHELINESIZE @@ -329,7 +329,7 @@ pxa2x0_cpu_resume_virt: ldr sp, [r2], #4 /* Restore FIQ mode registers. */ - mov r1, #(PSR_FIQ32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_FIQ32_MODE | PSR_I | PSR_F) msr cpsr, r1 ldr r0, [r2], #4 msr spsr, r0 @@ -342,7 +342,7 @@ pxa2x0_cpu_resume_virt: ldr lr, [r2], #4 /* Restore IRQ mode registers. */ - mov r1, #(PSR_IRQ32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_IRQ32_MODE | PSR_I | PSR_F) msr cpsr, r1 ldr r0, [r2], #4 msr spsr, r0 @@ -350,7 +350,7 @@ pxa2x0_cpu_resume_virt: ldr lr, [r2], #4 /* Restore ABT mode registers. */ - mov r1, #(PSR_ABT32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_ABT32_MODE | PSR_I | PSR_F) msr cpsr, r1 ldr r0, [r2], #4 msr spsr, r0 @@ -358,7 +358,7 @@ pxa2x0_cpu_resume_virt: ldr lr, [r2], #4 /* Restore UND mode registers. */ - mov r1, #(PSR_UND32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_UND32_MODE | PSR_I | PSR_F) msr cpsr, r1 ldr r0, [r2], #4 msr spsr, r0 @@ -366,13 +366,13 @@ pxa2x0_cpu_resume_virt: ldr lr, [r2], #4 /* Restore SYS mode registers. */ - mov r1, #(PSR_SYS32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_SYS32_MODE | PSR_I | PSR_F) msr cpsr, r1 ldr sp, [r2], #4 ldr lr, [r2], #4 /* Return to SVC mode. */ - mov r1, #(PSR_SVC32_MODE | I32_bit | F32_bit) + mov r1, #(PSR_SVC32_MODE | PSR_I | PSR_F) msr cpsr, r1 ldmia sp!, {r0-r12, pc} diff --git a/sys/arch/arm/xscale/pxa2x0_gpio.c b/sys/arch/arm/xscale/pxa2x0_gpio.c index 2cc410a10f4..5c86d1425af 100644 --- a/sys/arch/arm/xscale/pxa2x0_gpio.c +++ b/sys/arch/arm/xscale/pxa2x0_gpio.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pxa2x0_gpio.c,v 1.24 2014/07/12 18:44:41 tedu Exp $ */ +/* $OpenBSD: pxa2x0_gpio.c,v 1.25 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: pxa2x0_gpio.c,v 1.2 2003/07/15 00:24:55 lukem Exp $ */ /* @@ -338,7 +338,7 @@ void pxa2x0_gpio_intr_fixup(int minipl, int maxipl) { struct pxagpio_softc *sc = pxagpio_softc; - int save = disable_interrupts(I32_bit); + int save = disable_interrupts(PSR_I); if (maxipl == IPL_NONE && minipl == IPL_HIGH) { /* no remaining interrupts */ diff --git a/sys/arch/arm/xscale/pxa2x0_intr.c b/sys/arch/arm/xscale/pxa2x0_intr.c index 72d41a3f2b5..0743c9643e5 100644 --- a/sys/arch/arm/xscale/pxa2x0_intr.c +++ b/sys/arch/arm/xscale/pxa2x0_intr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pxa2x0_intr.c,v 1.26 2014/07/12 18:44:41 tedu Exp $ */ +/* $OpenBSD: pxa2x0_intr.c,v 1.27 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $ */ /* @@ -158,7 +158,7 @@ pxaintc_attach(struct device *parent, struct device *self, void *args) pxa2x0_init_interrupt_masks(); _splraise(IPL_HIGH); - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); } /* @@ -219,7 +219,7 @@ pxa2x0_irq_handler(void *arg) pxa2x0_setipl(extirq_level[irqno]); /* Enable interrupt */ - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ (* handler[irqno].func)( @@ -235,7 +235,7 @@ pxa2x0_irq_handler(void *arg) #endif /* Disable interrupt */ - disable_interrupts(I32_bit); + disable_interrupts(PSR_I); irqbits &= ~(1<<irqno); } @@ -254,7 +254,7 @@ pxa2x0_stray_interrupt(void *cookie) printf("stray interrupt %d\n", irqno); if (PXA2X0_IRQ_MIN <= irqno && irqno < ICU_LEN){ - int save = disable_interrupts(I32_bit); + int save = disable_interrupts(PSR_I); write_icu(SAIPIC_MR, read_icu(SAIPIC_MR) & ~(1U<<irqno)); restore_interrupts(save); @@ -289,7 +289,7 @@ pxa2x0_update_intr_masks(int irqno, int irqlevel) int level; #endif struct intrhand *ih; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); /* First figure out which levels each IRQ uses. */ for (irq = 0; irq < ICU_LEN; irq++) { @@ -339,7 +339,7 @@ pxa2x0_update_intr_masks(int irqno, int irqlevel) int level; /* debug */ int mask = 1U<<irqno; int i; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); for(i = 0; i < irqlevel; ++i) pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */ @@ -456,7 +456,7 @@ pxa2x0_do_pending(void) spl_save = current_spl_level; - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); #if 1 #define DO_SOFTINT(si,ipl) \ @@ -467,7 +467,7 @@ pxa2x0_do_pending(void) pxa2x0_setipl(ipl); \ restore_interrupts(oldirqstate); \ softintr_dispatch(si); \ - oldirqstate = disable_interrupts(I32_bit); \ + oldirqstate = disable_interrupts(PSR_I); \ pxa2x0_setipl(spl_save); \ } @@ -484,7 +484,7 @@ pxa2x0_do_pending(void) pxa2x0_setipl(ipl); restore_interrupts(oldirqstate); softintr_dispatch(si); - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); pxa2x0_setipl(spl_save); } #endif @@ -541,7 +541,7 @@ pxa2x0_intr_establish(int irqno, int level, if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN) panic("intr_establish: bogus irq number %d", irqno); - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ /* no point in sleeping unless someone can free memory. */ @@ -587,7 +587,7 @@ pxa2x0_intr_disestablish(void *cookie) struct intrhand *ih = cookie; int irqno = ih->ih_irq; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); TAILQ_REMOVE(&handler[irqno].list, ih, ih_list); free(ih, M_DEVBUF, 0); @@ -605,7 +605,7 @@ pxa2x0_intr_disestablish(void *cookie) if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN) panic("intr_disestablish: bogus irq number %d", irqno); - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); ih = &handler[irqno]; if (ih->name != NULL) @@ -648,7 +648,7 @@ pxa2x0_splx(int new) { int psw; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); pxa2x0_setipl(new); restore_interrupts(psw); @@ -665,7 +665,7 @@ pxa2x0_splraise(int ipl) old = current_spl_level; if( ipl > current_spl_level ){ - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); pxa2x0_setipl(ipl); restore_interrupts(psw); } @@ -677,7 +677,7 @@ int pxa2x0_spllower(int ipl) { int old = current_spl_level; - int psw = disable_interrupts(I32_bit); + int psw = disable_interrupts(PSR_I); pxa2x0_splx(ipl); restore_interrupts(psw); return(old); @@ -723,7 +723,7 @@ pxa2x0_splassert_check(int wantipl, const char *func) * If the splassert_ctl is set to not panic, raise the ipl * in a feeble attempt to reduce damage. */ - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); pxa2x0_setipl(wantipl); restore_interrupts(psw); } diff --git a/sys/arch/arm/xscale/pxa2x0_lcd.c b/sys/arch/arm/xscale/pxa2x0_lcd.c index 119782c61d3..9238889c8e4 100644 --- a/sys/arch/arm/xscale/pxa2x0_lcd.c +++ b/sys/arch/arm/xscale/pxa2x0_lcd.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pxa2x0_lcd.c,v 1.26 2014/07/12 18:44:41 tedu Exp $ */ +/* $OpenBSD: pxa2x0_lcd.c,v 1.27 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: pxa2x0_lcd.c,v 1.8 2003/10/03 07:24:05 bsh Exp $ */ /* @@ -292,7 +292,7 @@ pxa2x0_lcd_start_dma(bus_space_tag_t iot, bus_space_handle_t ioh, uint32_t tmp; int val, save; - save = disable_interrupts(I32_bit); + save = disable_interrupts(PSR_I); switch (scr->depth) { case 1: val = 0; break; diff --git a/sys/arch/armv7/armv7/armv7_start.S b/sys/arch/armv7/armv7/armv7_start.S index d745e962fc8..6ec8ef6280c 100644 --- a/sys/arch/armv7/armv7/armv7_start.S +++ b/sys/arch/armv7/armv7/armv7_start.S @@ -1,4 +1,4 @@ -/* $OpenBSD: armv7_start.S,v 1.4 2016/01/23 15:38:48 jsg Exp $ */ +/* $OpenBSD: armv7_start.S,v 1.5 2016/01/31 00:14:50 jsg Exp $ */ /* $NetBSD: lubbock_start.S,v 1.1 2003/06/18 10:51:15 bsh Exp $ */ /* @@ -102,7 +102,7 @@ _C_LABEL(bootstrap_start): mrs r0, cpsr bic r0, r0, #(PSR_MODE) orr r0, r0, #(PSR_SVC32_MODE) - orr r0, r0, #(I32_bit | F32_bit | A32_bit) + orr r0, r0, #(PSR_I | PSR_F | PSR_A) msr spsr_fsxc, r0 adr lr, 1f ELR diff --git a/sys/arch/armv7/armv7/intr.c b/sys/arch/armv7/armv7/intr.c index b481375baaf..b096bed7542 100644 --- a/sys/arch/armv7/armv7/intr.c +++ b/sys/arch/armv7/armv7/intr.c @@ -1,4 +1,4 @@ -/* $OpenBSD: intr.c,v 1.3 2015/06/13 07:16:37 jsg Exp $ */ +/* $OpenBSD: intr.c,v 1.4 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2011 Dale Rahn <drahn@openbsd.org> * @@ -151,7 +151,7 @@ arm_setsoftintr(int si) int oldirqstate; /* XXX atomic? */ - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); ci->ci_ipending |= SI_TO_IRQBIT(si); restore_interrupts(oldirqstate); @@ -168,7 +168,7 @@ arm_do_pending_intr(int pcpl) static int processing = 0; int oldirqstate; - oldirqstate = disable_interrupts(I32_bit); + oldirqstate = disable_interrupts(PSR_I); if (processing == 1) { /* Don't use splx... we are here already! */ @@ -184,7 +184,7 @@ arm_do_pending_intr(int pcpl) arm_intr_func.setipl(ipl); \ restore_interrupts(oldirqstate); \ softintr_dispatch(si); \ - oldirqstate = disable_interrupts(I32_bit); \ + oldirqstate = disable_interrupts(PSR_I); \ } do { diff --git a/sys/arch/armv7/omap/intc.c b/sys/arch/armv7/omap/intc.c index 8c662a70f05..335f9e6794d 100644 --- a/sys/arch/armv7/omap/intc.c +++ b/sys/arch/armv7/omap/intc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: intc.c,v 1.3 2014/07/12 18:44:41 tedu Exp $ */ +/* $OpenBSD: intc.c,v 1.4 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org> * @@ -170,7 +170,7 @@ intc_attach(struct device *parent, struct device *self, void *args) intc_irq_handler); intc_setipl(IPL_HIGH); /* XXX ??? */ - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); } void @@ -269,7 +269,7 @@ intc_setipl(int new) if (intc_attached == 0) return; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); #if 0 { volatile static int recursed = 0; @@ -342,7 +342,7 @@ intc_intr_establish(int irqno, int level, int (*func)(void *), if (irqno < 0 || irqno >= INTC_NUM_IRQ) panic("intc_intr_establish: bogus irqnumber %d: %s", irqno, name); - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); /* no point in sleeping unless someone can free memory. */ ih = (struct intrhand *)malloc (sizeof *ih, M_DEVBUF, @@ -376,7 +376,7 @@ intc_intr_disestablish(void *cookie) int psw; struct intrhand *ih = cookie; int irqno = ih->ih_irq; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); TAILQ_REMOVE(&intc_handler[irqno].iq_list, ih, ih_list); if (ih->ih_name != NULL) evcount_detach(&ih->ih_count); diff --git a/sys/arch/armv7/omap/omgpio.c b/sys/arch/armv7/omap/omgpio.c index 3acf4deef6e..5df65bdc899 100644 --- a/sys/arch/armv7/omap/omgpio.c +++ b/sys/arch/armv7/omap/omgpio.c @@ -1,4 +1,4 @@ -/* $OpenBSD: omgpio.c,v 1.5 2014/07/14 08:55:07 rapha Exp $ */ +/* $OpenBSD: omgpio.c,v 1.6 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org> * @@ -621,7 +621,7 @@ omgpio_intr_establish(struct omgpio_softc *sc, unsigned int gpio, int level, int gpio, sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)]->ih_name, name); - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); /* no point in sleeping unless someone can free memory. */ ih = (struct intrhand *)malloc( sizeof *ih, M_DEVBUF, @@ -656,7 +656,7 @@ omgpio_intr_disestablish(struct omgpio_softc *sc, void *cookie) struct intrhand *ih = cookie; struct omgpio_softc *sc = omgpio_cd.cd_devs[GPIO_PIN_TO_INST(ih->ih_gpio)]; int gpio = ih->ih_gpio; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); ih = sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)]; sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)] = NULL; diff --git a/sys/arch/armv7/sunxi/a1xintc.c b/sys/arch/armv7/sunxi/a1xintc.c index 42f28722bef..67407a9ebdd 100644 --- a/sys/arch/armv7/sunxi/a1xintc.c +++ b/sys/arch/armv7/sunxi/a1xintc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: a1xintc.c,v 1.6 2015/05/20 03:49:23 jsg Exp $ */ +/* $OpenBSD: a1xintc.c,v 1.7 2016/01/31 00:14:50 jsg Exp $ */ /* * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org> * Copyright (c) 2013 Artturi Alm @@ -194,7 +194,7 @@ a1xintc_attach(struct device *parent, struct device *self, void *args) a1xintc_intr_establish, a1xintc_intr_disestablish, a1xintc_intr_string, a1xintc_irq_handler); a1xintc_setipl(IPL_HIGH); /* XXX ??? */ - enable_interrupts(I32_bit); + enable_interrupts(PSR_I); printf("\n"); } @@ -297,7 +297,7 @@ a1xintc_setipl(int new) return; } #endif - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); ci->ci_cpl = new; for (i = 0; i < NBANKS; i++) bus_space_write_4(a1xintc_iot, a1xintc_ioh, @@ -365,7 +365,7 @@ a1xintc_intr_establish(int irq, int lvl, int (*f)(void *), void *arg, char *name DPRINTF(("intr_establish: irq %d level %d [%s]\n", irq, lvl, name != NULL ? name : "NULL")); - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); /* no point in sleeping unless someone can free memory. */ ih = (struct intrhand *)malloc (sizeof *ih, M_DEVBUF, @@ -403,7 +403,7 @@ a1xintc_intr_disestablish(void *cookie) int psw; uint32_t er; - psw = disable_interrupts(I32_bit); + psw = disable_interrupts(PSR_I); TAILQ_REMOVE(&a1xintc_handler[irq].iq_list, ih, ih_list); |