diff options
| -rw-r--r-- | sys/arch/aviion/aviion/av400_machdep.c | 25 | ||||
| -rw-r--r-- | sys/arch/aviion/aviion/machdep.c | 23 | ||||
| -rw-r--r-- | sys/arch/luna88k/luna88k/machdep.c | 73 | ||||
| -rw-r--r-- | sys/arch/m88k/include/intr.h | 7 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m187_machdep.c | 20 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m188_machdep.c | 23 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/m197_machdep.c | 20 | ||||
| -rw-r--r-- | sys/arch/mvme88k/mvme88k/machdep.c | 52 |
8 files changed, 122 insertions, 121 deletions
diff --git a/sys/arch/aviion/aviion/av400_machdep.c b/sys/arch/aviion/aviion/av400_machdep.c index a8b1eda520f..31f24ab51f1 100644 --- a/sys/arch/aviion/aviion/av400_machdep.c +++ b/sys/arch/aviion/aviion/av400_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: av400_machdep.c,v 1.5 2007/05/12 20:02:12 miod Exp $ */ +/* $OpenBSD: av400_machdep.c,v 1.6 2007/11/17 05:32:04 miod Exp $ */ /* * Copyright (c) 2006, Miodrag Vallat. * @@ -197,7 +197,7 @@ const struct board board_av400 = { */ unsigned int int_mask_reg[] = { 0, 0, 0, 0 }; -u_int av400_curspl[] = { 0, 0, 0, 0 }; +u_int av400_curspl[] = { IPL_NONE, IPL_NONE, IPL_NONE, IPL_NONE }; /* * external interrupt masks per spl. @@ -294,9 +294,11 @@ av400_getipl(void) u_int av400_setipl(u_int level) { - u_int32_t mask, curspl; + u_int32_t mask, curspl, psr; u_int cpu = cpu_number(); + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = av400_curspl[cpu]; mask = int_mask_val[level]; @@ -307,6 +309,11 @@ av400_setipl(u_int level) *(u_int32_t *)AV_IEN(cpu) = int_mask_reg[cpu] = mask; av400_curspl[cpu] = level; + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ + set_psr(psr); return curspl; } @@ -314,9 +321,11 @@ av400_setipl(u_int level) u_int av400_raiseipl(u_int level) { - u_int32_t mask, curspl; + u_int32_t mask, curspl, psr; u_int cpu = cpu_number(); + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = av400_curspl[cpu]; if (curspl < level) { mask = int_mask_val[level]; @@ -328,6 +337,12 @@ av400_raiseipl(u_int level) *(u_int32_t *)AV_IEN(cpu) = int_mask_reg[cpu] = mask; av400_curspl[cpu] = level; } + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ + set_psr(psr); + return curspl; } @@ -382,7 +397,7 @@ av400_intr(u_int v, struct trapframe *eframe) { int cpu = cpu_number(); unsigned int cur_mask, ign_mask; - unsigned int level, old_spl; + u_int level, old_spl; struct intrhand *intr; intrhand_t *list; int ret, intbit; diff --git a/sys/arch/aviion/aviion/machdep.c b/sys/arch/aviion/aviion/machdep.c index 84478d177f0..668f450da1b 100644 --- a/sys/arch/aviion/aviion/machdep.c +++ b/sys/arch/aviion/aviion/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.15 2007/11/15 21:23:14 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.16 2007/11/17 05:32:04 miod Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -96,7 +96,6 @@ void consinit(void); __dead void doboot(void); void dumpconf(void); void dumpsys(void); -u_int getipl(void); void identifycpu(void); void savectx(struct pcb *); void secondary_main(void); @@ -898,7 +897,7 @@ bootcnputc(dev, c) scm_putc(c); } -u_int +int getipl(void) { u_int curspl, psr; @@ -906,16 +905,16 @@ getipl(void) disable_interrupt(psr); curspl = platform->getipl(); set_psr(psr); - return curspl; + return (int)curspl; } -u_int -setipl(u_int level) +int +setipl(int level) { u_int curspl, psr; disable_interrupt(psr); - curspl = platform->setipl(level); + curspl = platform->setipl((u_int)level); /* * The flush pipeline is required to make sure the above change gets @@ -925,16 +924,16 @@ setipl(u_int level) flush_pipeline(); set_psr(psr); - return curspl; + return (int)curspl; } -u_int -raiseipl(u_int level) +int +raiseipl(int level) { u_int curspl, psr; disable_interrupt(psr); - curspl = platform->raiseipl(level); + curspl = platform->raiseipl((u_int)level); /* * The flush pipeline is required to make sure the above change gets @@ -944,7 +943,7 @@ raiseipl(u_int level) flush_pipeline(); set_psr(psr); - return curspl; + return (int)curspl; } u_char hostaddr[6]; diff --git a/sys/arch/luna88k/luna88k/machdep.c b/sys/arch/luna88k/luna88k/machdep.c index 2d1cc5d6ba5..d3f0028589f 100644 --- a/sys/arch/luna88k/luna88k/machdep.c +++ b/sys/arch/luna88k/luna88k/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.49 2007/11/15 21:23:15 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.50 2007/11/17 05:32:05 miod Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -110,13 +110,12 @@ void cpu_boot_secondary_processors(void); void dumpconf(void); void dumpsys(void); int getcpuspeed(void); -u_int getipl(void); void identifycpu(void); void luna88k_bootstrap(void); void savectx(struct pcb *); void secondary_main(void); vaddr_t secondary_pre_main(void); -void setlevel(unsigned int); +void setlevel(u_int); vaddr_t size_memory(void); void powerdown(void); @@ -137,7 +136,7 @@ unsigned int *volatile int_mask_reg[] = { (unsigned int *)INT_ST_MASK3 }; -unsigned int luna88k_curspl[] = {0, 0, 0, 0}; +u_int luna88k_curspl[] = { IPL_NONE, IPL_NONE, IPL_NONE, IPL_NONE }; unsigned int int_set_val[INT_LEVEL] = { INT_SET_LV0, @@ -839,7 +838,7 @@ luna88k_ext_int(u_int v, struct trapframe *eframe) { int cpu = cpu_number(); unsigned int cur_mask, cur_int; - unsigned int level, old_spl; + u_int level, old_spl; cur_mask = *int_mask_reg[cpu]; old_spl = luna88k_curspl[cpu]; @@ -1252,9 +1251,9 @@ nvram_by_symbol(symbol) } void -setlevel(unsigned int level) +setlevel(u_int level) { - unsigned int set_value; + u_int32_t set_value; int cpu = cpu_number(); set_value = int_set_val[level]; @@ -1264,58 +1263,44 @@ setlevel(unsigned int level) set_value &= INT_SLAVE_MASK; #endif - *int_mask_reg[cpu] = set_value; luna88k_curspl[cpu] = level; + *int_mask_reg[cpu] = set_value; + /* + * We do not flush the pipeline here, because we are invoked + * with interrupts disabled, and the caller will synchronize + * the pipeline when restoring the psr. + */ } -u_int +int getipl(void) { - u_int curspl, psr; - - disable_interrupt(psr); - curspl = luna88k_curspl[cpu_number()]; - set_psr(psr); - return curspl; + return (int)luna88k_curspl[cpu_number()]; } -unsigned -setipl(unsigned level) +int +setipl(int level) { - unsigned int curspl, psr; + u_int curspl, psr; - disable_interrupt(psr); + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = luna88k_curspl[cpu_number()]; - setlevel(level); - - /* - * The flush pipeline is required to make sure the above write gets - * through the data pipe and to the hardware; otherwise, the next - * bunch of instructions could execute at the wrong spl protection. - */ - flush_pipeline(); - + setlevel((u_int)level); set_psr(psr); - return curspl; + return (int)curspl; } -unsigned -raiseipl(unsigned level) +int +raiseipl(int level) { - unsigned int curspl, psr; + u_int curspl, psr; - disable_interrupt(psr); + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = luna88k_curspl[cpu_number()]; - if (curspl < level) - setlevel(level); - - /* - * The flush pipeline is required to make sure the above write gets - * through the data pipe and to the hardware; otherwise, the next - * bunch of instructions could execute at the wrong spl protection. - */ - flush_pipeline(); - + if (curspl < (u_int)level) + setlevel((u_int)level); set_psr(psr); - return curspl; + return (int)curspl; } diff --git a/sys/arch/m88k/include/intr.h b/sys/arch/m88k/include/intr.h index 0eb24b2076d..1ee0ea48731 100644 --- a/sys/arch/m88k/include/intr.h +++ b/sys/arch/m88k/include/intr.h @@ -1,4 +1,4 @@ -/* $OpenBSD: intr.h,v 1.8 2007/05/16 19:37:06 thib Exp $ */ +/* $OpenBSD: intr.h,v 1.9 2007/11/17 05:32:05 miod Exp $ */ /* * Copyright (C) 2000 Steve Murphree, Jr. * All rights reserved. @@ -31,8 +31,9 @@ #ifdef _KERNEL #ifndef _LOCORE -unsigned setipl(unsigned level); -unsigned raiseipl(unsigned level); +int getipl(void); +int setipl(int level); +int raiseipl(int level); int spl0(void); /* SPL asserts */ diff --git a/sys/arch/mvme88k/mvme88k/m187_machdep.c b/sys/arch/mvme88k/mvme88k/m187_machdep.c index b61990d34d9..5e3b2a4a5a6 100644 --- a/sys/arch/mvme88k/mvme88k/m187_machdep.c +++ b/sys/arch/mvme88k/mvme88k/m187_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: m187_machdep.c,v 1.15 2007/05/14 16:59:43 miod Exp $ */ +/* $OpenBSD: m187_machdep.c,v 1.16 2007/11/17 05:32:05 miod Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -205,21 +205,35 @@ m187_getipl(void) u_int m187_setipl(u_int level) { - unsigned curspl; + u_int curspl, psr; + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = *(u_int8_t *)M187_IMASK & 0x07; *(u_int8_t *)M187_IMASK = level; + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ + set_psr(psr); return curspl; } u_int m187_raiseipl(u_int level) { - unsigned curspl; + u_int curspl, psr; + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = *(u_int8_t *)M187_IMASK & 0x07; if (curspl < level) *(u_int8_t *)M187_IMASK = level; + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ + set_psr(psr); return curspl; } diff --git a/sys/arch/mvme88k/mvme88k/m188_machdep.c b/sys/arch/mvme88k/mvme88k/m188_machdep.c index 04897781664..31b6bdef70d 100644 --- a/sys/arch/mvme88k/mvme88k/m188_machdep.c +++ b/sys/arch/mvme88k/mvme88k/m188_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: m188_machdep.c,v 1.40 2007/11/14 23:14:14 miod Exp $ */ +/* $OpenBSD: m188_machdep.c,v 1.41 2007/11/17 05:32:05 miod Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -159,7 +159,7 @@ void m188_startup(void); */ unsigned int int_mask_reg[] = { 0, 0, 0, 0 }; -unsigned int m188_curspl[] = { IPL_NONE, IPL_NONE, IPL_NONE, IPL_NONE}; +u_int m188_curspl[] = { IPL_NONE, IPL_NONE, IPL_NONE, IPL_NONE }; /* * external interrupt masks per spl. @@ -256,7 +256,8 @@ m188_reset() } /* - * return next safe spl to reenable interrupts. + * Return the next ipl >= ``curlevel'' at which we can reenable interrupts + * while keeping ``mask'' masked. */ u_int safe_level(u_int mask, u_int curlevel) @@ -306,9 +307,12 @@ m188_setipl(u_int level) mask |= SWI_CLOCK_IPI_MASK(cpu); #endif - *(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask; m188_curspl[cpu] = level; - + *(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask; + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ set_psr(psr); return curspl; @@ -339,10 +343,13 @@ m188_raiseipl(u_int level) mask |= SWI_CLOCK_IPI_MASK(cpu); #endif - *(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask; m188_curspl[cpu] = level; + *(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask; } - + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ set_psr(psr); return curspl; @@ -484,7 +491,7 @@ m188_ext_int(u_int v, struct trapframe *eframe) u_int cpu = cpu_number(); #endif unsigned int cur_mask, ign_mask; - unsigned int level, old_spl; + u_int level, old_spl; struct intrhand *intr; intrhand_t *list; int ret, intbit; diff --git a/sys/arch/mvme88k/mvme88k/m197_machdep.c b/sys/arch/mvme88k/mvme88k/m197_machdep.c index 671b4a43eea..6a33e498703 100644 --- a/sys/arch/mvme88k/mvme88k/m197_machdep.c +++ b/sys/arch/mvme88k/mvme88k/m197_machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: m197_machdep.c,v 1.14 2007/05/14 16:59:43 miod Exp $ */ +/* $OpenBSD: m197_machdep.c,v 1.15 2007/11/17 05:32:05 miod Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -246,21 +246,35 @@ m197_getipl(void) u_int m197_setipl(u_int level) { - u_int curspl; + u_int curspl, psr; + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = *(u_int8_t *)M197_IMASK & 0x07; *(u_int8_t *)M197_IMASK = level; + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ + set_psr(psr); return curspl; } u_int m197_raiseipl(u_int level) { - u_int curspl; + u_int curspl, psr; + psr = get_psr(); + set_psr(psr | PSR_IND); curspl = *(u_int8_t *)M197_IMASK & 0x07; if (curspl < level) *(u_int8_t *)M197_IMASK = level; + /* + * We do not flush the pipeline here, because interrupts are disabled, + * and set_psr() will synchronize the pipeline. + */ + set_psr(psr); return curspl; } diff --git a/sys/arch/mvme88k/mvme88k/machdep.c b/sys/arch/mvme88k/mvme88k/machdep.c index d364c9a94b8..cf5975048e9 100644 --- a/sys/arch/mvme88k/mvme88k/machdep.c +++ b/sys/arch/mvme88k/mvme88k/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.201 2007/11/15 21:23:16 miod Exp $ */ +/* $OpenBSD: machdep.c,v 1.202 2007/11/17 05:32:05 miod Exp $ */ /* * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr. * Copyright (c) 1996 Nivas Madhur @@ -95,7 +95,6 @@ void consinit(void); void dumpconf(void); void dumpsys(void); int getcpuspeed(struct mvmeprom_brdid *); -u_int getipl(void); void identifycpu(void); void mvme_bootstrap(void); void mvme88k_vector_init(u_int32_t *, u_int32_t *); @@ -105,8 +104,6 @@ void secondary_main(void); vaddr_t secondary_pre_main(void); void _doboot(void); -extern void setlevel(unsigned int); - extern void m187_bootstrap(void); extern vaddr_t m187_memsize(void); extern void m187_startup(void); @@ -1114,53 +1111,22 @@ bootcnputc(dev, c) bugoutchr(c); } -u_int +int getipl(void) { - u_int curspl, psr; - - disable_interrupt(psr); - curspl = (*md_getipl)(); - set_psr(psr); - return curspl; + return (int)(*md_getipl)(); } -unsigned -setipl(unsigned level) +int +setipl(int level) { - u_int curspl, psr; - - disable_interrupt(psr); - curspl = (*md_setipl)(level); - - /* - * The flush pipeline is required to make sure the above change gets - * through the data pipe and to the hardware; otherwise, the next - * bunch of instructions could execute at the wrong spl protection. - */ - flush_pipeline(); - - set_psr(psr); - return curspl; + return (int)(*md_setipl)((u_int)level); } -unsigned -raiseipl(unsigned level) +int +raiseipl(int level) { - u_int curspl, psr; - - disable_interrupt(psr); - curspl = (*md_raiseipl)(level); - - /* - * The flush pipeline is required to make sure the above change gets - * through the data pipe and to the hardware; otherwise, the next - * bunch of instructions could execute at the wrong spl protection. - */ - flush_pipeline(); - - set_psr(psr); - return curspl; + return (int)(*md_raiseipl)((u_int)level); } #ifdef MULTIPROCESSOR |