diff options
| -rw-r--r-- | sys/dev/pci/if_ix.c | 154 | ||||
| -rw-r--r-- | sys/dev/pci/if_ix.h | 56 | ||||
| -rw-r--r-- | sys/dev/pci/ixgbe.c | 157 | ||||
| -rw-r--r-- | sys/dev/pci/ixgbe.h | 114 | ||||
| -rw-r--r-- | sys/dev/pci/ixgbe_82598.c | 162 | ||||
| -rw-r--r-- | sys/dev/pci/ixgbe_82599.c | 184 | ||||
| -rw-r--r-- | sys/dev/pci/ixgbe_phy.c | 282 | ||||
| -rw-r--r-- | sys/dev/pci/ixgbe_type.h | 136 |
8 files changed, 621 insertions, 624 deletions
diff --git a/sys/dev/pci/if_ix.c b/sys/dev/pci/if_ix.c index a364fd8f4df..a47bafc34cf 100644 --- a/sys/dev/pci/if_ix.c +++ b/sys/dev/pci/if_ix.c @@ -1,33 +1,33 @@ -/* $OpenBSD: if_ix.c,v 1.65 2012/07/06 11:08:44 mikeb Exp $ */ +/* $OpenBSD: if_ix.c,v 1.66 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2008, Intel Corporation + Copyright (c) 2001-2008, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -260,7 +260,7 @@ ixgbe_attach(struct device *parent, struct device *self, void *aux) if (error == IXGBE_ERR_SFP_NOT_PRESENT) { /* * No optics in this port, set up - * so the timer routine will probe + * so the timer routine will probe * for later insertion. */ sc->sfp_probe = TRUE; @@ -306,8 +306,8 @@ ixgbe_attach(struct device *parent, struct device *self, void *aux) IXGBE_ETH_LENGTH_OF_ADDRESS); /* XXX sc->msix > 1 && ixgbe_allocate_msix() */ - error = ixgbe_allocate_legacy(sc); - if (error) + error = ixgbe_allocate_legacy(sc); + if (error) goto err_late; /* Setup OS specific network interface */ @@ -428,9 +428,9 @@ ixgbe_start_locked(struct tx_ring *txr, struct ifnet * ifp) post = 1; } - bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, - 0, txr->txdma.dma_map->dm_mapsize, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, + 0, txr->txdma.dma_map->dm_mapsize, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); /* * Advance the Transmit Descriptor Tail (Tdt), this tells the @@ -565,16 +565,16 @@ ixgbe_watchdog(struct ifnet * ifp) int tx_hang = FALSE; int i; - /* - * The timer is set to 5 every time ixgbe_start() queues a packet. - * Then ixgbe_txeof() keeps resetting to 5 as long as it cleans at - * least one descriptor. - * Finally, anytime all descriptors are clean the timer is - * set to 0. - */ + /* + * The timer is set to 5 every time ixgbe_start() queues a packet. + * Then ixgbe_txeof() keeps resetting to 5 as long as it cleans at + * least one descriptor. + * Finally, anytime all descriptors are clean the timer is + * set to 0. + */ for (i = 0; i < sc->num_queues; i++, txr++) { - if (txr->watchdog_timer == 0 || --txr->watchdog_timer) - continue; + if (txr->watchdog_timer == 0 || --txr->watchdog_timer) + continue; else { tx_hang = TRUE; break; @@ -855,7 +855,7 @@ ixgbe_disable_queue(struct ix_softc *sc, uint32_t vector) { uint64_t queue = 1ULL << vector; uint32_t mask; - + if (sc->hw.mac.type == ixgbe_mac_82598EB) { mask = (IXGBE_EIMS_RTX_QUEUE & queue); IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, mask); @@ -869,10 +869,10 @@ ixgbe_disable_queue(struct ix_softc *sc, uint32_t vector) } } -void +void ixgbe_rearm_queue(struct ix_softc *sc, uint32_t vector) { - uint64_t queue = 1ULL << vector; + uint64_t queue = 1ULL << vector; uint32_t mask; if (sc->hw.mac.type == ixgbe_mac_82598EB) { @@ -891,7 +891,7 @@ ixgbe_rearm_queue(struct ix_softc *sc, uint32_t vector) void ixgbe_handle_que(void *context, int pending) { - struct ix_queue *que = context; + struct ix_queue *que = context; struct ix_softc *sc = que->sc; struct tx_ring *txr = que->txr; struct ifnet *ifp = &que->sc->arpcom.ac_if; @@ -947,7 +947,7 @@ ixgbe_legacy_irq(void *arg) /* Check for fan failure */ if ((hw->phy.media_type == ixgbe_media_type_copper) && (reg_eicr & IXGBE_EICR_GPI_SDP1)) { - printf("\n%s: CRITICAL: FAN FAILURE!! " + printf("\n%s: CRITICAL: FAN FAILURE!! " "REPLACE IMMEDIATELY!!\n", ifp->if_xname); IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS, IXGBE_EICR_GPI_SDP1); @@ -956,7 +956,7 @@ ixgbe_legacy_irq(void *arg) /* Link status change */ if (reg_eicr & IXGBE_EICR_LSC) { timeout_del(&sc->timer); - ixgbe_update_link_status(sc); + ixgbe_update_link_status(sc); timeout_add_sec(&sc->timer, 1); } @@ -1048,8 +1048,8 @@ ixgbe_encap(struct tx_ring *txr, struct mbuf *m_head) uint32_t paylen = 0; /* Basic descriptor defines */ - cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; - cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; + cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; + cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; #if NVLAN > 0 if (m_head->m_flags & M_VLANTAG) @@ -1068,12 +1068,12 @@ ixgbe_encap(struct tx_ring *txr, struct mbuf *m_head) return (ENOBUFS); } - /* - * Important to capture the first descriptor - * used because it will contain the index of - * the one we tell the hardware to report back - */ - first = txr->next_avail_desc; + /* + * Important to capture the first descriptor + * used because it will contain the index of + * the one we tell the hardware to report back + */ + first = txr->next_avail_desc; txbuf = &txr->tx_buffers[first]; map = txbuf->map; @@ -1099,7 +1099,7 @@ ixgbe_encap(struct tx_ring *txr, struct mbuf *m_head) /* * Set the appropriate offload context - * this becomes the first descriptor of + * this becomes the first descriptor of * a packet. */ #ifdef notyet @@ -1149,8 +1149,8 @@ ixgbe_encap(struct tx_ring *txr, struct mbuf *m_head) bus_dmamap_sync(txr->txdma.dma_tag, map, 0, map->dm_mapsize, BUS_DMASYNC_PREWRITE); - /* Set the index of the descriptor that will be marked done */ - txbuf = &txr->tx_buffers[first]; + /* Set the index of the descriptor that will be marked done */ + txbuf = &txr->tx_buffers[first]; txbuf->eop_index = last; ++txr->tx_packets; @@ -1243,7 +1243,7 @@ ixgbe_local_timer(void *arg) struct ifnet *ifp = &sc->arpcom.ac_if; #endif int s; - + s = splnet(); /* Check for pluggable optics */ @@ -1448,7 +1448,7 @@ ixgbe_setup_optics(struct ix_softc *sc) { struct ixgbe_hw *hw = &sc->hw; int layer; - + layer = ixgbe_hw(hw, get_supported_physical_layer); switch (layer) { case IXGBE_PHYSICAL_LAYER_10GBASE_T: @@ -1613,7 +1613,7 @@ ixgbe_setup_interface(struct ix_softc *sc) ETHER_HDR_LEN - ETHER_CRC_LEN; IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1); IFQ_SET_READY(&ifp->if_snd); - + m_clsetwms(ifp, MCLBYTES, 4, sc->num_rx_desc); ifp->if_capabilities = IFCAP_VLAN_MTU; @@ -1733,7 +1733,7 @@ ixgbe_dma_malloc(struct ix_softc *sc, bus_size_t size, } r = bus_dmamap_load(dma->dma_tag, dma->dma_map, - dma->dma_vaddr, size, NULL, + dma->dma_vaddr, size, NULL, mapflags | BUS_DMA_NOWAIT); if (r != 0) { printf("%s: ixgbe_dma_malloc: bus_dmamap_load failed; " @@ -1822,7 +1822,7 @@ ixgbe_allocate_queues(struct ix_softc *sc) * Now set up the TX queues, txconf is needed to handle the * possibility that things fail midcourse and we need to * undo memory gracefully - */ + */ for (i = 0; i < sc->num_queues; i++, txconf++) { /* Set up some basics */ txr = &sc->tx_rings[i]; @@ -1844,7 +1844,7 @@ ixgbe_allocate_queues(struct ix_softc *sc) /* * Next the RX queues... - */ + */ rsize = roundup2(sc->num_rx_desc * sizeof(union ixgbe_adv_rx_desc), 4096); for (i = 0; i < sc->num_queues; i++, rxconf++) { @@ -1930,7 +1930,7 @@ ixgbe_allocate_transmit_buffers(struct tx_ring *txr) } txr->txtag = txr->txdma.dma_tag; - /* Create the descriptor buffer dma maps */ + /* Create the descriptor buffer dma maps */ for (i = 0; i < sc->num_tx_desc; i++) { txbuf = &txr->tx_buffers[i]; error = bus_dmamap_create(txr->txdma.dma_tag, IXGBE_TSO_SIZE, @@ -2177,7 +2177,7 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp) TXD = (struct ixgbe_adv_tx_context_desc *) &txr->tx_base[ctxd]; /* - * In advanced descriptors the vlan tag must + * In advanced descriptors the vlan tag must * be placed into the descriptor itself. */ #if NVLAN > 0 @@ -2267,7 +2267,7 @@ ixgbe_tx_ctx_setup(struct tx_ring *txr, struct mbuf *mp) txr->next_avail_desc = ctxd; --txr->tx_avail; - return (offload); + return (offload); } #ifdef notyet @@ -2297,7 +2297,7 @@ ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, uint32_t *paylen) if (((mp->m_pkthdr.csum_flags & CSUM_TSO) == 0) || (mp->m_pkthdr.len <= IXGBE_TX_BUFFER_SIZE)) - return FALSE; + return FALSE; /* * Determine where frame payload starts. @@ -2305,7 +2305,7 @@ ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, uint32_t *paylen) */ #if NVLAN > 0 eh = mtod(mp, struct ether_vlan_header *); - if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) + if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; else ehdrlen = ETHER_HDR_LEN; @@ -2314,8 +2314,8 @@ ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, uint32_t *paylen) ehdrlen = ETHER_HDR_LEN; #endif - /* Ensure we have at least the IP+TCP header in the first mbuf. */ - if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) + /* Ensure we have at least the IP+TCP header in the first mbuf. */ + if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) return FALSE; ctxd = txr->next_avail_desc; @@ -2420,9 +2420,9 @@ ixgbe_txeof(struct tx_ring *txr) if (++last == sc->num_tx_desc) last = 0; done = last; - bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, + bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0, txr->txdma.dma_map->dm_mapsize, - BUS_DMASYNC_POSTREAD); + BUS_DMASYNC_POSTREAD); while (eop_desc->upper.fields.status & IXGBE_TXD_STAT_DD) { /* We clean the range of the packet */ @@ -2548,7 +2548,7 @@ ixgbe_get_buf(struct rx_ring *rxr, int i) m_freem(mh); return (error); } - bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->hmap, + bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->hmap, 0, rxbuf->hmap->dm_mapsize, BUS_DMASYNC_PREREAD); rxbuf->m_head = mh; @@ -2573,7 +2573,7 @@ no_split: return (error); } - bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->pmap, + bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->pmap, 0, rxbuf->pmap->dm_mapsize, BUS_DMASYNC_PREREAD); rxbuf->m_pack = mp; @@ -2587,7 +2587,7 @@ no_split: rxr->rx_ndescs++; - return (0); + return (0); } /********************************************************************* @@ -2604,7 +2604,7 @@ ixgbe_allocate_receive_buffers(struct rx_ring *rxr) struct ix_softc *sc = rxr->sc; struct ifnet *ifp = &sc->arpcom.ac_if; struct ixgbe_rx_buf *rxbuf; - int i, bsize, error; + int i, bsize, error; bsize = sizeof(struct ixgbe_rx_buf) * sc->num_rx_desc; if (!(rxr->rx_buffers = (struct ixgbe_rx_buf *) malloc(bsize, @@ -2808,7 +2808,7 @@ ixgbe_initialize_receive_units(struct ix_softc *sc) if (sc->hw.mac.type != ixgbe_mac_82598EB) { uint32_t psrtype = IXGBE_PSRTYPE_TCPHDR | - IXGBE_PSRTYPE_UDPHDR | + IXGBE_PSRTYPE_UDPHDR | IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR; IXGBE_WRITE_REG(&sc->hw, IXGBE_PSRTYPE(0), psrtype); @@ -3011,7 +3011,7 @@ ixgbe_rxeof(struct ix_queue *que, int count) } /* XXX ixgbe_realign() STRICT_ALIGN */ - /* Currently no HW RSC support of 82599 */ + /* Currently no HW RSC support of 82599 */ if (!eop) { /* * Figure out the next descriptor of this frame. @@ -3378,7 +3378,7 @@ ixgbe_configure_ivars(struct ix_softc *sc) #endif newitr = 0; - for (i = 0; i < sc->num_queues; i++, que++) { + for (i = 0; i < sc->num_queues; i++, que++) { /* First the RX queue entry */ ixgbe_set_ivar(sc, i, que->msix, 0); /* ... and the TX */ @@ -3389,7 +3389,7 @@ ixgbe_configure_ivars(struct ix_softc *sc) } /* For the Link interrupt */ - ixgbe_set_ivar(sc, 1, sc->linkvec, -1); + ixgbe_set_ivar(sc, 1, sc->linkvec, -1); } /* @@ -3441,7 +3441,7 @@ ixgbe_update_stats_counters(struct ix_softc *sc) int mp; mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); missed_rx += mp; - sc->stats.mpc[i] += mp; + sc->stats.mpc[i] += mp; if (hw->mac.type == ixgbe_mac_82598EB) sc->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); } diff --git a/sys/dev/pci/if_ix.h b/sys/dev/pci/if_ix.h index de10f4aa016..42ccfb6aab5 100644 --- a/sys/dev/pci/if_ix.h +++ b/sys/dev/pci/if_ix.h @@ -1,33 +1,33 @@ -/* $OpenBSD: if_ix.h,v 1.15 2012/07/05 14:36:22 mikeb Exp $ */ +/* $OpenBSD: if_ix.h,v 1.16 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2008, Intel Corporation + Copyright (c) 2001-2008, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -57,9 +57,9 @@ * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the * number of receive descriptors allocated for each RX queue. Increasing this * value allows the driver to buffer more incoming packets. Each descriptor - * is 16 bytes. A receive buffer is also allocated for each descriptor. - * - * Note: with 8 rings and a dual port card, it is possible to bump up + * is 16 bytes. A receive buffer is also allocated for each descriptor. + * + * Note: with 8 rings and a dual port card, it is possible to bump up * against the system mbuf pool limit, you can tune nmbclusters * to adjust for this. */ @@ -172,7 +172,7 @@ struct ix_queue { * The transmit ring, one per tx queue */ struct tx_ring { - struct ix_softc *sc; + struct ix_softc *sc; struct mutex tx_mtx; uint32_t me; int queue_status; @@ -196,7 +196,7 @@ struct tx_ring { * The Receive ring, one per rx queue */ struct rx_ring { - struct ix_softc *sc; + struct ix_softc *sc; struct mutex rx_mtx; uint32_t me; union ixgbe_adv_rx_desc *rx_base; @@ -208,8 +208,8 @@ struct rx_ring { int hdr_split; int hw_rsc; int discard; - unsigned int next_to_refresh; - unsigned int next_to_check; + unsigned int next_to_refresh; + unsigned int next_to_check; unsigned int last_desc_filled; int rx_ndescs; struct ixgbe_rx_buf *rx_buffers; diff --git a/sys/dev/pci/ixgbe.c b/sys/dev/pci/ixgbe.c index e3227631e69..3505cc5aa41 100644 --- a/sys/dev/pci/ixgbe.c +++ b/sys/dev/pci/ixgbe.c @@ -1,33 +1,33 @@ -/* $OpenBSD: ixgbe.c,v 1.6 2011/06/10 12:46:35 claudio Exp $ */ +/* $OpenBSD: ixgbe.c,v 1.7 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2009, Intel Corporation + Copyright (c) 2001-2009, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -42,7 +42,7 @@ void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); int32_t ixgbe_ready_eeprom(struct ixgbe_hw *hw); void ixgbe_standby_eeprom(struct ixgbe_hw *hw); void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, uint16_t data, - uint16_t count); + uint16_t count); uint16_t ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, uint16_t count); void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec); void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, uint32_t *eec); @@ -54,7 +54,7 @@ int32_t ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw); int32_t ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw); int32_t ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw); int32_t ixgbe_negotiate_fc(struct ixgbe_hw *hw, uint32_t adv_reg, uint32_t lp_reg, - uint32_t adv_sym, uint32_t adv_asm, uint32_t lp_sym, uint32_t lp_asm); + uint32_t adv_sym, uint32_t adv_asm, uint32_t lp_sym, uint32_t lp_asm); int32_t ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, uint32_t vlan); @@ -69,18 +69,18 @@ int32_t ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, uint16_t mbx_id); int32_t ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, uint16_t mbx_id); int32_t ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw); int32_t ixgbe_write_mbx_vf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t mbx_id); + uint16_t mbx_id); int32_t ixgbe_read_mbx_vf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t mbx_id); + uint16_t mbx_id); int32_t ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, uint32_t mask, int32_t index); int32_t ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, uint16_t vf_number); int32_t ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, uint16_t vf_number); int32_t ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, uint16_t vf_number); int32_t ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, uint16_t vf_number); int32_t ixgbe_write_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t vf_number); + uint16_t vf_number); int32_t ixgbe_read_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t vf_number); + uint16_t vf_number); /** @@ -104,7 +104,7 @@ int32_t ixgbe_init_ops_generic(struct ixgbe_hw *hw) eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; eeprom->ops.write = &ixgbe_write_eeprom_generic; eeprom->ops.validate_checksum = - &ixgbe_validate_eeprom_checksum_generic; + &ixgbe_validate_eeprom_checksum_generic; eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic; @@ -365,7 +365,7 @@ int32_t ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) * Reads the part number string from the EEPROM. **/ int32_t ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, uint8_t *pba_num, - uint32_t pba_num_size) + uint32_t pba_num_size) { int32_t ret_val; uint16_t data; @@ -776,9 +776,9 @@ int32_t ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) * change if a future EEPROM is not SPI. */ eeprom_size = (uint16_t)((eec & IXGBE_EEC_SIZE) >> - IXGBE_EEC_SIZE_SHIFT); + IXGBE_EEC_SIZE_SHIFT); eeprom->word_size = 1 << (eeprom_size + - IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT); + IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT); } if (eec & IXGBE_EEC_ADDR_SIZE) @@ -786,8 +786,8 @@ int32_t ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) else eeprom->address_bits = 8; DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " - "%d\n", eeprom->type, eeprom->word_size, - eeprom->address_bits); + "%d\n", eeprom->type, eeprom->word_size, + eeprom->address_bits); } return IXGBE_SUCCESS; @@ -829,7 +829,7 @@ int32_t ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_ /* Send the WRITE ENABLE command (8 bit opcode ) */ ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, - IXGBE_EEPROM_OPCODE_BITS); + IXGBE_EEPROM_OPCODE_BITS); ixgbe_standby_eeprom(hw); @@ -842,9 +842,9 @@ int32_t ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_ /* Send the Write command (8-bit opcode + addr) */ ixgbe_shift_out_eeprom_bits(hw, write_opcode, - IXGBE_EEPROM_OPCODE_BITS); + IXGBE_EEPROM_OPCODE_BITS); ixgbe_shift_out_eeprom_bits(hw, (uint16_t)(offset*2), - hw->eeprom.address_bits); + hw->eeprom.address_bits); /* Send the data */ data = (data >> 8) | (data << 8); @@ -868,7 +868,7 @@ out: * Reads 16 bit value from EEPROM through bit-bang method **/ int32_t ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset, - uint16_t *data) + uint16_t *data) { int32_t status; uint16_t word_in; @@ -903,9 +903,9 @@ int32_t ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset, /* Send the READ command (opcode + addr) */ ixgbe_shift_out_eeprom_bits(hw, read_opcode, - IXGBE_EEPROM_OPCODE_BITS); + IXGBE_EEPROM_OPCODE_BITS); ixgbe_shift_out_eeprom_bits(hw, (uint16_t)(offset*2), - hw->eeprom.address_bits); + hw->eeprom.address_bits); /* Read the data. */ word_in = ixgbe_shift_in_eeprom_bits(hw, 16); @@ -947,7 +947,7 @@ int32_t ixgbe_read_eerd_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t * if (status == IXGBE_SUCCESS) *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> - IXGBE_EEPROM_RW_REG_DATA); + IXGBE_EEPROM_RW_REG_DATA); else DEBUGOUT("Eeprom read timed out\n"); @@ -1130,13 +1130,13 @@ int32_t ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) */ if (i >= timeout) { DEBUGOUT("SWESMBI Software EEPROM semaphore " - "not granted.\n"); + "not granted.\n"); ixgbe_release_eeprom_semaphore(hw); status = IXGBE_ERR_EEPROM; } } else { DEBUGOUT("Software semaphore SMBI between device drivers " - "not granted.\n"); + "not granted.\n"); } return status; @@ -1178,7 +1178,7 @@ int32_t ixgbe_ready_eeprom(struct ixgbe_hw *hw) */ for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, - IXGBE_EEPROM_OPCODE_BITS); + IXGBE_EEPROM_OPCODE_BITS); spi_stat_reg = (uint8_t)ixgbe_shift_in_eeprom_bits(hw, 8); if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) break; @@ -1227,7 +1227,7 @@ void ixgbe_standby_eeprom(struct ixgbe_hw *hw) * @count: number of bits to shift out **/ void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, uint16_t data, - uint16_t count) + uint16_t count) { uint32_t eec; uint32_t mask; @@ -1427,7 +1427,7 @@ uint16_t ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) * caller does not need checksum_val, the value can be NULL. **/ int32_t ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, - uint16_t *checksum_val) + uint16_t *checksum_val) { int32_t status; uint16_t checksum; @@ -1481,7 +1481,7 @@ int32_t ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) if (status == IXGBE_SUCCESS) { checksum = hw->eeprom.ops.calc_checksum(hw); status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, - checksum); + checksum); } else { DEBUGOUT("EEPROM read failed\n"); } @@ -1509,7 +1509,7 @@ int32_t ixgbe_validate_mac_addr(uint8_t *mac_addr) status = IXGBE_ERR_INVALID_MAC_ADDR; /* Reject the zero address */ } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && - mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { + mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { DEBUGOUT("MAC address is all zeros\n"); status = IXGBE_ERR_INVALID_MAC_ADDR; } @@ -1527,7 +1527,7 @@ int32_t ixgbe_validate_mac_addr(uint8_t *mac_addr) * Puts an ethernet address into a receive address register. **/ int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr, uint32_t vmdq, - uint32_t enable_addr) + uint32_t enable_addr) { uint32_t rar_low, rar_high; uint32_t rar_entries = hw->mac.num_rar_entries; @@ -1547,9 +1547,9 @@ int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr * order from network order (big endian) to little endian */ rar_low = ((uint32_t)addr[0] | - ((uint32_t)addr[1] << 8) | - ((uint32_t)addr[2] << 16) | - ((uint32_t)addr[3] << 24)); + ((uint32_t)addr[1] << 8) | + ((uint32_t)addr[2] << 16) | + ((uint32_t)addr[3] << 24)); /* * Some parts put the VMDq setting in the extra RAH bits, * so save everything except the lower 16 bits that hold part @@ -1627,18 +1627,18 @@ int32_t ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) hw->mac.ops.get_mac_addr(hw, hw->mac.addr); DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", - hw->mac.addr[0], hw->mac.addr[1], - hw->mac.addr[2]); + hw->mac.addr[0], hw->mac.addr[1], + hw->mac.addr[2]); DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], - hw->mac.addr[4], hw->mac.addr[5]); + hw->mac.addr[4], hw->mac.addr[5]); } else { /* Setup the receive address. */ DEBUGOUT("Overriding MAC Address in RAR[0]\n"); DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", - hw->mac.addr[0], hw->mac.addr[1], - hw->mac.addr[2]); + hw->mac.addr[0], hw->mac.addr[1], + hw->mac.addr[2]); DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], - hw->mac.addr[4], hw->mac.addr[5]); + hw->mac.addr[4], hw->mac.addr[5]); hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); @@ -1682,7 +1682,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq) uint32_t rar; DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", - addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); /* * Place this address in the RAR if there is room, @@ -1715,7 +1715,7 @@ void ixgbe_add_uc_addr(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq) * manually putting the device into promiscuous mode. **/ int32_t ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *addr_list, - uint32_t addr_count, ixgbe_mc_addr_itr next) + uint32_t addr_count, ixgbe_mc_addr_itr next) { uint8_t *addr; uint32_t i; @@ -1853,7 +1853,7 @@ void ixgbe_set_mta(struct ixgbe_hw *hw, uint8_t *mc_addr) * multicast table. **/ int32_t ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *mc_addr_list, - uint32_t mc_addr_count, ixgbe_mc_addr_itr next) + uint32_t mc_addr_count, ixgbe_mc_addr_itr next) { uint32_t i; uint32_t vmdq; @@ -1882,7 +1882,7 @@ int32_t ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *mc_addr_ if (hw->addr_ctrl.mta_in_use > 0) IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, - IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); + IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); return IXGBE_SUCCESS; @@ -1900,7 +1900,7 @@ int32_t ixgbe_enable_mc_generic(struct ixgbe_hw *hw) if (a->mta_in_use > 0) IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | - hw->mac.mc_filter_type); + hw->mac.mc_filter_type); return IXGBE_SUCCESS; } @@ -2267,7 +2267,7 @@ int32_t ixgbe_setup_fc(struct ixgbe_hw *hw, int32_t packetbuf_num) /* Validate the packetbuf configuration */ if (packetbuf_num < 0 || packetbuf_num > 7) { DEBUGOUT1("Invalid packet buffer number [%d], expected range is" - " 0-7\n", packetbuf_num); + " 0-7\n", packetbuf_num); ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; goto out; } @@ -2649,7 +2649,7 @@ uint32_t ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) if (hw->mac.msix_vectors_from_pcie) { msix_count = IXGBE_READ_PCIE_WORD(hw, - IXGBE_PCIE_MSIX_82599_CAPS); + IXGBE_PCIE_MSIX_82599_CAPS); msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; /* MSI-X count is zero-based in HW, so increment to give @@ -2876,7 +2876,7 @@ int32_t ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, uint32_t vlan) * Turn on/off specified VLAN in the VLAN filter table. **/ int32_t ixgbe_set_vfta_generic(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind, - int vlan_on) + int vlan_on) { int32_t regindex; uint32_t bitindex; @@ -3041,7 +3041,7 @@ int32_t ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) * Reads the links register to determine if link is up and the current speed **/ int32_t ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, - int *link_up, int link_up_wait_to_complete) + int *link_up, int link_up_wait_to_complete) { uint32_t links_reg, links_orig; uint32_t i; @@ -3053,7 +3053,7 @@ int32_t ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *spee if (links_orig != links_reg) { DEBUGOUT2("LINKS changed from %08X to %08X\n", - links_orig, links_reg); + links_orig, links_reg); } if (link_up_wait_to_complete) { @@ -3078,10 +3078,10 @@ int32_t ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *spee IXGBE_LINKS_SPEED_10G_82599) *speed = IXGBE_LINK_SPEED_10GB_FULL; else if ((links_reg & IXGBE_LINKS_SPEED_82599) == - IXGBE_LINKS_SPEED_1G_82599) + IXGBE_LINKS_SPEED_1G_82599) *speed = IXGBE_LINK_SPEED_1GB_FULL; else if ((links_reg & IXGBE_LINKS_SPEED_82599) == - IXGBE_LINKS_SPEED_100_82599) + IXGBE_LINKS_SPEED_100_82599) *speed = IXGBE_LINK_SPEED_100_FULL; else *speed = IXGBE_LINK_SPEED_UNKNOWN; @@ -3151,7 +3151,7 @@ void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) for (i = 0; i < hw->mac.max_rx_queues; i++) { regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN | - IXGBE_DCA_RXCTRL_DESC_HSRO_EN); + IXGBE_DCA_RXCTRL_DESC_HSRO_EN); IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); } @@ -3368,7 +3368,7 @@ out: * received an ack to that message within delay * timeout period **/ int32_t ixgbe_write_posted_mbx(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t mbx_id) + uint16_t mbx_id) { struct ixgbe_mbx_info *mbx = &hw->mbx; int32_t ret_val = IXGBE_ERR_MBX; @@ -3500,7 +3500,7 @@ int32_t ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, uint16_t mbx_id) DEBUGFUNC("ixgbe_check_for_rst_vf"); if (!ixgbe_check_for_bit_vf(hw, (IXGBE_VFMAILBOX_RSTD | - IXGBE_VFMAILBOX_RSTI))) { + IXGBE_VFMAILBOX_RSTI))) { ret_val = IXGBE_SUCCESS; hw->mbx.stats.rsts++; } @@ -3540,7 +3540,7 @@ int32_t ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw) * returns SUCCESS if it successfully copied message into the buffer **/ int32_t ixgbe_write_mbx_vf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t mbx_id) + uint16_t mbx_id) { int32_t ret_val; uint16_t i; @@ -3582,7 +3582,7 @@ out_no_write: * returns SUCCESS if it successfuly read message from buffer **/ int32_t ixgbe_read_mbx_vf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t mbx_id) + uint16_t mbx_id) { int32_t ret_val = IXGBE_SUCCESS; uint16_t i; @@ -3670,7 +3670,7 @@ int32_t ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, uint16_t vf_number) DEBUGFUNC("ixgbe_check_for_msg_pf"); if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFREQ_VF1 << vf_bit, - index)) { + index)) { ret_val = IXGBE_SUCCESS; hw->mbx.stats.reqs++; } @@ -3694,7 +3694,7 @@ int32_t ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, uint16_t vf_number) DEBUGFUNC("ixgbe_check_for_ack_pf"); if (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFACK_VF1 << vf_bit, - index)) { + index)) { ret_val = IXGBE_SUCCESS; hw->mbx.stats.acks++; } @@ -3772,7 +3772,7 @@ int32_t ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, uint16_t vf_number) * returns SUCCESS if it successfully copied message into the buffer **/ int32_t ixgbe_write_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t vf_number) + uint16_t vf_number) { int32_t ret_val; uint16_t i; @@ -3815,7 +3815,7 @@ out_no_write: * a message due to a VF request so no polling for message is needed. **/ int32_t ixgbe_read_mbx_pf(struct ixgbe_hw *hw, uint32_t *msg, uint16_t size, - uint16_t vf_number) + uint16_t vf_number) { int32_t ret_val; uint16_t i; @@ -3873,4 +3873,3 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw) mbx->stats.acks = 0; mbx->stats.rsts = 0; } - diff --git a/sys/dev/pci/ixgbe.h b/sys/dev/pci/ixgbe.h index 4a649a4a8be..bd0318c8b61 100644 --- a/sys/dev/pci/ixgbe.h +++ b/sys/dev/pci/ixgbe.h @@ -1,33 +1,33 @@ -/* $OpenBSD: ixgbe.h,v 1.8 2012/01/20 14:48:49 mikeb Exp $ */ +/* $OpenBSD: ixgbe.h,v 1.9 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2008, Intel Corporation + Copyright (c) 2001-2008, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -85,7 +85,7 @@ #include <dev/pci/pcidevs.h> #include <dev/pci/ixgbe_type.h> -#define DBG 0 +#define DBG 0 #define MSGOUT(S, A, B) printf(S "\n", A, B) #define DEBUGFUNC(F) DEBUGOUT(F); #if DBG @@ -104,8 +104,8 @@ #define DEBUGOUT7(S,A,B,C,D,E,F,G) #endif -#define FALSE 0 -#define TRUE 1 +#define FALSE 0 +#define TRUE 1 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ #define PCI_COMMAND_REGISTER PCIR_COMMAND @@ -116,7 +116,7 @@ #define msec_delay(x) delay(1000 * (x)) /* This is needed by the shared code */ -struct ixgbe_hw; +struct ixgbe_hw; struct ixgbe_osdep { bus_dma_tag_t os_dmat; @@ -166,7 +166,7 @@ int32_t ixgbe_start_hw_gen2(struct ixgbe_hw *hw); int32_t ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw); int32_t ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, uint32_t *pba_num); int32_t ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, uint8_t *pba_num, - uint32_t pba_num_size); + uint32_t pba_num_size); int32_t ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, uint32_t *pba_num_size); int32_t ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *mac_addr); int32_t ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); @@ -181,22 +181,22 @@ int32_t ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_ int32_t ixgbe_read_eerd_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t *data); int32_t ixgbe_write_eewr_generic(struct ixgbe_hw *hw, uint16_t offset, uint16_t data); int32_t ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, uint16_t offset, - uint16_t *data); + uint16_t *data); uint16_t ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw); int32_t ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, - uint16_t *checksum_val); + uint16_t *checksum_val); int32_t ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw); int32_t ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, uint32_t ee_reg); int32_t ixgbe_set_rar_generic(struct ixgbe_hw *hw, uint32_t index, uint8_t *addr, uint32_t vmdq, - uint32_t enable_addr); + uint32_t enable_addr); int32_t ixgbe_clear_rar_generic(struct ixgbe_hw *hw, uint32_t index); int32_t ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw); int32_t ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *mc_addr_list, - uint32_t mc_addr_count, - ixgbe_mc_addr_itr func); + uint32_t mc_addr_count, + ixgbe_mc_addr_itr func); int32_t ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, uint8_t *addr_list, - uint32_t addr_count, ixgbe_mc_addr_itr func); + uint32_t addr_count, ixgbe_mc_addr_itr func); int32_t ixgbe_enable_mc_generic(struct ixgbe_hw *hw); int32_t ixgbe_disable_mc_generic(struct ixgbe_hw *hw); int32_t ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, uint32_t regval); @@ -221,15 +221,15 @@ int32_t ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmd int32_t ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *addr, uint32_t vmdq); int32_t ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw); int32_t ixgbe_set_vfta_generic(struct ixgbe_hw *hw, uint32_t vlan, - uint32_t vind, int vlan_on); + uint32_t vind, int vlan_on); int32_t ixgbe_clear_vfta_generic(struct ixgbe_hw *hw); int32_t ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *link_up, int link_up_wait_to_complete); + ixgbe_link_speed *speed, + int *link_up, int link_up_wait_to_complete); int32_t ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, uint16_t *wwnn_prefix, - uint16_t *wwpn_prefix); + uint16_t *wwpn_prefix); int32_t ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, uint16_t *bs); void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, int enable, int pf); @@ -245,10 +245,10 @@ int32_t ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); int32_t ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, uint32_t pballoc); int32_t ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, uint32_t pballoc); int32_t ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, - union ixgbe_atr_input *input, - struct ixgbe_atr_input_masks *masks, - uint16_t soft_id, - uint8_t queue); + union ixgbe_atr_input *input, + struct ixgbe_atr_input_masks *masks, + uint16_t soft_id, + uint8_t queue); uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *input, uint32_t key); int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw); @@ -262,42 +262,42 @@ int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw); int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw); int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw); int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, - uint32_t device_type, uint16_t *phy_data); + uint32_t device_type, uint16_t *phy_data); int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, - uint32_t device_type, uint16_t phy_data); + uint32_t device_type, uint16_t phy_data); int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw); int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete); + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete); int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *autoneg); + ixgbe_link_speed *speed, + int *autoneg); /* PHY specific */ int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *link_up); + ixgbe_link_speed *speed, + int *link_up); int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw); int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, - uint16_t *firmware_version); + uint16_t *firmware_version); int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, - uint16_t *firmware_version); + uint16_t *firmware_version); int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw); int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, - uint16_t *list_offset, - uint16_t *data_offset); + uint16_t *list_offset, + uint16_t *data_offset); int32_t ixgbe_tn_check_overtemp(struct ixgbe_hw *hw); int32_t ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t dev_addr, uint8_t *data); + uint8_t dev_addr, uint8_t *data); int32_t ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t dev_addr, uint8_t data); + uint8_t dev_addr, uint8_t data); int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t *eeprom_data); + uint8_t *eeprom_data); int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t eeprom_data); + uint8_t eeprom_data); /* MBX */ int32_t ixgbe_read_mbx(struct ixgbe_hw *, uint32_t *, uint16_t, uint16_t); diff --git a/sys/dev/pci/ixgbe_82598.c b/sys/dev/pci/ixgbe_82598.c index 2202d54d42a..4dcc3b7ddc9 100644 --- a/sys/dev/pci/ixgbe_82598.c +++ b/sys/dev/pci/ixgbe_82598.c @@ -1,33 +1,33 @@ -/* $OpenBSD: ixgbe_82598.c,v 1.6 2011/06/10 12:46:35 claudio Exp $ */ +/* $OpenBSD: ixgbe_82598.c,v 1.7 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2009, Intel Corporation + Copyright (c) 2001-2009, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -40,36 +40,36 @@ uint32_t ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw); int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw); int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *autoneg); + ixgbe_link_speed *speed, + int *autoneg); enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw); int32_t ixgbe_fc_enable_82598(struct ixgbe_hw *hw, int32_t packetbuf_num); int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, - int autoneg_wait_to_complete); + int autoneg_wait_to_complete); int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw); int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *link_up, int link_up_wait_to_complete); + ixgbe_link_speed *speed, + int *link_up, int link_up_wait_to_complete); int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete); + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete); int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete); + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete); int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw); int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw); void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw); int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq); int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq); int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan, - uint32_t vind, int vlan_on); + uint32_t vind, int vlan_on); int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw); int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val); int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val); int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t *eeprom_data); + uint8_t *eeprom_data); uint32_t ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw); int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw); void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw); @@ -130,7 +130,7 @@ uint32_t ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw) if (hw->mac.msix_vectors_from_pcie) { msix_count = IXGBE_READ_PCIE_WORD(hw, - IXGBE_PCIE_MSIX_82598_CAPS); + IXGBE_PCIE_MSIX_82598_CAPS); msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; /* MSI-X count is zero-based in HW, so increment to give @@ -165,7 +165,7 @@ int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw) mac->ops.reset_hw = &ixgbe_reset_hw_82598; mac->ops.get_media_type = &ixgbe_get_media_type_82598; mac->ops.get_supported_physical_layer = - &ixgbe_get_supported_physical_layer_82598; + &ixgbe_get_supported_physical_layer_82598; mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598; mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598; mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598; @@ -195,7 +195,7 @@ int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw) mac->ops.setup_link = &ixgbe_setup_mac_link_82598; mac->ops.flap_tx_laser = NULL; mac->ops.get_link_capabilities = - &ixgbe_get_link_capabilities_82598; + &ixgbe_get_link_capabilities_82598; return ret_val; } @@ -223,7 +223,7 @@ int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { mac->ops.setup_link = &ixgbe_setup_copper_link_82598; mac->ops.get_link_capabilities = - &ixgbe_get_copper_link_capabilities_generic; + &ixgbe_get_copper_link_capabilities_generic; } switch (hw->phy.type) { @@ -231,11 +231,11 @@ int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; phy->ops.check_link = &ixgbe_check_phy_link_tnx; phy->ops.get_firmware_version = - &ixgbe_get_phy_firmware_version_tnx; + &ixgbe_get_phy_firmware_version_tnx; break; case ixgbe_phy_aq: phy->ops.get_firmware_version = - &ixgbe_get_phy_firmware_version_generic; + &ixgbe_get_phy_firmware_version_generic; break; case ixgbe_phy_nl: phy->ops.reset = &ixgbe_reset_phy_nl; @@ -251,8 +251,8 @@ int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw) /* Check to see if SFP+ module is supported */ ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, - &list_offset, - &data_offset); + &list_offset, + &data_offset); if (ret_val != IXGBE_SUCCESS) { ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED; goto out; @@ -293,7 +293,7 @@ int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw) (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | - IXGBE_DCA_RXCTRL_DESC_HSRO_EN); + IXGBE_DCA_RXCTRL_DESC_HSRO_EN); IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); } @@ -313,8 +313,8 @@ int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw) * Determines the link capabilities by reading the AUTOC register. **/ int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *autoneg) + ixgbe_link_speed *speed, + int *autoneg) { int32_t status = IXGBE_SUCCESS; uint32_t autoc = 0; @@ -555,7 +555,7 @@ out: * Restarts the link. Performs autonegotiation if needed. **/ int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, - int autoneg_wait_to_complete) + int autoneg_wait_to_complete) { uint32_t autoc_reg; uint32_t links_reg; @@ -611,7 +611,7 @@ int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw) for (timeout = 0; timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) { hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg); if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) && (an_reg & IXGBE_MII_AUTONEG_LINK_UP)) @@ -638,7 +638,7 @@ int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw) * Reads the links register to determine if link is up and the current speed **/ int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, - int *link_up, int link_up_wait_to_complete) + int *link_up, int link_up_wait_to_complete) { uint32_t links_reg; uint32_t i; @@ -654,7 +654,7 @@ int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg); hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV, - &adapt_comp_reg); + &adapt_comp_reg); if (link_up_wait_to_complete) { for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { if ((link_reg & 1) && @@ -666,11 +666,11 @@ int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed, } msec_delay(100); hw->phy.ops.read_reg(hw, 0xC79F, - IXGBE_TWINAX_DEV, - &link_reg); + IXGBE_TWINAX_DEV, + &link_reg); hw->phy.ops.read_reg(hw, 0xC00C, - IXGBE_TWINAX_DEV, - &adapt_comp_reg); + IXGBE_TWINAX_DEV, + &adapt_comp_reg); } } else { if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0)) @@ -730,8 +730,8 @@ out: * Set the link speed in the AUTOC register and restarts link. **/ int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, - ixgbe_link_speed speed, int autoneg, - int autoneg_wait_to_complete) + ixgbe_link_speed speed, int autoneg, + int autoneg_wait_to_complete) { int32_t status = IXGBE_SUCCESS; ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; @@ -748,7 +748,7 @@ int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, /* Set KX4/KX support according to speed requested */ else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN || - link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { + link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) { autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK; if (speed & IXGBE_LINK_SPEED_10GB_FULL) autoc |= IXGBE_AUTOC_KX4_SUPP; @@ -765,7 +765,7 @@ int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, * stored values */ status = ixgbe_start_mac_link_82598(hw, - autoneg_wait_to_complete); + autoneg_wait_to_complete); } return status; @@ -782,15 +782,15 @@ int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw, * Sets the link speed in the AUTOC register in the MAC and restarts link. **/ int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete) + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete) { int32_t status; /* Setup the PHY according to input speed */ status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, - autoneg_wait_to_complete); + autoneg_wait_to_complete); /* Set up MAC */ ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete); @@ -827,28 +827,28 @@ int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw) if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) { /* Enable Tx Atlas so packets can be transmitted again */ hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, - &analog_val); + &analog_val); analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN; hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, - analog_val); + analog_val); hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, - &analog_val); + &analog_val); analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL; hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, - analog_val); + analog_val); hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, - &analog_val); + &analog_val); analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL; hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, - analog_val); + analog_val); hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, - &analog_val); + &analog_val); analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL; hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, - analog_val); + analog_val); } /* Reset PHY */ @@ -1003,7 +1003,7 @@ int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq) * Turn on/off specified VLAN in the VLAN filter table. **/ int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind, - int vlan_on) + int vlan_on) { uint32_t regindex; uint32_t bitindex; @@ -1058,7 +1058,7 @@ int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw) for (vlanbyte = 0; vlanbyte < 4; vlanbyte++) for (offset = 0; offset < hw->mac.vft_size; offset++) IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset), - 0); + 0); return IXGBE_SUCCESS; } @@ -1076,7 +1076,7 @@ int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t uint32_t atlas_ctl; IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, - IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); + IXGBE_ATLASCTL_WRITE_CMD | (reg << 8)); IXGBE_WRITE_FLUSH(hw); usec_delay(10); atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); @@ -1114,7 +1114,7 @@ int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t * Performs 8 byte read operation to SFP module's EEPROM over I2C interface. **/ int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t *eeprom_data) + uint8_t *eeprom_data) { int32_t status = IXGBE_SUCCESS; uint16_t sfp_addr = 0; @@ -1131,16 +1131,16 @@ int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset, sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset; sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK); hw->phy.ops.write_reg(hw, - IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - sfp_addr); + IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR, + IXGBE_MDIO_PMA_PMD_DEV_TYPE, + sfp_addr); /* Poll status */ for (i = 0; i < 100; i++) { hw->phy.ops.read_reg(hw, - IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - &sfp_stat); + IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT, + IXGBE_MDIO_PMA_PMD_DEV_TYPE, + &sfp_stat); sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK; if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS) break; @@ -1155,7 +1155,7 @@ int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset, /* Read data */ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); + IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data); *eeprom_data = (uint8_t)(sfp_data >> 8); } else { @@ -1323,7 +1323,7 @@ void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw) (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) { regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN | - IXGBE_DCA_RXCTRL_DESC_HSRO_EN); + IXGBE_DCA_RXCTRL_DESC_HSRO_EN); IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); } diff --git a/sys/dev/pci/ixgbe_82599.c b/sys/dev/pci/ixgbe_82599.c index f6c90d87a04..ee12b1f856f 100644 --- a/sys/dev/pci/ixgbe_82599.c +++ b/sys/dev/pci/ixgbe_82599.c @@ -1,33 +1,33 @@ -/* $OpenBSD: ixgbe_82599.c,v 1.3 2011/06/10 12:46:35 claudio Exp $ */ +/* $OpenBSD: ixgbe_82599.c,v 1.4 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2009, Intel Corporation + Copyright (c) 2001-2009, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -39,28 +39,28 @@ int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw); int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *autoneg); + ixgbe_link_speed *speed, + int *autoneg); enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, - ixgbe_link_speed speed, int autoneg, - int autoneg_wait_to_complete); + ixgbe_link_speed speed, int autoneg, + int autoneg_wait_to_complete); int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, ixgbe_link_speed speed, int autoneg, int autoneg_wait_to_complete); int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, int autoneg_wait_to_complete); int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete); + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete); int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete); + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete); int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw); @@ -77,9 +77,9 @@ int ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); uint32_t ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, union ixgbe_atr_hash_dword common); int32_t ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, - union ixgbe_atr_hash_dword input, - union ixgbe_atr_hash_dword common, - uint8_t queue); + union ixgbe_atr_hash_dword input, + union ixgbe_atr_hash_dword common, + uint8_t queue); uint32_t ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks); void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) @@ -91,9 +91,9 @@ void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) /* enable the laser control functions for SFP+ fiber */ if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) { mac->ops.disable_tx_laser = - &ixgbe_disable_tx_laser_multispeed_fiber; + &ixgbe_disable_tx_laser_multispeed_fiber; mac->ops.enable_tx_laser = - &ixgbe_enable_tx_laser_multispeed_fiber; + &ixgbe_enable_tx_laser_multispeed_fiber; mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; } else { @@ -148,7 +148,7 @@ int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { mac->ops.setup_link = &ixgbe_setup_copper_link_82599; mac->ops.get_link_capabilities = - &ixgbe_get_copper_link_capabilities_generic; + &ixgbe_get_copper_link_capabilities_generic; } /* Set necessary function pointers based on phy type */ @@ -157,11 +157,11 @@ int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) phy->ops.setup_link = &ixgbe_setup_phy_link_tnx; phy->ops.check_link = &ixgbe_check_phy_link_tnx; phy->ops.get_firmware_version = - &ixgbe_get_phy_firmware_version_tnx; + &ixgbe_get_phy_firmware_version_tnx; break; case ixgbe_phy_aq: phy->ops.get_firmware_version = - &ixgbe_get_phy_firmware_version_generic; + &ixgbe_get_phy_firmware_version_generic; break; default: break; @@ -185,7 +185,7 @@ int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) hw->phy.ops.reset = NULL; ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, - &data_offset); + &data_offset); if (ret_val != IXGBE_SUCCESS) goto setup_sfp_out; @@ -210,8 +210,8 @@ int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) /* Now restart DSP by setting Restart_AN and clearing LMS */ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw, - IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | - IXGBE_AUTOC_AN_RESTART)); + IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) | + IXGBE_AUTOC_AN_RESTART)); /* Wait for AN to leave state 0 */ for (i = 0; i < 10; i++) { @@ -228,8 +228,8 @@ int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) /* Restart DSP by setting Restart_AN and return to SFI mode */ IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw, - IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | - IXGBE_AUTOC_AN_RESTART)); + IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL | + IXGBE_AUTOC_AN_RESTART)); } setup_sfp_out: @@ -264,7 +264,7 @@ int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw) mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; mac->ops.get_media_type = &ixgbe_get_media_type_82599; mac->ops.get_supported_physical_layer = - &ixgbe_get_supported_physical_layer_82599; + &ixgbe_get_supported_physical_layer_82599; mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599; mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599; mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599; @@ -319,8 +319,8 @@ int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw) * Determines the link capabilities by reading the AUTOC register. **/ int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *negotiation) + ixgbe_link_speed *speed, + int *negotiation) { int32_t status = IXGBE_SUCCESS; uint32_t autoc = 0; @@ -402,7 +402,7 @@ int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, if (hw->phy.multispeed_fiber) { *speed |= IXGBE_LINK_SPEED_10GB_FULL | - IXGBE_LINK_SPEED_1GB_FULL; + IXGBE_LINK_SPEED_1GB_FULL; *negotiation = TRUE; } @@ -468,7 +468,7 @@ out: * Restarts the link. Performs autonegotiation if needed. **/ int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, - int autoneg_wait_to_complete) + int autoneg_wait_to_complete) { uint32_t autoc_reg; uint32_t links_reg; @@ -582,8 +582,8 @@ void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) * Set the link speed in the AUTOC register and restarts link. **/ int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, - ixgbe_link_speed speed, int autoneg, - int autoneg_wait_to_complete) + ixgbe_link_speed speed, int autoneg, + int autoneg_wait_to_complete) { int32_t status = IXGBE_SUCCESS; ixgbe_link_speed link_speed; @@ -648,7 +648,7 @@ int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, /* If we have link, just jump out */ status = ixgbe_hw(hw, check_link, &link_speed, - &link_up, FALSE); + &link_up, FALSE); if (status != IXGBE_SUCCESS) return status; @@ -708,7 +708,7 @@ int32_t ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, */ if (speedcnt > 1) status = ixgbe_setup_mac_link_multispeed_fiber(hw, - highest_link_speed, autoneg, autoneg_wait_to_complete); + highest_link_speed, autoneg, autoneg_wait_to_complete); out: /* Set autoneg_advertised value based on input link speed */ @@ -846,8 +846,8 @@ out: * Set the link speed in the AUTOC register and restarts link. **/ int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, - ixgbe_link_speed speed, int autoneg, - int autoneg_wait_to_complete) + ixgbe_link_speed speed, int autoneg, + int autoneg_wait_to_complete) { int32_t status = IXGBE_SUCCESS; uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); @@ -895,8 +895,8 @@ int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, if (speed & IXGBE_LINK_SPEED_1GB_FULL) autoc |= IXGBE_AUTOC_KX_SUPP; } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && - (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || - link_mode == IXGBE_AUTOC_LMS_1G_AN)) { + (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || + link_mode == IXGBE_AUTOC_LMS_1G_AN)) { /* Switch from 1G SFI to 10G SFI if requested */ if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { @@ -904,7 +904,7 @@ int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; } } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && - (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { + (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { /* Switch from 10G SFI to 1G SFI if requested */ if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { @@ -960,9 +960,9 @@ out: * Restarts link on PHY and MAC based on settings passed in. **/ int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete) + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete) { int32_t status; @@ -970,7 +970,7 @@ int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, /* Setup the PHY according to input speed */ status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, - autoneg_wait_to_complete); + autoneg_wait_to_complete); /* Set up MAC */ ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); @@ -1080,7 +1080,7 @@ mac_reset_top: (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; autoc2 |= (hw->mac.orig_autoc2 & - IXGBE_AUTOC2_UPPER_MASK); + IXGBE_AUTOC2_UPPER_MASK); IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); } } @@ -1103,7 +1103,7 @@ mac_reset_top: /* Add the SAN MAC address to the RAR only if it's a valid address */ if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, - hw->mac.san_addr, 0, IXGBE_RAH_AV); + hw->mac.san_addr, 0, IXGBE_RAH_AV); /* Reserve the last RAR for the SAN MAC address */ hw->mac.num_rar_entries--; @@ -1111,7 +1111,7 @@ mac_reset_top: /* Store the alternative WWNN/WWPN prefix */ hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, - &hw->mac.wwpn_prefix); + &hw->mac.wwpn_prefix); #endif reset_hw_out: return status; @@ -1141,7 +1141,7 @@ int32_t ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) } if (i >= IXGBE_FDIRCMD_CMD_POLL) { DEBUGOUT("Flow Director previous command isn't complete, " - "aborting table re-initialization. \n"); + "aborting table re-initialization. \n"); return IXGBE_ERR_FDIR_REINIT_FAILED; } @@ -1155,12 +1155,12 @@ int32_t ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) * - write 0 to bit 8 of FDIRCMD register */ IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, - (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | - IXGBE_FDIRCMD_CLEARHT)); + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | + IXGBE_FDIRCMD_CLEARHT)); IXGBE_WRITE_FLUSH(hw); IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, - (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & - ~IXGBE_FDIRCMD_CLEARHT)); + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & + ~IXGBE_FDIRCMD_CLEARHT)); IXGBE_WRITE_FLUSH(hw); /* * Clear FDIR Hash register to clear any leftover hashes @@ -1175,7 +1175,7 @@ int32_t ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) /* Poll init-done after we write FDIRCTRL register */ for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & - IXGBE_FDIRCTRL_INIT_DONE) + IXGBE_FDIRCTRL_INIT_DONE) break; usec_delay(10); } @@ -1274,7 +1274,7 @@ int32_t ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, uint32_t pballoc) IXGBE_WRITE_FLUSH(hw); for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & - IXGBE_FDIRCTRL_INIT_DONE) + IXGBE_FDIRCTRL_INIT_DONE) break; msec_delay(1); } @@ -1371,7 +1371,7 @@ int32_t ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, uint32_t pballoc) IXGBE_WRITE_FLUSH(hw); for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & - IXGBE_FDIRCTRL_INIT_DONE) + IXGBE_FDIRCTRL_INIT_DONE) break; msec_delay(1); } @@ -1387,7 +1387,7 @@ int32_t ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, uint32_t pballoc) * @key: 32-bit hash key **/ uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input, - uint32_t key) + uint32_t key) { /* * The algorithm is as follows: @@ -1568,9 +1568,9 @@ uint32_t ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input, * @queue: queue index to direct traffic to **/ int32_t ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, - union ixgbe_atr_hash_dword input, - union ixgbe_atr_hash_dword common, - uint8_t queue) + union ixgbe_atr_hash_dword input, + union ixgbe_atr_hash_dword common, + uint8_t queue) { uint64_t fdirhashcmd; uint64_t fdircmd; @@ -1596,7 +1596,7 @@ int32_t ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, /* configure FDIRCMD register */ fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | - IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; + IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN; fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; @@ -1662,9 +1662,9 @@ uint32_t ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks) * hardware writes must be protected from one another. **/ int32_t ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, - union ixgbe_atr_input *input, - struct ixgbe_atr_input_masks *input_masks, - uint16_t soft_id, uint8_t queue) + union ixgbe_atr_input *input, + struct ixgbe_atr_input_masks *input_masks, + uint16_t soft_id, uint8_t queue) { uint32_t fdirhash; uint32_t fdircmd; @@ -1812,7 +1812,7 @@ int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, uint8_t DEBUGFUNC("ixgbe_read_analog_reg8_82599"); IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | - (reg << 8)); + (reg << 8)); IXGBE_WRITE_FLUSH(hw); usec_delay(10); core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); @@ -2084,7 +2084,7 @@ int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval) /* For informational purposes only */ if (i >= IXGBE_MAX_SECRX_POLL) DEBUGOUT("Rx unit being enabled before security " - "path fully disabled. Continuing with init.\n"); + "path fully disabled. Continuing with init.\n"); IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); @@ -2127,16 +2127,16 @@ int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) /* get the offset to the Pass Through Patch Configuration block */ hw->eeprom.ops.read(hw, (fw_offset + - IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), - &fw_ptp_cfg_offset); + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), + &fw_ptp_cfg_offset); if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) goto fw_version_out; /* get the firmware version */ hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + - IXGBE_FW_PATCH_VERSION_4), - &fw_version); + IXGBE_FW_PATCH_VERSION_4), + &fw_version); if (fw_version > 0x5) status = IXGBE_SUCCESS; @@ -2169,8 +2169,8 @@ int ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) /* get the offset to the LESM Parameters block */ status = hw->eeprom.ops.read(hw, (fw_offset + - IXGBE_FW_LESM_PARAMETERS_PTR), - &fw_lesm_param_offset); + IXGBE_FW_LESM_PARAMETERS_PTR), + &fw_lesm_param_offset); if ((status != IXGBE_SUCCESS) || (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) @@ -2178,8 +2178,8 @@ int ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) /* get the lesm state word */ status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + - IXGBE_FW_LESM_STATE_1), - &fw_lesm_state); + IXGBE_FW_LESM_STATE_1), + &fw_lesm_state); if ((status == IXGBE_SUCCESS) && (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) @@ -2188,5 +2188,3 @@ int ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) out: return lesm_enabled; } - - diff --git a/sys/dev/pci/ixgbe_phy.c b/sys/dev/pci/ixgbe_phy.c index 7bfcd7ff9b7..c52a7a4a4e6 100644 --- a/sys/dev/pci/ixgbe_phy.c +++ b/sys/dev/pci/ixgbe_phy.c @@ -1,33 +1,33 @@ -/* $OpenBSD: ixgbe_phy.c,v 1.6 2011/06/10 12:46:35 claudio Exp $ */ +/* $OpenBSD: ixgbe_phy.c,v 1.7 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2009, Intel Corporation + Copyright (c) 2001-2009, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -97,21 +97,21 @@ int32_t ixgbe_identify_phy_generic(struct ixgbe_hw *hw) hw->phy.addr = phy_addr; ixgbe_get_phy_id(hw); hw->phy.type = - ixgbe_get_phy_type_from_id(hw->phy.id); + ixgbe_get_phy_type_from_id(hw->phy.id); if (hw->phy.type == ixgbe_phy_unknown) { hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - &ext_ability); + IXGBE_MDIO_PMA_PMD_DEV_TYPE, + &ext_ability); if (ext_ability & (IXGBE_MDIO_PHY_10GBASET_ABILITY | IXGBE_MDIO_PHY_1000BASET_ABILITY)) hw->phy.type = - ixgbe_phy_cu_unknown; + ixgbe_phy_cu_unknown; else hw->phy.type = - ixgbe_phy_generic; + ixgbe_phy_generic; } status = IXGBE_SUCCESS; @@ -140,7 +140,7 @@ int ixgbe_validate_phy_addr(struct ixgbe_hw *hw, uint32_t phy_addr) hw->phy.addr = phy_addr; hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); + IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); if (phy_id != 0xFFFF && phy_id != 0x0) valid = TRUE; @@ -160,14 +160,14 @@ int32_t ixgbe_get_phy_id(struct ixgbe_hw *hw) uint16_t phy_id_low = 0; status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - &phy_id_high); + IXGBE_MDIO_PMA_PMD_DEV_TYPE, + &phy_id_high); if (status == IXGBE_SUCCESS) { hw->phy.id = (uint32_t)(phy_id_high << 16); status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - &phy_id_low); + IXGBE_MDIO_PMA_PMD_DEV_TYPE, + &phy_id_low); hw->phy.id |= (uint32_t)(phy_id_low & IXGBE_PHY_REVISION_MASK); hw->phy.revision = (uint32_t)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); } @@ -231,8 +231,8 @@ int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw) * This will cause a soft reset to the PHY */ hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, - IXGBE_MDIO_PHY_XS_DEV_TYPE, - IXGBE_MDIO_PHY_XS_RESET); + IXGBE_MDIO_PHY_XS_DEV_TYPE, + IXGBE_MDIO_PHY_XS_RESET); /* * Poll for reset bit to self-clear indicating reset is complete. @@ -242,7 +242,7 @@ int32_t ixgbe_reset_phy_generic(struct ixgbe_hw *hw) for (i = 0; i < 30; i++) { msec_delay(100); hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, - IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); + IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { usec_delay(2); break; @@ -265,7 +265,7 @@ out: * @phy_data: Pointer to read data from PHY register **/ int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, - uint32_t device_type, uint16_t *phy_data) + uint32_t device_type, uint16_t *phy_data) { uint32_t command; uint32_t i; @@ -284,9 +284,9 @@ int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, if (status == IXGBE_SUCCESS) { /* Setup and write the address cycle command */ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | - (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | + (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); @@ -315,9 +315,9 @@ int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, * command */ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | - (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | + (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); @@ -363,7 +363,7 @@ int32_t ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, * @phy_data: Data to write to the PHY register **/ int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, - uint32_t device_type, uint16_t phy_data) + uint32_t device_type, uint16_t phy_data) { uint32_t command; uint32_t i; @@ -384,9 +384,9 @@ int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, /* Setup and write the address cycle command */ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | - (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | + (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); @@ -415,9 +415,9 @@ int32_t ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, uint32_t reg_addr, * command */ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | - (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | + (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); @@ -468,66 +468,66 @@ int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) if (speed & IXGBE_LINK_SPEED_10GB_FULL) { /* Set or unset auto-negotiation 10G advertisement */ hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + autoneg_reg); } if (speed & IXGBE_LINK_SPEED_1GB_FULL) { /* Set or unset auto-negotiation 1G advertisement */ hw->phy.ops.read_reg(hw, - IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; hw->phy.ops.write_reg(hw, - IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - autoneg_reg); + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + autoneg_reg); } if (speed & IXGBE_LINK_SPEED_100_FULL) { /* Set or unset auto-negotiation 100M advertisement */ hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + autoneg_reg); } /* Restart PHY autonegotiation and wait for completion */ hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); autoneg_reg |= IXGBE_MII_RESTART; hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); /* Wait for autonegotiation to finish */ for (time_out = 0; time_out < max_time_out; time_out++) { usec_delay(10); /* Restart PHY autonegotiation and wait for completion */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { @@ -550,9 +550,9 @@ int32_t ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) * @autoneg: TRUE if autonegotiation enabled **/ int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - int autoneg, - int autoneg_wait_to_complete) + ixgbe_link_speed speed, + int autoneg, + int autoneg_wait_to_complete) { UNREFERENCED_PARAMETER(autoneg); UNREFERENCED_PARAMETER(autoneg_wait_to_complete); @@ -587,8 +587,8 @@ int32_t ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, * Determines the link capabilities by reading the AUTOC register. **/ int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - int *autoneg) + ixgbe_link_speed *speed, + int *autoneg) { int32_t status = IXGBE_ERR_LINK_SETUP; uint16_t speed_ability; @@ -597,8 +597,8 @@ int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, *autoneg = TRUE; status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, - IXGBE_MDIO_PMA_PMD_DEV_TYPE, - &speed_ability); + IXGBE_MDIO_PMA_PMD_DEV_TYPE, + &speed_ability); if (status == IXGBE_SUCCESS) { if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) @@ -620,7 +620,7 @@ int32_t ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, * the PHY. **/ int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, - int *link_up) + int *link_up) { int32_t status = IXGBE_SUCCESS; uint32_t time_out; @@ -641,13 +641,13 @@ int32_t ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, for (time_out = 0; time_out < max_time_out; time_out++) { usec_delay(10); status = hw->phy.ops.read_reg(hw, - IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, - &phy_data); + IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + &phy_data); phy_link = phy_data & - IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; + IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; phy_speed = phy_data & - IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; + IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { *link_up = TRUE; if (phy_speed == @@ -680,64 +680,64 @@ int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) if (speed & IXGBE_LINK_SPEED_10GB_FULL) { /* Set or unset auto-negotiation 10G advertisement */ hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + autoneg_reg); } if (speed & IXGBE_LINK_SPEED_1GB_FULL) { /* Set or unset auto-negotiation 1G advertisement */ hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + autoneg_reg); } if (speed & IXGBE_LINK_SPEED_100_FULL) { /* Set or unset auto-negotiation 100M advertisement */ hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + autoneg_reg); } /* Restart PHY autonegotiation and wait for completion */ hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); autoneg_reg |= IXGBE_MII_RESTART; hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); /* Wait for autonegotiation to finish */ for (time_out = 0; time_out < max_time_out; time_out++) { usec_delay(10); /* Restart PHY autonegotiation and wait for completion */ status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - &autoneg_reg); + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_reg); autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE; if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) { @@ -759,13 +759,13 @@ int32_t ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) * @firmware_version: pointer to the PHY Firmware Version **/ int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, - uint16_t *firmware_version) + uint16_t *firmware_version) { int32_t status = IXGBE_SUCCESS; status = hw->phy.ops.read_reg(hw, TNX_FW_REV, - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, - firmware_version); + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + firmware_version); return status; } @@ -776,13 +776,13 @@ int32_t ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, * @firmware_version: pointer to the PHY Firmware Version **/ int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, - uint16_t *firmware_version) + uint16_t *firmware_version) { int32_t status = IXGBE_SUCCESS; status = hw->phy.ops.read_reg(hw, AQ_FW_REV, - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, - firmware_version); + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + firmware_version); return status; } @@ -793,7 +793,7 @@ int32_t ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, **/ int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) { - uint16_t phy_offset, control, eword, edata, block_crc; + uint16_t phy_offset, control, eword, edata, block_crc; int end_data = FALSE; uint16_t list_offset, data_offset; uint16_t phy_data = 0; @@ -801,16 +801,16 @@ int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) uint32_t i; hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, - IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); + IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); /* reset the PHY and poll for completion */ hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, - IXGBE_MDIO_PHY_XS_DEV_TYPE, - (phy_data | IXGBE_MDIO_PHY_XS_RESET)); + IXGBE_MDIO_PHY_XS_DEV_TYPE, + (phy_data | IXGBE_MDIO_PHY_XS_RESET)); for (i = 0; i < 100; i++) { hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, - IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); + IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) break; msec_delay(10); @@ -824,7 +824,7 @@ int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) /* Get init offsets */ ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, - &data_offset); + &data_offset); if (ret_val != IXGBE_SUCCESS) goto out; @@ -836,7 +836,7 @@ int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) */ ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); control = (eword & IXGBE_CONTROL_MASK_NL) >> - IXGBE_CONTROL_SHIFT_NL; + IXGBE_CONTROL_SHIFT_NL; edata = eword & IXGBE_DATA_MASK_NL; switch (control) { case IXGBE_DELAY_NL: @@ -848,13 +848,13 @@ int32_t ixgbe_reset_phy_nl(struct ixgbe_hw *hw) DEBUGOUT("DATA: \n"); data_offset++; hw->eeprom.ops.read(hw, data_offset++, - &phy_offset); + &phy_offset); for (i = 0; i < edata; i++) { hw->eeprom.ops.read(hw, data_offset, &eword); hw->phy.ops.write_reg(hw, phy_offset, - IXGBE_TWINAX_DEV, eword); + IXGBE_TWINAX_DEV, eword); DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, - phy_offset); + phy_offset); data_offset++; phy_offset++; } @@ -911,7 +911,7 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) } status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, - &identifier); + &identifier); if (status == IXGBE_ERR_SWFW_SYNC || status == IXGBE_ERR_I2C || @@ -926,8 +926,8 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) status = IXGBE_ERR_SFP_NOT_SUPPORTED; } else { status = hw->phy.ops.read_i2c_eeprom(hw, - IXGBE_SFF_1GBE_COMP_CODES, - &comp_codes_1g); + IXGBE_SFF_1GBE_COMP_CODES, + &comp_codes_1g); if (status == IXGBE_ERR_SWFW_SYNC || status == IXGBE_ERR_I2C || @@ -935,16 +935,16 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) goto err_read_i2c_eeprom; status = hw->phy.ops.read_i2c_eeprom(hw, - IXGBE_SFF_10GBE_COMP_CODES, - &comp_codes_10g); + IXGBE_SFF_10GBE_COMP_CODES, + &comp_codes_10g); if (status == IXGBE_ERR_SWFW_SYNC || status == IXGBE_ERR_I2C || status == IXGBE_ERR_SFP_NOT_PRESENT) goto err_read_i2c_eeprom; status = hw->phy.ops.read_i2c_eeprom(hw, - IXGBE_SFF_CABLE_TECHNOLOGY, - &cable_tech); + IXGBE_SFF_CABLE_TECHNOLOGY, + &cable_tech); if (status == IXGBE_ERR_SWFW_SYNC || status == IXGBE_ERR_I2C || @@ -980,10 +980,10 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { if (hw->bus.lan_id == 0) hw->phy.sfp_type = - ixgbe_sfp_type_da_cu_core0; + ixgbe_sfp_type_da_cu_core0; else hw->phy.sfp_type = - ixgbe_sfp_type_da_cu_core1; + ixgbe_sfp_type_da_cu_core1; } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { hw->phy.ops.read_i2c_eeprom( hw, IXGBE_SFF_CABLE_SPEC_COMP, @@ -998,17 +998,17 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) ixgbe_sfp_type_da_act_lmt_core1; } else { hw->phy.sfp_type = - ixgbe_sfp_type_unknown; + ixgbe_sfp_type_unknown; } } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | IXGBE_SFF_10GBASELR_CAPABLE)) { if (hw->bus.lan_id == 0) hw->phy.sfp_type = - ixgbe_sfp_type_srlr_core0; + ixgbe_sfp_type_srlr_core0; else hw->phy.sfp_type = - ixgbe_sfp_type_srlr_core1; + ixgbe_sfp_type_srlr_core1; } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { if (hw->bus.lan_id == 0) hw->phy.sfp_type = @@ -1036,8 +1036,8 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) if (hw->phy.type != ixgbe_phy_nl) { hw->phy.id = identifier; status = hw->phy.ops.read_i2c_eeprom(hw, - IXGBE_SFF_VENDOR_OUI_BYTE0, - &oui_bytes[0]); + IXGBE_SFF_VENDOR_OUI_BYTE0, + &oui_bytes[0]); if (status == IXGBE_ERR_SWFW_SYNC || status == IXGBE_ERR_I2C || @@ -1045,8 +1045,8 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) goto err_read_i2c_eeprom; status = hw->phy.ops.read_i2c_eeprom(hw, - IXGBE_SFF_VENDOR_OUI_BYTE1, - &oui_bytes[1]); + IXGBE_SFF_VENDOR_OUI_BYTE1, + &oui_bytes[1]); if (status == IXGBE_ERR_SWFW_SYNC || status == IXGBE_ERR_I2C || @@ -1054,8 +1054,8 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) goto err_read_i2c_eeprom; status = hw->phy.ops.read_i2c_eeprom(hw, - IXGBE_SFF_VENDOR_OUI_BYTE2, - &oui_bytes[2]); + IXGBE_SFF_VENDOR_OUI_BYTE2, + &oui_bytes[2]); if (status == IXGBE_ERR_SWFW_SYNC || status == IXGBE_ERR_I2C || @@ -1071,7 +1071,7 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) case IXGBE_SFF_VENDOR_OUI_TYCO: if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) hw->phy.type = - ixgbe_phy_sfp_passive_tyco; + ixgbe_phy_sfp_passive_tyco; break; case IXGBE_SFF_VENDOR_OUI_FTL: if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) @@ -1088,7 +1088,7 @@ int32_t ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) default: if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) hw->phy.type = - ixgbe_phy_sfp_passive_unknown; + ixgbe_phy_sfp_passive_unknown; else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) hw->phy.type = ixgbe_phy_sfp_active_unknown; @@ -1162,8 +1162,8 @@ err_read_i2c_eeprom: * so it returns the offsets to the phy init sequence block. **/ int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, - uint16_t *list_offset, - uint16_t *data_offset) + uint16_t *list_offset, + uint16_t *data_offset) { uint16_t sfp_id; uint16_t sfp_type = hw->phy.sfp_type; @@ -1248,11 +1248,11 @@ int32_t ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, * Performs byte read operation to SFP module's EEPROM over I2C interface. **/ int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t *eeprom_data) + uint8_t *eeprom_data) { return hw->phy.ops.read_i2c_byte(hw, byte_offset, - IXGBE_I2C_EEPROM_DEV_ADDR, - eeprom_data); + IXGBE_I2C_EEPROM_DEV_ADDR, + eeprom_data); } /** @@ -1264,11 +1264,11 @@ int32_t ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, * Performs byte write operation to SFP module's EEPROM over I2C interface. **/ int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t eeprom_data) + uint8_t eeprom_data) { return hw->phy.ops.write_i2c_byte(hw, byte_offset, - IXGBE_I2C_EEPROM_DEV_ADDR, - eeprom_data); + IXGBE_I2C_EEPROM_DEV_ADDR, + eeprom_data); } /** @@ -1281,7 +1281,7 @@ int32_t ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, uint8_t byte_offset, * a specified deivce address. **/ int32_t ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t dev_addr, uint8_t *data) + uint8_t dev_addr, uint8_t *data) { int32_t status = IXGBE_SUCCESS; uint32_t max_retry = 10; @@ -1369,7 +1369,7 @@ read_byte_out: * a specified device address. **/ int32_t ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, uint8_t byte_offset, - uint8_t dev_addr, uint8_t data) + uint8_t dev_addr, uint8_t data) { int32_t status = IXGBE_SUCCESS; uint32_t max_retry = 1; diff --git a/sys/dev/pci/ixgbe_type.h b/sys/dev/pci/ixgbe_type.h index c22c8019eaa..ed810845e18 100644 --- a/sys/dev/pci/ixgbe_type.h +++ b/sys/dev/pci/ixgbe_type.h @@ -1,33 +1,33 @@ -/* $OpenBSD: ixgbe_type.h,v 1.10 2011/12/09 11:41:55 mikeb Exp $ */ +/* $OpenBSD: ixgbe_type.h,v 1.11 2012/07/29 13:49:03 mikeb Exp $ */ /****************************************************************************** - Copyright (c) 2001-2009, Intel Corporation + Copyright (c) 2001-2009, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -128,7 +128,7 @@ #define IXGBE_MAX_EITR 0x00000FF8 #define IXGBE_MIN_EITR 8 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ - (0x012300 + (((_i) - 24) * 4))) + (0x012300 + (((_i) - 24) * 4))) #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 #define IXGBE_EITR_LLI_MOD 0x00008000 #define IXGBE_EITR_CNT_WDIS 0x80000000 @@ -157,19 +157,19 @@ /* Receive DMA Registers */ #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ - (0x0D000 + ((_i - 64) * 0x40))) + (0x0D000 + ((_i - 64) * 0x40))) #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ - (0x0D004 + ((_i - 64) * 0x40))) + (0x0D004 + ((_i - 64) * 0x40))) #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ - (0x0D008 + ((_i - 64) * 0x40))) + (0x0D008 + ((_i - 64) * 0x40))) #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ - (0x0D010 + ((_i - 64) * 0x40))) + (0x0D010 + ((_i - 64) * 0x40))) #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ - (0x0D018 + ((_i - 64) * 0x40))) + (0x0D018 + ((_i - 64) * 0x40))) #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ - (0x0D028 + ((_i - 64) * 0x40))) + (0x0D028 + ((_i - 64) * 0x40))) #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ - (0x0D02C + ((_i - 64) * 0x40))) + (0x0D02C + ((_i - 64) * 0x40))) #define IXGBE_RSCDBU 0x03028 #define IXGBE_RDDCC 0x02F20 #define IXGBE_RXMEMWRAP 0x03190 @@ -181,8 +181,8 @@ * 64-127: 0x0D014 + (n-64)*0x40 */ #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ - (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ - (0x0D014 + ((_i - 64) * 0x40)))) + (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ + (0x0D014 + ((_i - 64) * 0x40)))) /* * Rx DCA Control Register: * 00-15 : 0x02200 + n*4 @@ -190,12 +190,12 @@ * 64-127: 0x0D00C + (n-64)*0x40 */ #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ - (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ - (0x0D00C + ((_i - 64) * 0x40)))) + (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ + (0x0D00C + ((_i - 64) * 0x40)))) #define IXGBE_RDRXCTL 0x02F00 #define IXGBE_RDRXCTL_RSC_PUSH 0x80 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) - /* 8 of these 0x03C00 - 0x03C1C */ + /* 8 of these 0x03C00 - 0x03C1C */ #define IXGBE_RXCTRL 0x03000 #define IXGBE_DROPEN 0x03D04 #define IXGBE_RXPBSIZE_SHIFT 10 @@ -209,14 +209,14 @@ /* Multicast Table Array - 128 entries */ #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ - (0x0A200 + ((_i) * 8))) + (0x0A200 + ((_i) * 8))) #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ - (0x0A204 + ((_i) * 8))) + (0x0A204 + ((_i) * 8))) #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) /* Packet split receive type */ #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ - (0x0EA00 + ((_i) * 4))) + (0x0EA00 + ((_i) * 4))) /* array of 4096 1-bit vlan filters */ #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) /*array of 4096 4-bit vlan vmdq indices */ @@ -337,7 +337,7 @@ #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */ #define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host - * Filter Table */ + * Filter Table */ #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 @@ -664,7 +664,7 @@ #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ - (0x08600 + ((_i) * 4))) + (0x08600 + ((_i) * 4))) #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ @@ -765,7 +765,7 @@ #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ - IXGBE_GCR_EXT_VT_MODE_64) + IXGBE_GCR_EXT_VT_MODE_64) /* Time Sync Registers */ #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ @@ -1316,9 +1316,9 @@ #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ #define IXGBE_EIMS_ENABLE_MASK ( \ - IXGBE_EIMS_RTX_QUEUE | \ - IXGBE_EIMS_LSC | \ - IXGBE_EIMS_OTHER) + IXGBE_EIMS_RTX_QUEUE | \ + IXGBE_EIMS_LSC | \ + IXGBE_EIMS_OTHER) /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ @@ -1732,12 +1732,12 @@ /* Check whether address is multicast. This is little-endian specific check.*/ #define IXGBE_IS_MULTICAST(Address) \ - (int)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) + (int)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) /* Check whether an address is broadcast. */ #define IXGBE_IS_BROADCAST(Address) \ - ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && \ - (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) + ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && \ + (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) /* RAH */ #define IXGBE_RAH_VIND_MASK 0x003C0000 @@ -1980,18 +1980,18 @@ /* Masks to determine if packets should be dropped due to frame errors */ #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ - IXGBE_RXD_ERR_CE | \ - IXGBE_RXD_ERR_LE | \ - IXGBE_RXD_ERR_PE | \ - IXGBE_RXD_ERR_OSE | \ - IXGBE_RXD_ERR_USE) + IXGBE_RXD_ERR_CE | \ + IXGBE_RXD_ERR_LE | \ + IXGBE_RXD_ERR_PE | \ + IXGBE_RXD_ERR_OSE | \ + IXGBE_RXD_ERR_USE) #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ - IXGBE_RXDADV_ERR_CE | \ - IXGBE_RXDADV_ERR_LE | \ - IXGBE_RXDADV_ERR_PE | \ - IXGBE_RXDADV_ERR_OSE | \ - IXGBE_RXDADV_ERR_USE) + IXGBE_RXDADV_ERR_CE | \ + IXGBE_RXDADV_ERR_LE | \ + IXGBE_RXDADV_ERR_PE | \ + IXGBE_RXDADV_ERR_OSE | \ + IXGBE_RXDADV_ERR_USE) /* Multicast bit mask */ #define IXGBE_MCSTCTRL_MFE 0x4 @@ -2213,9 +2213,9 @@ struct ixgbe_adv_tx_context_desc { #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ - IXGBE_ADVTXD_POPTS_SHIFT) + IXGBE_ADVTXD_POPTS_SHIFT) #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ - IXGBE_ADVTXD_POPTS_SHIFT) + IXGBE_ADVTXD_POPTS_SHIFT) #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ @@ -2255,10 +2255,10 @@ typedef uint32_t ixgbe_link_speed; #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ - IXGBE_LINK_SPEED_10GB_FULL) + IXGBE_LINK_SPEED_10GB_FULL) #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ - IXGBE_LINK_SPEED_1GB_FULL | \ - IXGBE_LINK_SPEED_10GB_FULL) + IXGBE_LINK_SPEED_1GB_FULL | \ + IXGBE_LINK_SPEED_10GB_FULL) /* Physical layer type */ @@ -2652,7 +2652,7 @@ struct ixgbe_mac_operations { int32_t (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, int, int); int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, int *, int); int32_t (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, - int *); + int *); /* LED */ int32_t (*led_on)(struct ixgbe_hw *, uint32_t); @@ -2668,9 +2668,9 @@ struct ixgbe_mac_operations { int32_t (*clear_vmdq)(struct ixgbe_hw *, uint32_t, uint32_t); int32_t (*init_rx_addrs)(struct ixgbe_hw *); int32_t (*update_uc_addr_list)(struct ixgbe_hw *, uint8_t *, uint32_t, - ixgbe_mc_addr_itr); + ixgbe_mc_addr_itr); int32_t (*update_mc_addr_list)(struct ixgbe_hw *, uint8_t *, uint32_t, - ixgbe_mc_addr_itr); + ixgbe_mc_addr_itr); int32_t (*enable_mc)(struct ixgbe_hw *); int32_t (*disable_mc)(struct ixgbe_hw *); int32_t (*clear_vfta)(struct ixgbe_hw *); @@ -2692,7 +2692,7 @@ struct ixgbe_phy_operations { int32_t (*write_reg)(struct ixgbe_hw *, uint32_t, uint32_t, uint16_t); int32_t (*setup_link)(struct ixgbe_hw *); int32_t (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, int, - int); + int); int32_t (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, int *); int32_t (*get_firmware_version)(struct ixgbe_hw *, uint16_t *); int32_t (*read_i2c_byte)(struct ixgbe_hw *, uint8_t, uint8_t, uint8_t *); @@ -2796,11 +2796,11 @@ struct ixgbe_phy_info { * Message ACK's are the value or'd with 0xF0000000 */ #define IXGBE_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with - * this are the ACK */ + * this are the ACK */ #define IXGBE_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with - * this are the NACK */ + * this are the NACK */ #define IXGBE_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still - clear to send requests */ + clear to send requests */ #define IXGBE_VT_MSGINFO_SHIFT 16 /* bits 23:16 are used for exra info for certain messages */ #define IXGBE_VT_MSGINFO_MASK (0xFF << IXGBE_VT_MSGINFO_SHIFT) |