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Diffstat (limited to 'sys/arch/i386/i386/machdep.c')
-rw-r--r--sys/arch/i386/i386/machdep.c75
1 files changed, 35 insertions, 40 deletions
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c
index b3c7aabcd69..1ea794eaae8 100644
--- a/sys/arch/i386/i386/machdep.c
+++ b/sys/arch/i386/i386/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.610 2018/02/10 09:46:58 jsg Exp $ */
+/* $OpenBSD: machdep.c,v 1.611 2018/03/13 13:51:05 bluhm Exp $ */
/* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
/*-
@@ -377,16 +377,6 @@ cpu_startup(void)
printf("%s", version);
startclocks();
- /*
- * We need to call identifycpu here early, so users have at least some
- * basic information, if booting hangs later on.
- */
- strlcpy(curcpu()->ci_dev.dv_xname, "cpu0",
- sizeof(curcpu()->ci_dev.dv_xname));
- curcpu()->ci_signature = cpu_id;
- curcpu()->ci_feature_flags = cpu_feature;
- identifycpu(curcpu());
-
printf("real mem = %llu (%lluMB)\n",
(unsigned long long)ptoa((psize_t)physmem),
(unsigned long long)ptoa((psize_t)physmem)/1024U/1024U);
@@ -436,16 +426,14 @@ i386_proc0_tss_init(void)
struct pcb *pcb;
curpcb = pcb = &proc0.p_addr->u_pcb;
-
- pcb->pcb_tss.tss_ioopt = sizeof(pcb->pcb_tss) << 16;
pcb->pcb_cr0 = rcr0();
- pcb->pcb_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
- pcb->pcb_tss.tss_esp0 = (int)proc0.p_addr + USPACE - 16;
- proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_tss.tss_esp0 - 1;
- proc0.p_md.md_tss_sel = tss_alloc(pcb);
+ pcb->pcb_kstack = (int)proc0.p_addr + USPACE - 16;
+ proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_kstack - 1;
- ltr(proc0.p_md.md_tss_sel);
- lldt(0);
+ /* empty iomap */
+ cpu_info_primary.ci_tss->tss_ioopt = sizeof(struct i386tss) << 16;
+ cpu_info_primary.ci_tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
+ cpu_info_primary.ci_tss->tss_esp0 = pcb->pcb_kstack;
}
#ifdef MULTIPROCESSOR
@@ -454,9 +442,11 @@ i386_init_pcb_tss(struct cpu_info *ci)
{
struct pcb *pcb = ci->ci_idle_pcb;
- pcb->pcb_tss.tss_ioopt = sizeof(pcb->pcb_tss) << 16;
+ ci->ci_tss->tss_ioopt = sizeof(*ci->ci_tss) << 16;
+ ci->ci_tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
+ ci->ci_tss->tss_esp0 = pcb->pcb_kstack;
+
pcb->pcb_cr0 = rcr0();
- ci->ci_idle_tss_sel = tss_alloc(pcb);
}
#endif /* MULTIPROCESSOR */
@@ -1088,7 +1078,7 @@ winchip_cpu_setup(struct cpu_info *ci)
ci->ci_feature_flags &= ~CPUID_TSC;
/* Disable RDTSC instruction from user-level. */
lcr4(rcr4() | CR4_TSD);
- printf("%s: TSC disabled\n", ci->ci_dev.dv_xname);
+ printf("%s: TSC disabled\n", ci->ci_dev->dv_xname);
break;
}
}
@@ -1102,7 +1092,7 @@ cyrix3_setperf_setup(struct cpu_info *ci)
est_init(ci, CPUVENDOR_VIA);
else
printf("%s: Enhanced SpeedStep disabled by BIOS\n",
- ci->ci_dev.dv_xname);
+ ci->ci_dev->dv_xname);
}
}
#endif
@@ -1157,7 +1147,7 @@ cyrix3_cpu_setup(struct cpu_info *ci)
if (CPU_IS_PRIMARY(ci) &&
(model == 10 || model == 13 || model == 15)) {
/* Setup the sensors structures */
- strlcpy(ci->ci_sensordev.xname, ci->ci_dev.dv_xname,
+ strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname,
sizeof(ci->ci_sensordev.xname));
ci->ci_sensor.type = SENSOR_TEMP;
sensor_task_register(ci, via_update_sensor, 5);
@@ -1187,7 +1177,7 @@ cyrix3_cpu_setup(struct cpu_info *ci)
val = 0;
if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE))
- printf("%s:", ci->ci_dev.dv_xname);
+ printf("%s:", ci->ci_dev->dv_xname);
/* Enable RNG if present and disabled */
if (val & C3_CPUID_HAS_RNG) {
@@ -1305,13 +1295,13 @@ cyrix6x86_cpu_setup(struct cpu_info *ci)
cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10);
printf("%s: xchg bug workaround performed\n",
- ci->ci_dev.dv_xname);
+ ci->ci_dev->dv_xname);
break; /* fallthrough? */
case 4: /* GXm */
/* Unset the TSC bit until calibrate_delay() gets fixed. */
clock_broken_latch = 1;
curcpu()->ci_feature_flags &= ~CPUID_TSC;
- printf("%s: TSC disabled\n", ci->ci_dev.dv_xname);
+ printf("%s: TSC disabled\n", ci->ci_dev->dv_xname);
break;
}
}
@@ -1326,7 +1316,7 @@ natsem6x86_cpu_setup(struct cpu_info *ci)
switch (model) {
case 4:
cpu_feature &= ~CPUID_TSC;
- printf("%s: TSC disabled\n", ci->ci_dev.dv_xname);
+ printf("%s: TSC disabled\n", ci->ci_dev->dv_xname);
break;
}
}
@@ -1337,7 +1327,7 @@ intel586_cpu_setup(struct cpu_info *ci)
if (!cpu_f00f_bug) {
fix_f00f();
printf("%s: F00F bug workaround installed\n",
- ci->ci_dev.dv_xname);
+ ci->ci_dev->dv_xname);
}
}
@@ -1479,7 +1469,7 @@ intel686_cpusensors_setup(struct cpu_info *ci)
return;
/* Setup the sensors structures */
- strlcpy(ci->ci_sensordev.xname, ci->ci_dev.dv_xname,
+ strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname,
sizeof(ci->ci_sensordev.xname));
ci->ci_sensor.type = SENSOR_TEMP;
sensor_task_register(ci, intelcore_update_sensor, 5);
@@ -1500,7 +1490,7 @@ intel686_setperf_setup(struct cpu_info *ci)
est_init(ci, CPUVENDOR_INTEL);
else
printf("%s: Enhanced SpeedStep disabled by BIOS\n",
- ci->ci_dev.dv_xname);
+ ci->ci_dev->dv_xname);
} else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) ==
(CPUID_ACPI | CPUID_TM))
p4tcc_init(family, step);
@@ -1557,7 +1547,7 @@ intel686_cpu_setup(struct cpu_info *ci)
wrmsr(MSR_BBL_CR_CTL, msr119);
printf("%s: disabling processor serial number\n",
- ci->ci_dev.dv_xname);
+ ci->ci_dev->dv_xname);
ci->ci_feature_flags &= ~CPUID_PSN;
ci->ci_level = 2;
}
@@ -1673,7 +1663,7 @@ identifycpu(struct cpu_info *ci)
int family, model, step, modif, cachesize;
const struct cpu_cpuid_nameclass *cpup = NULL;
char *brandstr_from, *brandstr_to;
- char *cpu_device = ci->ci_dev.dv_xname;
+ char *cpu_device = ci->ci_dev->dv_xname;
int skipspace;
if (cpuid_level == -1) {
@@ -2150,7 +2140,7 @@ p4_get_bus_clock(struct cpu_info *ci)
default:
printf("%s: unknown Pentium 4 (model %d) "
"EBC_FREQUENCY_ID value %d\n",
- ci->ci_dev.dv_xname, model, bus);
+ ci->ci_dev->dv_xname, model, bus);
break;
}
} else {
@@ -2171,7 +2161,7 @@ p4_get_bus_clock(struct cpu_info *ci)
default:
printf("%s: unknown Pentium 4 (model %d) "
"EBC_FREQUENCY_ID value %d\n",
- ci->ci_dev.dv_xname, model, bus);
+ ci->ci_dev->dv_xname, model, bus);
break;
}
}
@@ -2199,7 +2189,7 @@ p3_get_bus_clock(struct cpu_info *ci)
break;
default:
printf("%s: unknown Pentium M FSB_FREQ value %d",
- ci->ci_dev.dv_xname, bus);
+ ci->ci_dev->dv_xname, bus);
goto print_msr;
}
break;
@@ -2233,7 +2223,7 @@ p3_get_bus_clock(struct cpu_info *ci)
break;
default:
printf("%s: unknown Core FSB_FREQ value %d",
- ci->ci_dev.dv_xname, bus);
+ ci->ci_dev->dv_xname, bus);
goto print_msr;
}
break;
@@ -2257,7 +2247,7 @@ p3_get_bus_clock(struct cpu_info *ci)
break;
default:
printf("%s: unknown Atom FSB_FREQ value %d",
- ci->ci_dev.dv_xname, bus);
+ ci->ci_dev->dv_xname, bus);
goto print_msr;
}
break;
@@ -2283,7 +2273,7 @@ p3_get_bus_clock(struct cpu_info *ci)
break;
default:
printf("%s: unknown i686 EBL_CR_POWERON value %d",
- ci->ci_dev.dv_xname, bus);
+ ci->ci_dev->dv_xname, bus);
goto print_msr;
}
break;
@@ -3060,6 +3050,8 @@ cpu_init_idt(void)
}
#endif /* MULTIPROCESSOR */
+struct i386tss proc0_tss;
+
void
init386(paddr_t first_avail)
{
@@ -3070,6 +3062,7 @@ init386(paddr_t first_avail)
proc0.p_addr = proc0paddr;
cpu_info_primary.ci_self = &cpu_info_primary;
cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb;
+ cpu_info_primary.ci_tss = &proc0_tss;
/* make bootstrap gdt gates and memory segments */
setsegment(&gdt[GCODE_SEL].sd, 0, 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1);
@@ -3085,6 +3078,8 @@ init386(paddr_t first_avail)
SDT_MEMRWA, SEL_UPL, 1, 1);
setsegment(&gdt[GUGS_SEL].sd, 0, atop(VM_MAXUSER_ADDRESS) - 1,
SDT_MEMRWA, SEL_UPL, 1, 1);
+ setsegment(&gdt[GTSS_SEL].sd, &proc0_tss, sizeof(proc0_tss)-1,
+ SDT_SYS386TSS, SEL_KPL, 0, 0);
/* exceptions */
setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL);
@@ -3113,7 +3108,7 @@ init386(paddr_t first_avail)
unsetgate(&idt[i]);
setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386TGT, SEL_UPL, GCODE_SEL);
- setregion(&region, gdt, NGDT * sizeof(union descriptor) - 1);
+ setregion(&region, gdt, GDT_SIZE - 1);
lgdt(&region);
setregion(&region, idt, sizeof(idt_region) - 1);
lidt(&region);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 04:04:01 +0000