diff options
Diffstat (limited to 'sys/arch/mvme68k/dev/if_lereg.h')
| -rw-r--r-- | sys/arch/mvme68k/dev/if_lereg.h | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/sys/arch/mvme68k/dev/if_lereg.h b/sys/arch/mvme68k/dev/if_lereg.h index a670bf81496..77cbc3aac96 100644 --- a/sys/arch/mvme68k/dev/if_lereg.h +++ b/sys/arch/mvme68k/dev/if_lereg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_lereg.h,v 1.5 1996/08/20 05:17:09 deraadt Exp $ */ +/* $OpenBSD: if_lereg.h,v 1.6 2000/01/24 05:20:53 smurph Exp $ */ /*- * Copyright (c) 1982, 1992, 1993 @@ -44,3 +44,49 @@ struct lereg1 { volatile u_int16_t ler1_rdp; /* data port */ volatile u_int16_t ler1_rap; /* register select port */ }; + +#define VLEMEMSIZE 0x40000 + +/* + * LANCE registers for MVME376 + */ +struct vlereg1 { + volatile u_int16_t ler1_csr; /* board control/status register */ + volatile u_int16_t ler1_vec; /* interupt vector register */ + volatile u_int16_t ler1_rdp; /* data port */ + volatile u_int16_t ler1_rap; /* register select port */ + volatile u_int16_t ler1_ear; /* ethernet address register */ +}; + +#define NVRAM_EN 0x0008 /* NVRAM enable bit */ +#define INTR_EN 0x0010 /* Interrupt enable bit */ +#define PARITYB 0x0020 /* Parity clear bit */ +#define HW_RS 0x0040 /* Hardware reset bit */ +#define SYSFAILB 0x0080 /* SYSFAIL bit */ +#define NVRAM_RWEL 0xE0 /* Reset write enable latch */ +#define NVRAM_STO 0x60 /* Store ram to eeprom */ +#define NVRAM_SLP 0xA0 /* Novram into low power mode */ +#define NVRAM_WRITE 0x20 /* Writes word from location x */ +#define NVRAM_SWEL 0xC0 /* Set write enable latch */ +#define NVRAM_RCL 0x40 /* Recall eeprom data into ram */ +#define NVRAM_READ 0x00 /* Reads word from location x */ + +#define CDELAY delay(10000) +#define WRITE_CSR_OR(x) reg1->ler1_csr=((struct le_softc *)sc)->csr|=x +#define WRITE_CSR_AND(x) reg1->ler1_csr=((struct le_softc *)sc)->csr&=x +#define ENABLE_NVRAM WRITE_CSR_AND(~NVRAM_EN) +#define DISABLE_NVRAM WRITE_CSR_OR(NVRAM_EN) +#define ENABLE_INTR WRITE_CSR_AND(~INTR_EN) +#define DISABLE_INTR WRITE_CSR_OR(INTR_EN) +#define RESET_HW WRITE_CSR_AND(~0xFF00);WRITE_CSR_AND(~HW_RS);CDELAY +#define SET_IPL(x) WRITE_CSR_AND(~x) +#define SET_VEC(x) reg1->ler1_vec=0;reg1->ler1_vec |=x; +#define PARITY_CL WRITE_CSR_AND(~PARITYB) +#define SYSFAIL_CL WRITE_CSR_AND(~SYSFAILB) +#define NVRAM_CMD(c,a) for(i=0;i<8;i++){ \ + reg1->ler1_ear=((c|(a<<1))>>i); \ + CDELAY; \ + } \ + CDELAY; + + |