diff options
Diffstat (limited to 'sys/dev/tc')
| -rw-r--r-- | sys/dev/tc/asc.c | 127 | ||||
| -rw-r--r-- | sys/dev/tc/asc_tc.c | 330 | ||||
| -rw-r--r-- | sys/dev/tc/asc_tcds.c | 495 | ||||
| -rw-r--r-- | sys/dev/tc/ascvar.h | 24 | ||||
| -rw-r--r-- | sys/dev/tc/devlist2h.awk | 4 | ||||
| -rw-r--r-- | sys/dev/tc/files.tc | 45 | ||||
| -rw-r--r-- | sys/dev/tc/if_le_dec.c | 160 | ||||
| -rw-r--r-- | sys/dev/tc/if_le_ioasic.c | 300 | ||||
| -rw-r--r-- | sys/dev/tc/if_le_tc.c | 14 | ||||
| -rw-r--r-- | sys/dev/tc/if_levar.h | 6 | ||||
| -rw-r--r-- | sys/dev/tc/ioasic_subr.c | 86 | ||||
| -rw-r--r-- | sys/dev/tc/ioasicreg.h | 204 | ||||
| -rw-r--r-- | sys/dev/tc/ioasicvar.h | 51 | ||||
| -rw-r--r-- | sys/dev/tc/tc.c | 58 | ||||
| -rw-r--r-- | sys/dev/tc/tcdevs | 42 | ||||
| -rw-r--r-- | sys/dev/tc/tcdevs.h | 62 | ||||
| -rw-r--r-- | sys/dev/tc/tcdevs_data.h | 78 | ||||
| -rw-r--r-- | sys/dev/tc/tcds.c | 602 | ||||
| -rw-r--r-- | sys/dev/tc/tcdsreg.h | 218 | ||||
| -rw-r--r-- | sys/dev/tc/tcdsvar.h | 87 | ||||
| -rw-r--r-- | sys/dev/tc/tcreg.h | 2 | ||||
| -rw-r--r-- | sys/dev/tc/tcvar.h | 77 |
22 files changed, 2689 insertions, 383 deletions
diff --git a/sys/dev/tc/asc.c b/sys/dev/tc/asc.c new file mode 100644 index 00000000000..b9fd2d5e692 --- /dev/null +++ b/sys/dev/tc/asc.c @@ -0,0 +1,127 @@ +/* $OpenBSD: asc.c,v 1.21 2002/05/02 22:56:06 miod Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1994 Peter Galbavy. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Peter Galbavy. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/buf.h> + +#include <scsi/scsi_all.h> +#include <scsi/scsiconf.h> + +#include <dev/ic/ncr53c9xreg.h> +#include <dev/ic/ncr53c9xvar.h> +#include <dev/tc/ascvar.h> + +struct cfdriver asc_cd = { + NULL, "asc", DV_DULL, +}; + +struct scsi_adapter asc_switch = { + ncr53c9x_scsi_cmd, + minphys, /* no max at this level; handled by DMA code */ + NULL, + NULL, +}; + +struct scsi_device asc_dev = { + NULL, /* Use default error handler */ + NULL, /* have a queue, served by this */ + NULL, /* have no async handler */ + NULL, /* Use default `done' routine */ +}; + +/* + * Glue functions + */ +u_char +asc_read_reg(sc, reg) + struct ncr53c9x_softc *sc; + int reg; +{ + struct asc_softc *asc = (struct asc_softc *)sc; + u_char v; + + v = bus_space_read_4(asc->sc_bst, asc->sc_bsh, + reg * sizeof(u_int32_t)) & 0xff; + + return (v); +} + +void +asc_write_reg(sc, reg, val) + struct ncr53c9x_softc *sc; + int reg; + u_char val; +{ + struct asc_softc *asc = (struct asc_softc *)sc; + + bus_space_write_4(asc->sc_bst, asc->sc_bsh, + reg * sizeof(u_int32_t), val); +} + diff --git a/sys/dev/tc/asc_tc.c b/sys/dev/tc/asc_tc.c new file mode 100644 index 00000000000..df417243dba --- /dev/null +++ b/sys/dev/tc/asc_tc.c @@ -0,0 +1,330 @@ +/* $OpenBSD: asc_tc.c,v 1.6 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: asc_tc.c,v 1.19 2001/11/15 09:48:19 lukem Exp $ */ + +/*- + * Copyright (c) 2000 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Tohru Nishimura. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/buf.h> + +#include <scsi/scsi_all.h> +#include <scsi/scsiconf.h> +#include <scsi/scsi_message.h> + +#include <machine/bus.h> + +#include <dev/ic/ncr53c9xreg.h> +#include <dev/ic/ncr53c9xvar.h> +#include <dev/tc/ascvar.h> + +#include <dev/tc/tcvar.h> + +struct asc_tc_softc { + struct asc_softc asc; + + /* XXX XXX XXX */ + caddr_t sc_base, sc_bounce, sc_target; +}; + +int asc_tc_match(struct device *, void *, void *); +void asc_tc_attach(struct device *, struct device *, void *); + +struct cfattach asc_tc_ca = { + sizeof(struct asc_tc_softc), asc_tc_match, asc_tc_attach +}; + +extern struct scsi_adapter asc_switch; +extern struct scsi_device asc_dev; + +int asc_dma_isintr(struct ncr53c9x_softc *); +void asc_tc_reset(struct ncr53c9x_softc *); +int asc_tc_intr(struct ncr53c9x_softc *); +int asc_tc_setup(struct ncr53c9x_softc *, caddr_t *, + size_t *, int, size_t *); +void asc_tc_go(struct ncr53c9x_softc *); +void asc_tc_stop(struct ncr53c9x_softc *); +int asc_dma_isactive(struct ncr53c9x_softc *); +void asc_clear_latched_intr(struct ncr53c9x_softc *); + +struct ncr53c9x_glue asc_tc_glue = { + asc_read_reg, + asc_write_reg, + asc_dma_isintr, + asc_tc_reset, + asc_tc_intr, + asc_tc_setup, + asc_tc_go, + asc_tc_stop, + asc_dma_isactive, + asc_clear_latched_intr, +}; + +/* + * Parameters specific to PMAZ-A TC option card. + */ +#define PMAZ_OFFSET_53C94 0x0 /* from module base */ +#define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */ +#define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */ +#define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */ + +#define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */ +#define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1)) + +#define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */ +#define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */ +#define PMAZ_DMA_ADDR(x) ((unsigned long)(x) & PMAZ_DMAR_MASK) + +int +asc_tc_match(parent, cfdata, aux) + struct device *parent; + void *cfdata, *aux; +{ + struct tc_attach_args *d = aux; + + if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) + return (0); + + return (1); +} + +void +asc_tc_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct tc_attach_args *ta = aux; + struct asc_tc_softc *asc = (struct asc_tc_softc *)self; + struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; + + /* + * Set up glue for MI code early; we use some of it here. + */ + sc->sc_glue = &asc_tc_glue; + asc->asc.sc_bst = ta->ta_memt; + asc->asc.sc_dmat = ta->ta_dmat; + if (bus_space_map(asc->asc.sc_bst, ta->ta_addr, + PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->asc.sc_bsh)) { + printf("%s: unable to map device\n", sc->sc_dev.dv_xname); + return; + } + asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */ + + tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc); + + sc->sc_id = 7; + sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000; + + /* gimme Mhz */ + sc->sc_freq /= 1000000; + + /* + * XXX More of this should be in ncr53c9x_attach(), but + * XXX should we really poke around the chip that much in + * XXX the MI code? Think about this more... + */ + + /* + * Set up static configuration info. + */ + sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; + sc->sc_cfg2 = NCRCFG2_SCSI2; + sc->sc_cfg3 = 0; + sc->sc_rev = NCR_VARIANT_NCR53C94; + + /* + * XXX minsync and maxxfer _should_ be set up in MI code, + * XXX but it appears to have some dependency on what sort + * XXX of DMA we're hooked up to, etc. + */ + + /* + * This is the value used to start sync negotiations + * Note that the NCR register "SYNCTP" is programmed + * in "clocks per byte", and has a minimum value of 4. + * The SCSI period used in negotiation is one-fourth + * of the time (in nanoseconds) needed to transfer one byte. + * Since the chip's clock is given in MHz, we have the following + * formula: 4 * period = (1000 / freq) * 4 + */ + sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; + + sc->sc_maxxfer = 64 * 1024; + + /* Do the common parts of attachment. */ + ncr53c9x_attach(sc, &asc_switch, &asc_dev); +} + +void +asc_tc_reset(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; + + asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); +} + +int +asc_tc_intr(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; + int trans, resid; + + resid = 0; + if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0 && + (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { + NCR_DMA(("asc_tc_intr: empty FIFO of %d ", resid)); + DELAY(1); + } + + resid += NCR_READ_REG(sc, NCR_TCL); + resid += NCR_READ_REG(sc, NCR_TCM) << 8; + + trans = asc->asc.sc_dmasize - resid; + + if (asc->asc.sc_flags & ASC_ISPULLUP) + memcpy(asc->sc_target, asc->sc_bounce, trans); + *asc->asc.sc_dmalen -= trans; + *asc->asc.sc_dmaaddr += trans; + asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); + + return (0); +} + +int +asc_tc_setup(sc, addr, len, datain, dmasize) + struct ncr53c9x_softc *sc; + caddr_t *addr; + size_t *len; + int datain; + size_t *dmasize; +{ + struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; + u_int32_t tc_dmar; + size_t size; + + asc->asc.sc_dmaaddr = addr; + asc->asc.sc_dmalen = len; + asc->asc.sc_flags = (datain) ? ASC_ISPULLUP : 0; + + NCR_DMA(("asc_tc_setup: start %ld@%p, %s\n", (long)*asc->asc.sc_dmalen, + *asc->asc.sc_dmaaddr, datain ? "IN" : "OUT")); + + size = *dmasize; + if (size > PER_TGT_DMA_SIZE) + size = PER_TGT_DMA_SIZE; + *dmasize = asc->asc.sc_dmasize = size; + + NCR_DMA(("asc_tc_setup: dmasize = %ld\n", (long)asc->asc.sc_dmasize)); + + asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM; + asc->sc_bounce += PER_TGT_DMA_SIZE * + sc->sc_nexus->xs->sc_link->target; + asc->sc_target = *addr; + + if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0) + memcpy(asc->sc_bounce, asc->sc_target, size); + +#if 1 + if (asc->asc.sc_flags & ASC_ISPULLUP) + tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); + else + tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); + bus_space_write_4(asc->asc.sc_bst, asc->asc.sc_bsh, PMAZ_OFFSET_DMAR, + tc_dmar); + asc->asc.sc_flags |= ASC_MAPLOADED|ASC_DMAACTIVE; +#endif + return (0); +} + +void +asc_tc_go(sc) + struct ncr53c9x_softc *sc; +{ +#if 0 + struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; + u_int32_t tc_dmar; + + if (asc->asc.sc_flags & ASC_ISPULLUP) + tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce); + else + tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce); + bus_space_write_4(asc->asc.sc_bst, asc->asc.sc_bsh, PMAZ_OFFSET_DMAR, + tc_dmar); + asc->asc.sc_flags |= ASC_DMAACTIVE; +#endif +} + +/* NEVER CALLED BY MI 53C9x ENGINE INDEED */ +void +asc_tc_stop(sc) + struct ncr53c9x_softc *sc; +{ +#if 0 + struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; + + if (asc->asc.sc_flags & ASC_ISPULLUP) + memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize); + asc->asc.sc_flags &= ~ASC_DMAACTIVE; +#endif +} + +/* + * Glue functions. + */ +int +asc_dma_isintr(sc) + struct ncr53c9x_softc *sc; +{ + return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT); +} + +int +asc_dma_isactive(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tc_softc *asc = (struct asc_tc_softc *)sc; + + return !!(asc->asc.sc_flags & ASC_DMAACTIVE); +} + +void +asc_clear_latched_intr(sc) + struct ncr53c9x_softc *sc; +{ +} diff --git a/sys/dev/tc/asc_tcds.c b/sys/dev/tc/asc_tcds.c new file mode 100644 index 00000000000..aecbef78109 --- /dev/null +++ b/sys/dev/tc/asc_tcds.c @@ -0,0 +1,495 @@ +/* $OpenBSD: asc_tcds.c,v 1.1 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: asc_tcds.c,v 1.5 2001/11/15 09:48:19 lukem Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1994 Peter Galbavy. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Peter Galbavy. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/buf.h> + +#include <scsi/scsi_all.h> +#include <scsi/scsiconf.h> + +#include <dev/ic/ncr53c9xreg.h> +#include <dev/ic/ncr53c9xvar.h> +#include <dev/tc/ascvar.h> + +#include <machine/bus.h> + +#include <dev/tc/tcvar.h> +#include <dev/tc/tcdsreg.h> +#include <dev/tc/tcdsvar.h> + +struct asc_tcds_softc { + struct asc_softc asc; + + struct tcds_slotconfig *sc_tcds; +}; + +int asc_tcds_match (struct device *, void *, void *); +void asc_tcds_attach(struct device *, struct device *, void *); + +/* Linkup to the rest of the kernel */ +struct cfattach asc_tcds_ca = { + sizeof(struct asc_tcds_softc), asc_tcds_match, asc_tcds_attach +}; + +/* + * Functions and the switch for the MI code. + */ +int tcds_dma_isintr(struct ncr53c9x_softc *); +void tcds_dma_reset(struct ncr53c9x_softc *); +int tcds_dma_intr(struct ncr53c9x_softc *); +int tcds_dma_setup(struct ncr53c9x_softc *, caddr_t *, + size_t *, int, size_t *); +void tcds_dma_go(struct ncr53c9x_softc *); +void tcds_dma_stop(struct ncr53c9x_softc *); +int tcds_dma_isactive(struct ncr53c9x_softc *); +void tcds_clear_latched_intr(struct ncr53c9x_softc *); + +struct ncr53c9x_glue asc_tcds_glue = { + asc_read_reg, + asc_write_reg, + tcds_dma_isintr, + tcds_dma_reset, + tcds_dma_intr, + tcds_dma_setup, + tcds_dma_go, + tcds_dma_stop, + tcds_dma_isactive, + tcds_clear_latched_intr, +}; + +extern struct scsi_adapter asc_switch; +extern struct scsi_device asc_dev; + +int +asc_tcds_match(parent, cf, aux) + struct device *parent; + void *cf, *aux; +{ + + /* We always exist. */ + return 1; +} + +#define DMAMAX(a) (NBPG - ((a) & (NBPG - 1))) + +/* + * Attach this instance, and then all the sub-devices + */ +void +asc_tcds_attach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct tcdsdev_attach_args *tcdsdev = aux; + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)self; + struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; + int error; + + /* + * Set up glue for MI code early; we use some of it here. + */ + sc->sc_glue = &asc_tcds_glue; + + asc->asc.sc_bst = tcdsdev->tcdsda_bst; + asc->asc.sc_bsh = tcdsdev->tcdsda_bsh; + asc->sc_tcds = tcdsdev->tcdsda_sc; + + /* + * The TCDS ASIC cannot DMA across 8k boundaries, and this + * driver is written such that each DMA segment gets a new + * call to tcds_dma_setup(). Thus, the DMA map only needs + * to support 8k transfers. + */ + asc->asc.sc_dmat = tcdsdev->tcdsda_dmat; + if ((error = bus_dmamap_create(asc->asc.sc_dmat, NBPG, 1, NBPG, + NBPG, BUS_DMA_NOWAIT, &asc->asc.sc_dmamap)) < 0) { + printf("failed to create dma map, error = %d\n", error); + } + + sc->sc_id = tcdsdev->tcdsda_id; + sc->sc_freq = tcdsdev->tcdsda_freq; + + /* gimme Mhz */ + sc->sc_freq /= 1000000; + + tcds_intr_establish(parent, tcdsdev->tcdsda_chip, ncr53c9x_intr, sc); + + /* + * XXX More of this should be in ncr53c9x_attach(), but + * XXX should we really poke around the chip that much in + * XXX the MI code? Think about this more... + */ + + /* + * Set up static configuration info. + */ + sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; + sc->sc_cfg2 = NCRCFG2_SCSI2; + sc->sc_cfg3 = NCRCFG3_CDB; + if (sc->sc_freq > 25) + sc->sc_cfg3 |= NCRF9XCFG3_FCLK; + sc->sc_rev = tcdsdev->tcdsda_variant; + if (tcdsdev->tcdsda_fast) { + sc->sc_features |= NCR_F_FASTSCSI; + sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; + } + + /* + * XXX minsync and maxxfer _should_ be set up in MI code, + * XXX but it appears to have some dependency on what sort + * XXX of DMA we're hooked up to, etc. + */ + + /* + * This is the value used to start sync negotiations + * Note that the NCR register "SYNCTP" is programmed + * in "clocks per byte", and has a minimum value of 4. + * The SCSI period used in negotiation is one-fourth + * of the time (in nanoseconds) needed to transfer one byte. + * Since the chip's clock is given in MHz, we have the following + * formula: 4 * period = (1000 / freq) * 4 + */ + sc->sc_minsync = (1000 / sc->sc_freq) * tcdsdev->tcdsda_period / 4; + + sc->sc_maxxfer = 64 * 1024; + + /* Do the common parts of attachment. */ + ncr53c9x_attach(sc, &asc_switch, &asc_dev); +} + +void +tcds_dma_reset(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; + + /* TCDS SCSI disable/reset/enable. */ + tcds_scsi_reset(asc->sc_tcds); /* XXX */ + + if (asc->asc.sc_flags & ASC_MAPLOADED) + bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); + asc->asc.sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED); +} + +/* + * start a dma transfer or keep it going + */ +int +tcds_dma_setup(sc, addr, len, ispullup, dmasize) + struct ncr53c9x_softc *sc; + caddr_t *addr; + size_t *len, *dmasize; + int ispullup; /* DMA into main memory */ +{ + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; + struct tcds_slotconfig *tcds = asc->sc_tcds; + size_t size; + u_int32_t dic; + + NCR_DMA(("tcds_dma %d: start %d@%p,%s\n", tcds->sc_slot, + (int)*asc->asc.sc_dmalen, *asc->asc.sc_dmaaddr, + (ispullup) ? "IN" : "OUT")); + + /* + * the rules say we cannot transfer more than the limit + * of this DMA chip (64k) and we cannot cross a 8k boundary. + */ + size = min(*dmasize, DMAMAX((size_t)*addr)); + asc->asc.sc_dmaaddr = addr; + asc->asc.sc_dmalen = len; + asc->asc.sc_flags = (ispullup) ? ASC_ISPULLUP : 0; + *dmasize = asc->asc.sc_dmasize = size; + + NCR_DMA(("dma_start: dmasize = %d\n", (int)size)); + + if (size == 0) + return 0; + + if (bus_dmamap_load(asc->asc.sc_dmat, asc->asc.sc_dmamap, *addr, size, + NULL, BUS_DMA_NOWAIT | (ispullup ? BUS_DMA_READ : BUS_DMA_WRITE))) { + /* + * XXX Should return an error, here, but the upper-layer + * XXX doesn't check the return value! + */ + panic("tcds_dma_setup: dmamap load failed"); + } + + /* synchronize dmamap contents with memory image */ + bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, 0, size, + (ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); + + /* load address, set/clear unaligned transfer and read/write bits. */ + bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_sda, + asc->asc.sc_dmamap->dm_segs[0].ds_addr >> 2); + dic = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic); + dic &= ~TCDS_DIC_ADDRMASK; + dic |= asc->asc.sc_dmamap->dm_segs[0].ds_addr & TCDS_DIC_ADDRMASK; + if (ispullup) + dic |= TCDS_DIC_WRITE; + else + dic &= ~TCDS_DIC_WRITE; + bus_space_write_4(tcds->sc_bst, tcds->sc_bsh, tcds->sc_dic, dic); + + asc->asc.sc_flags |= ASC_MAPLOADED; + return 0; +} + +void +tcds_dma_go(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; + + /* mark unit as DMA-active */ + asc->asc.sc_flags |= ASC_DMAACTIVE; + + /* start DMA */ + tcds_dma_enable(asc->sc_tcds, 1); +} + +void +tcds_dma_stop(sc) + struct ncr53c9x_softc *sc; +{ +#if 0 + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; +#endif + + /* + * XXX STOP DMA HERE! + */ +} + +/* + * Pseudo (chained) interrupt from the asc driver to kick the + * current running DMA transfer. Called from ncr53c9x_intr() + * for now. + * + * return 1 if it was a DMA continue. + */ +int +tcds_dma_intr(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; + struct tcds_slotconfig *tcds = asc->sc_tcds; + int trans, resid; + u_int32_t tcl, tcm; + u_int32_t dud, dudmask, *addr; + bus_addr_t pa; + + NCR_DMA(("tcds_dma %d: intr", tcds->sc_slot)); + + if (tcds_scsi_iserr(tcds)) + return 0; + + /* This is an "assertion" :) */ + if ((asc->asc.sc_flags & ASC_DMAACTIVE) == 0) + panic("tcds_dma_intr: DMA wasn't active"); + + /* DMA has stopped */ + tcds_dma_enable(tcds, 0); + asc->asc.sc_flags &= ~ASC_DMAACTIVE; + + if (asc->asc.sc_dmasize == 0) { + /* A "Transfer Pad" operation completed */ + tcl = NCR_READ_REG(sc, NCR_TCL); + tcm = NCR_READ_REG(sc, NCR_TCM); + NCR_DMA(("dma_intr: discarded %d bytes (tcl=%d, tcm=%d)\n", + tcl | (tcm << 8), tcl, tcm)); + return 0; + } + + resid = 0; + if ((asc->asc.sc_flags & ASC_ISPULLUP) == 0 && + (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { + NCR_DMA(("dma_intr: empty esp FIFO of %d ", resid)); + DELAY(1); + } + + resid += (tcl = NCR_READ_REG(sc, NCR_TCL)); + resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8; + + trans = asc->asc.sc_dmasize - resid; + if (trans < 0) { /* transferred < 0 ? */ + printf("tcds_dma %d: xfer (%d) > req (%d)\n", + tcds->sc_slot, trans, (int)asc->asc.sc_dmasize); + trans = asc->asc.sc_dmasize; + } + + NCR_DMA(("dma_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", + tcl, tcm, trans, resid)); + + *asc->asc.sc_dmalen -= trans; + *asc->asc.sc_dmaaddr += trans; + + bus_dmamap_sync(asc->asc.sc_dmat, asc->asc.sc_dmamap, + 0, asc->asc.sc_dmamap->dm_mapsize, + (asc->asc.sc_flags & ASC_ISPULLUP) + ? BUS_DMASYNC_POSTREAD + : BUS_DMASYNC_POSTWRITE); + + /* + * Clean up unaligned DMAs into main memory. + */ + if (asc->asc.sc_flags & ASC_ISPULLUP) { + /* Handle unaligned starting address, length. */ + dud = bus_space_read_4(tcds->sc_bst, + tcds->sc_bsh, tcds->sc_dud0); + if ((dud & TCDS_DUD0_VALIDBITS) != 0) { + addr = (u_int32_t *) + ((paddr_t)*asc->asc.sc_dmaaddr & ~0x3); + dudmask = 0; + if (dud & TCDS_DUD0_VALID00) + panic("tcds_dma: dud0 byte 0 valid"); + if (dud & TCDS_DUD0_VALID01) + dudmask |= TCDS_DUD_BYTE01; + if (dud & TCDS_DUD0_VALID10) + dudmask |= TCDS_DUD_BYTE10; +#ifdef DIAGNOSTIC + if (dud & TCDS_DUD0_VALID11) + dudmask |= TCDS_DUD_BYTE11; +#endif + NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n", + addr, dudmask)); + *addr = (*addr & ~dudmask) | (dud & dudmask); + } + dud = bus_space_read_4(tcds->sc_bst, + tcds->sc_bsh, tcds->sc_dud1); + if ((dud & TCDS_DUD1_VALIDBITS) != 0) { + pa = bus_space_read_4(tcds->sc_bst, tcds->sc_bsh, + tcds->sc_sda) << 2; + dudmask = 0; + if (dud & TCDS_DUD1_VALID00) + dudmask |= TCDS_DUD_BYTE00; + if (dud & TCDS_DUD1_VALID01) + dudmask |= TCDS_DUD_BYTE01; + if (dud & TCDS_DUD1_VALID10) + dudmask |= TCDS_DUD_BYTE10; +#ifdef DIAGNOSTIC + if (dud & TCDS_DUD1_VALID11) + panic("tcds_dma: dud1 byte 3 valid"); +#endif + NCR_DMA(("dud1 at 0x%lx dudmask 0x%x\n", + pa, dudmask)); + /* XXX Fix TC_PHYS_TO_UNCACHED() */ +#if defined(__alpha__) + addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG(pa); +#elif defined(__mips__) + addr = (u_int32_t *)MIPS_PHYS_TO_KSEG1(pa); +#else +#error TURBOchannel only exists on DECs, folks... +#endif + *addr = (*addr & ~dudmask) | (dud & dudmask); + } + /* XXX deal with saved residual byte? */ + } + + bus_dmamap_unload(asc->asc.sc_dmat, asc->asc.sc_dmamap); + asc->asc.sc_flags &= ~ASC_MAPLOADED; + + return 0; +} + +/* + * Glue functions. + */ +int +tcds_dma_isintr(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; + int x; + + x = tcds_scsi_isintr(asc->sc_tcds, 1); + + /* XXX */ + return x; +} + +int +tcds_dma_isactive(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; + + return !!(asc->asc.sc_flags & ASC_DMAACTIVE); +} + +void +tcds_clear_latched_intr(sc) + struct ncr53c9x_softc *sc; +{ + struct asc_tcds_softc *asc = (struct asc_tcds_softc *)sc; + + /* Clear the TCDS interrupt bit. */ + (void)tcds_scsi_isintr(asc->sc_tcds, 1); +} diff --git a/sys/dev/tc/ascvar.h b/sys/dev/tc/ascvar.h new file mode 100644 index 00000000000..f69e770dc5d --- /dev/null +++ b/sys/dev/tc/ascvar.h @@ -0,0 +1,24 @@ +/* $OpenBSD: ascvar.h,v 1.9 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: ascvar.h,v 1.7 2000/10/31 15:16:26 simonb Exp $ */ + +/* + * State kept for each active SCSI host interface (53C94). + */ + +struct asc_softc { + struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ + bus_space_tag_t sc_bst; /* bus space tag */ + bus_space_handle_t sc_bsh; /* ASC register handle */ + bus_dma_tag_t sc_dmat; /* bus dma tag */ + bus_dmamap_t sc_dmamap; /* bus dmamap */ + caddr_t *sc_dmaaddr; + size_t *sc_dmalen; + size_t sc_dmasize; + unsigned sc_flags; +#define ASC_ISPULLUP 0x01 +#define ASC_DMAACTIVE 0x02 +#define ASC_MAPLOADED 0x04 +}; + +u_char asc_read_reg(struct ncr53c9x_softc *, int); +void asc_write_reg(struct ncr53c9x_softc *, int, u_char); diff --git a/sys/dev/tc/devlist2h.awk b/sys/dev/tc/devlist2h.awk index 9164d87ac26..bf189844e04 100644 --- a/sys/dev/tc/devlist2h.awk +++ b/sys/dev/tc/devlist2h.awk @@ -1,5 +1,5 @@ #! /usr/bin/awk -f -# $OpenBSD: devlist2h.awk,v 1.3 1996/12/08 01:03:03 niklas Exp $ +# $OpenBSD: devlist2h.awk,v 1.4 2002/05/02 22:56:06 miod Exp $ # $NetBSD: devlist2h.awk,v 1.3 1996/06/05 18:32:19 cgd Exp $ # # Copyright (c) 1995, 1996 Christopher G. Demetriou @@ -39,6 +39,7 @@ NR == 1 { VERSION = $0 gsub("\\$", "", VERSION) + printf("/*\t\$OpenBSD\$\t*/\n\n") > dfile printf("/*\n") > dfile printf(" * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n") \ > dfile @@ -47,6 +48,7 @@ NR == 1 { printf(" *\t%s\n", VERSION) > dfile printf(" */\n") > dfile + printf("/*\t\$OpenBSD\$\t*/\n\n") > hfile printf("/*\n") > hfile printf(" * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.\n") \ > hfile diff --git a/sys/dev/tc/files.tc b/sys/dev/tc/files.tc index 38490a44ab8..5c8b0895d6e 100644 --- a/sys/dev/tc/files.tc +++ b/sys/dev/tc/files.tc @@ -1,21 +1,42 @@ -# $OpenBSD: files.tc,v 1.5 1996/05/26 00:27:52 deraadt Exp $ -# $NetBSD: files.tc,v 1.5 1996/05/20 00:45:02 thorpej Exp $ +# $OpenBSD: files.tc,v 1.6 2002/05/02 22:56:06 miod Exp $ +# $NetBSD: files.tc,v 1.26 2001/11/28 10:21:24 lukem Exp $ # -# Config.new file and device description for machine-independent -# TurboChannel code. Included by ports that need it. +# Config file and device description for machine-independent +# TURBOchannel code. Included by ports that need it. device tc {[slot = -1], [offset = -1]} -attach tc at tcbus +#attach tc at tcbus file dev/tc/tc.c tc needs-flag -# device defined in sys/conf/files -# attach le at ioasic with le_ioasic -# attach le at tc with le_tc -# file dev/tc/if_le_dec.c (le_ioasic | le_tc) -# file dev/tc/if_le_ioasic.c le_ioasic needs-flag # for le_iomem -# file dev/tc/if_le_tc.c le_tc +# IOCTL ASIC +device ioasic { offset = -1 } +attach ioasic at tc +file dev/tc/ioasic_subr.c ioasic -# DEC DEFTA TC FDDI Controller +# LANCE attachments. +# lance device defined in sys/conf/files +# le_dec_subr attribute defined in sys/dev/dec/files.dec + +attach le at ioasic with le_ioasic: le_dec_subr +file dev/tc/if_le_ioasic.c le_ioasic + +attach le at tc with le_tc: le_dec_subr +file dev/tc/if_le_tc.c le_tc + +# DEFTA FDDI controller device fta: pdq, fddi, ifnet attach fta at tc file dev/tc/if_fta.c fta + +# TCDS dual channel SCSI +device tcds { chip = -1 } +attach tcds at tc +file dev/tc/tcds.c tcds + +# 53C[F]90 PMAZ single channel SCSI +device asc: ncr53c9x, scsi +file dev/tc/asc.c asc +attach asc at tc with asc_tc +file dev/tc/asc_tc.c asc_tc +attach asc at tcds with asc_tcds +file dev/tc/asc_tcds.c asc_tcds diff --git a/sys/dev/tc/if_le_dec.c b/sys/dev/tc/if_le_dec.c deleted file mode 100644 index 68a96fbeb6f..00000000000 --- a/sys/dev/tc/if_le_dec.c +++ /dev/null @@ -1,160 +0,0 @@ -/* $OpenBSD: if_le_dec.c,v 1.5 2002/03/14 01:27:03 millert Exp $ */ -/* $NetBSD: if_le_dec.c,v 1.3 1996/10/13 01:38:38 christos Exp $ */ - -/*- - * Copyright (c) 1995 Charles M. Hannum. All rights reserved. - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * Ralph Campbell and Rick Macklem. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)if_le.c 8.2 (Berkeley) 11/16/93 - */ - -#include "bpfilter.h" - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/mbuf.h> -#include <sys/syslog.h> -#include <sys/socket.h> -#include <sys/device.h> - -#include <net/if.h> -#include <net/if_media.h> - -#ifdef INET -#include <netinet/in.h> -#include <netinet/if_ether.h> -#endif - -#include <dev/ic/am7990reg.h> -#include <dev/ic/am7990var.h> - -#include <dev/tc/if_levar.h> -#include <dev/tc/tcvar.h> - -/* access LANCE registers */ -void le_dec_writereg(volatile u_short *regptr, u_short val); -#define LERDWR(cntl, src, dst) { (dst) = (src); tc_mb(); } -#define LEWREG(src, dst) le_dec_writereg(&(dst), (src)) - -hide void le_dec_wrcsr(struct am7990_softc *, u_int16_t, u_int16_t); -hide u_int16_t le_dec_rdcsr(struct am7990_softc *, u_int16_t); - -void -dec_le_common_attach(sc, eap) - struct am7990_softc *sc; - u_char *eap; -{ - int i; - - sc->sc_rdcsr = le_dec_rdcsr; - sc->sc_wrcsr = le_dec_wrcsr; - sc->sc_hwinit = NULL; - - sc->sc_conf3 = 0; - sc->sc_addr = 0; - sc->sc_memsize = 65536; - - /* - * Get the ethernet address out of rom - */ - for (i = 0; i < sizeof(sc->sc_arpcom.ac_enaddr); i++) { - sc->sc_arpcom.ac_enaddr[i] = *eap; - eap += 4; - } - - am7990_config(sc); -} - -hide void -le_dec_wrcsr(sc, port, val) - struct am7990_softc *sc; - u_int16_t port, val; -{ - struct lereg1 *ler1 = ((struct le_softc *)sc)->sc_r1; - - LEWREG(port, ler1->ler1_rap); - LERDWR(port, val, ler1->ler1_rdp); -} - -hide u_int16_t -le_dec_rdcsr(sc, port) - struct am7990_softc *sc; - u_int16_t port; -{ - struct lereg1 *ler1 = ((struct le_softc *)sc)->sc_r1; - u_int16_t val; - - LEWREG(port, ler1->ler1_rap); - LERDWR(0, ler1->ler1_rdp, val); - return (val); -} - -/* - * Write a lance register port, reading it back to ensure success. This seems - * to be necessary during initialization, since the chip appears to be a bit - * pokey sometimes. - */ -void -le_dec_writereg(regptr, val) - register volatile u_short *regptr; - register u_short val; -{ - register int i = 0; - - while (*regptr != val) { - *regptr = val; - tc_mb(); - if (++i > 10000) { - printf("le: Reg did not settle (to x%x): x%x\n", val, - *regptr); - return; - } - DELAY(100); - } -} - -/* - * Routines for accessing the transmit and receive buffers are provided - * by am7990.c, because of the LE_NEED_BUF_* macros defined above. - * Unfortunately, CPU addressing of these buffers is done in one of - * 3 ways: - * - contiguous (for the 3max and turbochannel option card) - * - gap2, which means shorts (2 bytes) interspersed with short (2 byte) - * spaces (for the pmax) - * - gap16, which means 16bytes interspersed with 16byte spaces - * for buffers which must begin on a 32byte boundary (for 3min, maxine, - * and alpha) - * The buffer offset is the logical byte offset, assuming contiguous storage. - */ diff --git a/sys/dev/tc/if_le_ioasic.c b/sys/dev/tc/if_le_ioasic.c index 2ff91977d17..9eab3788dc2 100644 --- a/sys/dev/tc/if_le_ioasic.c +++ b/sys/dev/tc/if_le_ioasic.c @@ -1,5 +1,5 @@ -/* $OpenBSD: if_le_ioasic.c,v 1.10 2002/03/14 01:27:03 millert Exp $ */ -/* $NetBSD: if_le_ioasic.c,v 1.2 1996/05/07 02:24:56 thorpej Exp $ */ +/* $OpenBSD: if_le_ioasic.c,v 1.11 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: if_le_ioasic.c,v 1.18 2001/11/13 06:26:10 lukem Exp $ */ /* * Copyright (c) 1996 Carnegie-Mellon University. @@ -42,8 +42,6 @@ #include <net/if.h> #include <net/if_media.h> -#include <uvm/uvm_extern.h> - #ifdef INET #include <netinet/in.h> #include <netinet/if_ether.h> @@ -54,26 +52,35 @@ #include <dev/tc/if_levar.h> #include <dev/tc/tcvar.h> +#include <dev/tc/ioasicreg.h> #include <dev/tc/ioasicvar.h> -int le_ioasic_match(struct device *, void *, void *); -void le_ioasic_attach(struct device *, struct device *, void *); +struct le_ioasic_softc { + struct am7990_softc sc_am7990; /* glue to MI code */ + struct lereg1 *sc_r1; /* LANCE registers */ + /* XXX must match with le_softc of if_levar.h XXX */ -hide void le_ioasic_copytobuf_gap2(struct am7990_softc *, void *, - int, int); -hide void le_ioasic_copyfrombuf_gap2(struct am7990_softc *, void *, - int, int); + bus_dma_tag_t sc_dmat; /* bus dma tag */ + bus_dmamap_t sc_dmamap; /* bus dmamap */ +}; -hide void le_ioasic_copytobuf_gap16(struct am7990_softc *, void *, - int, int); -hide void le_ioasic_copyfrombuf_gap16(struct am7990_softc *, void *, - int, int); -hide void le_ioasic_zerobuf_gap16(struct am7990_softc *, int, int); +int le_ioasic_match(struct device *, void *, void *); +void le_ioasic_attach(struct device *, struct device *, void *); struct cfattach le_ioasic_ca = { sizeof(struct le_softc), le_ioasic_match, le_ioasic_attach }; +void le_ioasic_copytobuf_gap2(struct am7990_softc *, void *, + int, int); +void le_ioasic_copyfrombuf_gap2(struct am7990_softc *, void *, + int, int); +void le_ioasic_copytobuf_gap16(struct am7990_softc *, void *, + int, int); +void le_ioasic_copyfrombuf_gap16(struct am7990_softc *, void *, + int, int); +void le_ioasic_zerobuf_gap16(struct am7990_softc *, int, int); + int le_ioasic_match(parent, match, aux) struct device *parent; @@ -81,67 +88,92 @@ le_ioasic_match(parent, match, aux) { struct ioasicdev_attach_args *d = aux; - if (!ioasic_submatch(match, aux)) - return (0); - if (strncmp("lance", d->iada_modname, TC_ROM_LLEN)) - return (0); + if (strncmp("PMAD-BA ", d->iada_modname, TC_ROM_LLEN) != 0) + return 0; - return (1); + return 1; } -#define LE_IOASIC_MEMSIZE (128*1024) -#define LE_IOASIC_MEMALIGN (128*1024) +/* IOASIC LANCE DMA needs 128KB boundary aligned 128KB chunk */ +#define LE_IOASIC_MEMSIZE (128*1024) +#define LE_IOASIC_MEMALIGN (128*1024) + void le_ioasic_attach(parent, self, aux) struct device *parent, *self; void *aux; { + struct le_ioasic_softc *sc = (void *)self; struct ioasicdev_attach_args *d = aux; - struct le_softc *lesc = (void *)self; - struct am7990_softc *sc = &lesc->sc_am7990; + struct am7990_softc *le = &sc->sc_am7990; + bus_space_tag_t ioasic_bst; + bus_space_handle_t ioasic_bsh; + bus_dma_tag_t dmat; + bus_dma_segment_t seg; + tc_addr_t tca; + u_int32_t ssr; + int rseg; caddr_t le_iomem; - struct pglist pglist; - struct vm_page *pg; - vaddr_t va; - vsize_t size; + ioasic_bst = ((struct ioasic_softc *)parent)->sc_bst; + ioasic_bsh = ((struct ioasic_softc *)parent)->sc_bsh; + dmat = sc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat; /* - * XXX - this vm juggling is so wrong. use bus_dma instead! + * Allocate a DMA area for the chip. */ - size = round_page(LE_IOASIC_MEMSIZE); - if (uvm_pglistalloc(size, 0, 0, LE_IOASIC_MEMALIGN, 0, &pglist, 1, 0) || - uvm_map(kernel_map, &va, size, NULL, UVM_UNKNOWN_OFFSET, 0, - UVM_MAPFLAG(UVM_PROT_ALL, UVM_PROT_ALL, UVM_INH_NONE, - UVM_ADV_RANDOM, 0))) - panic("aha_init: could not allocate mailbox"); - - le_iomem = (caddr_t)va; - for (pg = TAILQ_FIRST(&pglist); pg != NULL;pg = TAILQ_NEXT(pg, pageq)) { - pmap_kenter_pa(va, VM_PAGE_TO_PHYS(pg), - VM_PROT_READ|VM_PROT_WRITE); - va += PAGE_SIZE; + if (bus_dmamem_alloc(dmat, LE_IOASIC_MEMSIZE, LE_IOASIC_MEMALIGN, + 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { + printf("can't allocate DMA area for LANCE\n"); + return; + } + if (bus_dmamem_map(dmat, &seg, rseg, LE_IOASIC_MEMSIZE, + &le_iomem, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { + printf("can't map DMA area for LANCE\n"); + bus_dmamem_free(dmat, &seg, rseg); + return; } - pmap_update(pmap_kernel()); /* - * XXXEND + * Create and load the DMA map for the DMA area. */ + if (bus_dmamap_create(dmat, LE_IOASIC_MEMSIZE, 1, + LE_IOASIC_MEMSIZE, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { + printf("can't create DMA map\n"); + goto bad; + } + if (bus_dmamap_load(dmat, sc->sc_dmamap, + le_iomem, LE_IOASIC_MEMSIZE, NULL, BUS_DMA_NOWAIT)) { + printf("can't load DMA map\n"); + goto bad; + } + /* + * Bind 128KB buffer with IOASIC DMA. + */ + tca = IOASIC_DMA_ADDR(sc->sc_dmamap->dm_segs[0].ds_addr); + bus_space_write_4(ioasic_bst, ioasic_bsh, IOASIC_LANCE_DMAPTR, tca); + ssr = bus_space_read_4(ioasic_bst, ioasic_bsh, IOASIC_CSR); + ssr |= IOASIC_CSR_DMAEN_LANCE; + bus_space_write_4(ioasic_bst, ioasic_bsh, IOASIC_CSR, ssr); - lesc->sc_r1 = (struct lereg1 *) + sc->sc_r1 = (struct lereg1 *) TC_DENSE_TO_SPARSE(TC_PHYS_TO_UNCACHED(d->iada_addr)); - sc->sc_mem = (void *)TC_PHYS_TO_UNCACHED(le_iomem); - - sc->sc_copytodesc = le_ioasic_copytobuf_gap2; - sc->sc_copyfromdesc = le_ioasic_copyfrombuf_gap2; - sc->sc_copytobuf = le_ioasic_copytobuf_gap16; - sc->sc_copyfrombuf = le_ioasic_copyfrombuf_gap16; - sc->sc_zerobuf = le_ioasic_zerobuf_gap16; + le->sc_mem = (void *)TC_PHYS_TO_UNCACHED(le_iomem); + le->sc_copytodesc = le_ioasic_copytobuf_gap2; + le->sc_copyfromdesc = le_ioasic_copyfrombuf_gap2; + le->sc_copytobuf = le_ioasic_copytobuf_gap16; + le->sc_copyfrombuf = le_ioasic_copyfrombuf_gap16; + le->sc_zerobuf = le_ioasic_zerobuf_gap16; - ioasic_lance_dma_setup(le_iomem); /* XXX more thought */ - - dec_le_common_attach(sc, ioasic_lance_ether_address()); + dec_le_common_attach(&sc->sc_am7990, + (u_char *)((struct ioasic_softc *)parent)->sc_base + + IOASIC_SLOT_2_START); ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_NET, am7990_intr, sc); + return; + + bad: + bus_dmamem_unmap(dmat, le_iomem, LE_IOASIC_MEMSIZE); + bus_dmamem_free(dmat, &seg, rseg); } /* @@ -161,11 +193,11 @@ le_ioasic_copytobuf_gap2(sc, fromv, boff, len) struct am7990_softc *sc; void *fromv; int boff; - register int len; + int len; { volatile caddr_t buf = sc->sc_mem; - register caddr_t from = fromv; - register volatile u_int16_t *bptr; + caddr_t from = fromv; + volatile u_int16_t *bptr; if (boff & 0x1) { /* handle unaligned first byte */ @@ -192,9 +224,9 @@ le_ioasic_copyfrombuf_gap2(sc, tov, boff, len) int boff, len; { volatile caddr_t buf = sc->sc_mem; - register caddr_t to = tov; - register volatile u_int16_t *bptr; - register u_int16_t tmp; + caddr_t to = tov; + volatile u_int16_t *bptr; + u_int16_t tmp; if (boff & 0x1) { /* handle unaligned first byte */ @@ -226,24 +258,84 @@ le_ioasic_copytobuf_gap16(sc, fromv, boff, len) struct am7990_softc *sc; void *fromv; int boff; - register int len; + int len; { volatile caddr_t buf = sc->sc_mem; - register caddr_t from = fromv; - register caddr_t bptr; - register int xfer; + caddr_t from = fromv; + caddr_t bptr; bptr = buf + ((boff << 1) & ~0x1f); boff &= 0xf; - xfer = min(len, 16 - boff); - while (len > 0) { + + /* + * Dispose of boff so destination of subsequent copies is + * 16-byte aligned. + */ + if (boff) { + int xfer; + xfer = min(len, 16 - boff); bcopy(from, bptr + boff, xfer); from += xfer; bptr += 32; - boff = 0; len -= xfer; - xfer = min(len, 16); } + + /* Destination of copies is now 16-byte aligned. */ + if (len >= 16) + switch ((u_long)from & (sizeof(u_int32_t) -1)) { + case 2: + /* Ethernet headers make this the dominant case. */ + do { + u_int32_t *dst = (u_int32_t*)bptr; + u_int16_t t0; + u_int32_t t1, t2, t3, t4; + + /* read from odd-16-bit-aligned, cached src */ + t0 = *(u_int16_t*)from; + t1 = *(u_int32_t*)(from+2); + t2 = *(u_int32_t*)(from+6); + t3 = *(u_int32_t*)(from+10); + t4 = *(u_int16_t*)(from+14); + + /* DMA buffer is uncached on mips */ + dst[0] = t0 | (t1 << 16); + dst[1] = (t1 >> 16) | (t2 << 16); + dst[2] = (t2 >> 16) | (t3 << 16); + dst[3] = (t3 >> 16) | (t4 << 16); + + from += 16; + bptr += 32; + len -= 16; + } while (len >= 16); + break; + + case 0: + do { + u_int32_t *src = (u_int32_t*)from; + u_int32_t *dst = (u_int32_t*)bptr; + u_int32_t t0, t1, t2, t3; + + t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3]; + dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3; + + from += 16; + bptr += 32; + len -= 16; + } while (len >= 16); + break; + + default: + /* Does odd-aligned case ever happen? */ + do { + bcopy(from, bptr, 16); + from += 16; + bptr += 32; + len -= 16; + } while (len >= 16); + break; + } + if (len) + bcopy(from, bptr, len); } void @@ -253,21 +345,73 @@ le_ioasic_copyfrombuf_gap16(sc, tov, boff, len) int boff, len; { volatile caddr_t buf = sc->sc_mem; - register caddr_t to = tov; - register caddr_t bptr; - register int xfer; + caddr_t to = tov; + caddr_t bptr; bptr = buf + ((boff << 1) & ~0x1f); boff &= 0xf; - xfer = min(len, 16 - boff); - while (len > 0) { - bcopy(bptr + boff, to, xfer); + + /* Dispose of boff. source of copy is subsequently 16-byte aligned. */ + if (boff) { + int xfer; + xfer = min(len, 16 - boff); + bcopy(bptr+boff, to, xfer); to += xfer; bptr += 32; - boff = 0; len -= xfer; - xfer = min(len, 16); } + if (len >= 16) + switch ((u_long)to & (sizeof(u_int32_t) -1)) { + case 2: + /* + * to is aligned to an odd 16-bit boundary. Ethernet headers + * make this the dominant case (98% or more). + */ + do { + u_int32_t *src = (u_int32_t*)bptr; + u_int32_t t0, t1, t2, t3; + + /* read from uncached aligned DMA buf */ + t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3]; + + /* write to odd-16-bit-word aligned dst */ + *(u_int16_t *) (to+0) = (u_short) t0; + *(u_int32_t *) (to+2) = (t0 >> 16) | (t1 << 16); + *(u_int32_t *) (to+6) = (t1 >> 16) | (t2 << 16); + *(u_int32_t *) (to+10) = (t2 >> 16) | (t3 << 16); + *(u_int16_t *) (to+14) = (t3 >> 16); + bptr += 32; + to += 16; + len -= 16; + } while (len > 16); + break; + case 0: + /* 32-bit aligned aligned copy. Rare. */ + do { + u_int32_t *src = (u_int32_t*)bptr; + u_int32_t *dst = (u_int32_t*)to; + u_int32_t t0, t1, t2, t3; + + t0 = src[0]; t1 = src[1]; t2 = src[2]; t3 = src[3]; + dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3; + to += 16; + bptr += 32; + len -= 16; + } while (len > 16); + break; + + /* XXX Does odd-byte-aligned case ever happen? */ + default: + do { + bcopy(bptr, to, 16); + to += 16; + bptr += 32; + len -= 16; + } while (len > 16); + break; + } + if (len) + bcopy(bptr, to, len); } void @@ -276,8 +420,8 @@ le_ioasic_zerobuf_gap16(sc, boff, len) int boff, len; { volatile caddr_t buf = sc->sc_mem; - register caddr_t bptr; - register int xfer; + caddr_t bptr; + int xfer; bptr = buf + ((boff << 1) & ~0x1f); boff &= 0xf; diff --git a/sys/dev/tc/if_le_tc.c b/sys/dev/tc/if_le_tc.c index 704449b4ef8..deb0c87ac63 100644 --- a/sys/dev/tc/if_le_tc.c +++ b/sys/dev/tc/if_le_tc.c @@ -1,5 +1,5 @@ -/* $OpenBSD: if_le_tc.c,v 1.5 2002/03/14 01:27:03 millert Exp $ */ -/* $NetBSD: if_le_tc.c,v 1.2 1996/05/07 02:24:57 thorpej Exp $ */ +/* $OpenBSD: if_le_tc.c,v 1.6 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: if_le_tc.c,v 1.12 2001/11/13 06:26:10 lukem Exp $ */ /* * Copyright (c) 1996 Carnegie-Mellon University. @@ -71,8 +71,7 @@ le_tc_match(parent, match, aux) { struct tc_attach_args *d = aux; - if (strncmp("PMAD-AA ", d->ta_modname, TC_ROM_LLEN) && - strncmp("PMAD-BA ", d->ta_modname, TC_ROM_LLEN)) + if (strncmp("PMAD-AA ", d->ta_modname, TC_ROM_LLEN) != 0) return (0); return (1); @@ -83,8 +82,8 @@ le_tc_attach(parent, self, aux) struct device *parent, *self; void *aux; { - register struct le_softc *lesc = (void *)self; - register struct am7990_softc *sc = &lesc->sc_am7990; + struct le_softc *lesc = (void *)self; + struct am7990_softc *sc = &lesc->sc_am7990; struct tc_attach_args *d = aux; /* @@ -106,7 +105,8 @@ le_tc_attach(parent, self, aux) * so DMA setup is not required. */ - dec_le_common_attach(sc, (u_char *)(d->ta_addr + LE_OFFSET_ROM + 2)); + dec_le_common_attach(&lesc->sc_am7990, + (u_char *)(d->ta_addr + LE_OFFSET_ROM + 2)); tc_intr_establish(parent, d->ta_cookie, TC_IPL_NET, am7990_intr, sc); } diff --git a/sys/dev/tc/if_levar.h b/sys/dev/tc/if_levar.h index 25843885576..1efab40ebee 100644 --- a/sys/dev/tc/if_levar.h +++ b/sys/dev/tc/if_levar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: if_levar.h,v 1.5 2002/03/14 01:27:03 millert Exp $ */ -/* $NetBSD: if_levar.h,v 1.3 1996/05/07 02:24:58 thorpej Exp $ */ +/* $OpenBSD: if_levar.h,v 1.6 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: if_levar.h,v 1.4 1997/03/15 18:12:07 is Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -57,7 +57,7 @@ struct lereg1 { * Ethernet software status per interface. * * Each interface is referenced by a network interface structure, - * arpcom.ac_if, which the routing code uses to locate the interface. + * ethercom.ec_if, which the routing code uses to locate the interface. * This structure contains the output queue for the interface, its address, ... */ struct le_softc { diff --git a/sys/dev/tc/ioasic_subr.c b/sys/dev/tc/ioasic_subr.c new file mode 100644 index 00000000000..bb3a4364da8 --- /dev/null +++ b/sys/dev/tc/ioasic_subr.c @@ -0,0 +1,86 @@ +/* $OpenBSD: ioasic_subr.c,v 1.1 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: ioasic_subr.c,v 1.3 2001/11/13 06:26:10 lukem Exp $ */ + +/* + * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Keith Bostic, Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <dev/tc/tcvar.h> +#include <dev/tc/ioasicvar.h> + +int ioasicprint(void *, const char *); + +int +ioasicprint(aux, pnp) + void *aux; + const char *pnp; +{ + struct ioasicdev_attach_args *d = aux; + + if (pnp) + printf("%s at %s", d->iada_modname, pnp); + printf(" offset 0x%lx", (long)d->iada_offset); + return (UNCONF); +} + +int +ioasic_submatch(vcf, d) + void *vcf; + struct ioasicdev_attach_args *d; +{ + struct cfdata *match = vcf; + + return ((match->ioasiccf_offset == d->iada_offset) || + (match->ioasiccf_offset == IOASIC_OFFSET_UNKNOWN)); +} + +void +ioasic_attach_devs(sc, ioasic_devs, ioasic_ndevs) + struct ioasic_softc *sc; + struct ioasic_dev *ioasic_devs; + int ioasic_ndevs; +{ + struct ioasicdev_attach_args idev; + int i; + + /* + * Try to configure each device. + */ + for (i = 0; i < ioasic_ndevs; i++) { + strncpy(idev.iada_modname, ioasic_devs[i].iad_modname, + TC_ROM_LLEN); + idev.iada_modname[TC_ROM_LLEN] = '\0'; + idev.iada_offset = ioasic_devs[i].iad_offset; + idev.iada_addr = sc->sc_base + ioasic_devs[i].iad_offset; + idev.iada_cookie = ioasic_devs[i].iad_cookie; + + /* Tell the autoconfig machinery we've found the hardware. */ + config_found(&sc->sc_dv, &idev, ioasicprint); + } +} diff --git a/sys/dev/tc/ioasicreg.h b/sys/dev/tc/ioasicreg.h new file mode 100644 index 00000000000..067c15a79ab --- /dev/null +++ b/sys/dev/tc/ioasicreg.h @@ -0,0 +1,204 @@ +/* $OpenBSD: ioasicreg.h,v 1.1 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: ioasicreg.h,v 1.6 2000/07/17 02:18:17 thorpej Exp $ */ + +/* + * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * The Mach Operating System project at Carnegie-Mellon University, + * Ralph Campbell and Rick Macklem. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)asic.h 8.1 (Berkeley) 6/10/93 + */ + +/* + * Slot definitions + */ + +#define IOASIC_SLOT_0_START 0x000000 +#define IOASIC_SLOT_1_START 0x040000 +#define IOASIC_SLOT_2_START 0x080000 +#define IOASIC_SLOT_3_START 0x0c0000 +#define IOASIC_SLOT_4_START 0x100000 +#define IOASIC_SLOT_5_START 0x140000 +#define IOASIC_SLOT_6_START 0x180000 +#define IOASIC_SLOT_7_START 0x1c0000 +#define IOASIC_SLOT_8_START 0x200000 +#define IOASIC_SLOT_9_START 0x240000 +#define IOASIC_SLOT_10_START 0x280000 +#define IOASIC_SLOT_11_START 0x2c0000 +#define IOASIC_SLOT_12_START 0x300000 +#define IOASIC_SLOT_13_START 0x340000 +#define IOASIC_SLOT_14_START 0x380000 +#define IOASIC_SLOT_15_START 0x3c0000 +#define IOASIC_SLOTS_END 0x3fffff + +/* + * Register offsets (slot 1) + */ + +#define IOASIC_SCSI_DMAPTR IOASIC_SLOT_1_START+0x000 +#define IOASIC_SCSI_NEXTPTR IOASIC_SLOT_1_START+0x010 +#define IOASIC_LANCE_DMAPTR IOASIC_SLOT_1_START+0x020 +#define IOASIC_SCC_T1_DMAPTR IOASIC_SLOT_1_START+0x030 +#define IOASIC_SCC_R1_DMAPTR IOASIC_SLOT_1_START+0x040 +#define IOASIC_SCC_T2_DMAPTR IOASIC_SLOT_1_START+0x050 +#define IOASIC_SCC_R2_DMAPTR IOASIC_SLOT_1_START+0x060 +#define IOASIC_FLOPPY_DMAPTR IOASIC_SLOT_1_START+0x070 +#define IOASIC_ISDN_X_DMAPTR IOASIC_SLOT_1_START+0x080 +#define IOASIC_ISDN_X_NEXTPTR IOASIC_SLOT_1_START+0x090 +#define IOASIC_ISDN_R_DMAPTR IOASIC_SLOT_1_START+0x0a0 +#define IOASIC_ISDN_R_NEXTPTR IOASIC_SLOT_1_START+0x0b0 +#define IOASIC_BUFF0 IOASIC_SLOT_1_START+0x0c0 +#define IOASIC_BUFF1 IOASIC_SLOT_1_START+0x0d0 +#define IOASIC_BUFF2 IOASIC_SLOT_1_START+0x0e0 +#define IOASIC_BUFF3 IOASIC_SLOT_1_START+0x0f0 +#define IOASIC_CSR IOASIC_SLOT_1_START+0x100 +#define IOASIC_INTR IOASIC_SLOT_1_START+0x110 +#define IOASIC_IMSK IOASIC_SLOT_1_START+0x120 +#define IOASIC_CURADDR IOASIC_SLOT_1_START+0x130 +#define IOASIC_ISDN_X_DATA IOASIC_SLOT_1_START+0x140 +#define IOASIC_ISDN_R_DATA IOASIC_SLOT_1_START+0x150 +#define IOASIC_LANCE_DECODE IOASIC_SLOT_1_START+0x160 +#define IOASIC_SCSI_DECODE IOASIC_SLOT_1_START+0x170 +#define IOASIC_SCC0_DECODE IOASIC_SLOT_1_START+0x180 +#define IOASIC_SCC1_DECODE IOASIC_SLOT_1_START+0x190 +#define IOASIC_FLOPPY_DECODE IOASIC_SLOT_1_START+0x1a0 +#define IOASIC_SCSI_SCR IOASIC_SLOT_1_START+0x1b0 +#define IOASIC_SCSI_SDR0 IOASIC_SLOT_1_START+0x1c0 +#define IOASIC_SCSI_SDR1 IOASIC_SLOT_1_START+0x1d0 +#define IOASIC_CTR IOASIC_SLOT_1_START+0x1e0 /*3max+/3000*/ + +/* System Status and control Register (SSR). */ +#define IOASIC_CSR_DMAEN_T1 0x80000000 /* rw */ +#define IOASIC_CSR_DMAEN_R1 0x40000000 /* rw */ +#define IOASIC_CSR_DMAEN_T2 0x20000000 /* rw */ +#define IOASIC_CSR_DMAEN_R2 0x10000000 /* rw */ +#define IOASIC_CSR_FASTMODE 0x08000000 /* rw - 3000 */ +#define IOASIC_CSR_xxx 0x07800000 /* reserved - 3000 */ +#define IOASIC_CSR_DS_xxx 0x0f800000 /* reserved - DS */ +#define IOASIC_CSR_FLOPPY_DIR 0x00400000 /* rw - maxine */ +#define IOASIC_CSR_DMAEN_FLOPPY 0x00200000 /* rw - maxine */ +#define IOASIC_CSR_DMAEN_ISDN_T 0x00100000 /* rw */ +#define IOASIC_CSR_DMAEN_ISDN_R 0x00080000 /* rw */ +#define IOASIC_CSR_SCSI_DIR 0x00040000 /* rw - DS */ +#define IOASIC_CSR_DMAEN_SCSI 0x00020000 /* rw - DS */ +#define IOASIC_CSR_DMAEN_LANCE 0x00010000 /* rw - DS */ +/* low 16 bits are rw gp outputs */ +#define IOASIC_CSR_DIAGDN 0x00008000 /* rw */ +#define IOASIC_CSR_TXDIS_2 0x00004000 /* rw - 3min,3max+ */ +#define IOASIC_CSR_TXDIS_1 0x00002000 /* rw - 3min,3max+ */ +#define IOASIC_CSR_ISDN_ENABLE 0x00001000 /* rw - 3000/maxine */ +#define IOASIC_CSR_SCC_ENABLE 0x00000800 /* rw */ +#define IOASIC_CSR_RTC_ENABLE 0x00000400 /* rw */ +#define IOASIC_CSR_SCSI_ENABLE 0x00000200 /* rw - DS */ +#define IOASIC_CSR_LANCE_ENABLE 0x00000100 /* rw */ + +/* System Interrupt Register (and Interrupt Mask Register). */ +#define IOASIC_INTR_T1_PAGE_END 0x80000000 /* rz */ +#define IOASIC_INTR_T1_READ_E 0x40000000 /* rz */ +#define IOASIC_INTR_R1_HALF_PAGE 0x20000000 /* rz */ +#define IOASIC_INTR_R1_DMA_OVRUN 0x10000000 /* rz */ +#define IOASIC_INTR_T2_PAGE_END 0x08000000 /* rz */ +#define IOASIC_INTR_T2_READ_E 0x04000000 /* rz */ +#define IOASIC_INTR_R2_HALF_PAGE 0x02000000 /* rz */ +#define IOASIC_INTR_R2_DMA_OVRUN 0x01000000 /* rz */ +#define IOASIC_INTR_FLOPPY_DMA_E 0x00800000 /* rz - maxine */ +#define IOASIC_INTR_ISDN_TXLOAD 0x00400000 /* rz - 3000/maxine */ +#define IOASIC_INTR_ISDN_RXLOAD 0x00200000 /* rz - 3000/maxine */ +#define IOASIC_INTR_ISDN_OVRUN 0x00100000 /* rz - 3000/maxine */ +#define IOASIC_INTR_SCSI_PTR_LOAD 0x00080000 /* rz - DS */ +#define IOASIC_INTR_SCSI_OVRUN 0x00040000 /* rz - DS */ +#define IOASIC_INTR_SCSI_READ_E 0x00020000 /* rz - DS */ +#define IOASIC_INTR_LANCE_READ_E 0x00010000 /* rz - DS */ + +/* low 16 bits are model-dependent; see also model specific *.h */ +#define IOASIC_INTR_NVR_JUMPER 0x00004000 /* ro */ +#define IOASIC_INTR_ISDN 0x00002000 /* ro - 3000 */ +#define IOASIC_INTR_NRMOD_JUMPER 0x00000400 /* ro */ +#define IOASIC_INTR_SEC_CON 0x00000200 /* ro */ +#define IOASIC_INTR_SCSI 0x00000200 /* ro - DS */ +#define IOASIC_INTR_LANCE 0x00000100 /* ro */ +#define IOASIC_INTR_SCC_1 0x00000080 /* ro */ +#define IOASIC_INTR_SCC_0 0x00000040 /* ro */ +#define IOASIC_INTR_ALT_CON 0x00000008 /* ro - 3000/500 */ +#define IOASIC_INTR_300_OPT1 0x00000008 /* ro - 3000/300 */ +#define IOASIC_INTR_300_OPT0 0x00000004 /* ro - 3000/300 */ + +/* DMA pointer registers (SCSI, Comm, ...) */ + +#define IOASIC_DMA_ADDR(p) \ + ((((p) << 3) & ~0x1f) | (((p) >> 29) & 0x1f)) +#define IOASIC_DMA_BLOCKSIZE 0x1000 + +/* For the LANCE DMA pointer register initialization the above suffices */ + +/* More SCSI DMA registers */ + +#define IOASIC_SCR_STATUS 0x00000004 +#define IOASIC_SCR_WORD 0x00000003 + +/* Various Decode registers */ + +#define IOASIC_DECODE_HW_ADDRESS 0x000003f0 +#define IOASIC_DECODE_CHIP_SELECT 0x0000000f + +/* + * And slot assignments. + */ +#define IOASIC_SYS_ETHER_ADDRESS(base) ((base) + IOASIC_SLOT_2_START) +#define IOASIC_SYS_LANCE(base) ((base) + IOASIC_SLOT_3_START) diff --git a/sys/dev/tc/ioasicvar.h b/sys/dev/tc/ioasicvar.h index fe00a3fe465..09b95ac8414 100644 --- a/sys/dev/tc/ioasicvar.h +++ b/sys/dev/tc/ioasicvar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: ioasicvar.h,v 1.5 2002/03/14 03:16:08 millert Exp $ */ -/* $NetBSD: ioasicvar.h,v 1.2 1996/03/17 21:37:45 jonathan Exp $ */ +/* $OpenBSD: ioasicvar.h,v 1.6 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: ioasicvar.h,v 1.14 2000/10/17 09:45:49 nisimura Exp $ */ /* * Copyright (c) 1995 Carnegie-Mellon University. @@ -28,11 +28,16 @@ * rights to redistribute these changes. */ -/* - * IOASIC subdevice attachment information. - */ +#ifndef _DEV_TC_IOASICVAR_H_ +#define _DEV_TC_IOASICVAR_H_ + +struct ioasic_dev { + char *iad_modname; + tc_offset_t iad_offset; + void *iad_cookie; + u_int32_t iad_intrbits; +}; -/* Attachment arguments. */ struct ioasicdev_attach_args { char iada_modname[TC_ROM_LLEN]; tc_offset_t iada_offset; @@ -45,30 +50,28 @@ struct ioasicdev_attach_args { #define IOASIC_OFFSET_UNKNOWN -1 -/* - * The IOASIC (bus) cfdriver, so that subdevices can more - * easily tell what bus they're on. - */ -extern struct cfdriver ioasic_cd; +struct ioasic_softc { + struct device sc_dv; + bus_space_tag_t sc_bst; + bus_space_handle_t sc_bsh; + bus_dma_tag_t sc_dmat; + + tc_addr_t sc_base; /* XXX offset XXX */ +}; +extern struct cfdriver ioasic_cd; /* * XXX Some drivers need direct access to IOASIC registers. */ extern tc_addr_t ioasic_base; - -/* - * Interrupt establishment/disestablishment functions - */ -void ioasic_intr_establish(struct device *, void *, tc_intrlevel_t, - int (*)(void *), void *); +const struct evcnt *ioasic_intr_evcnt(struct device *, void *); +void ioasic_intr_establish(struct device *, void *, + int, int (*)(void *), void *); void ioasic_intr_disestablish(struct device *, void *); +int ioasic_submatch(void *, struct ioasicdev_attach_args *); +void ioasic_attach_devs(struct ioasic_softc *, + struct ioasic_dev *, int); - -/* - * Miscellaneous helper functions. - */ -int ioasic_submatch(struct cfdata *, struct ioasicdev_attach_args *); -char *ioasic_lance_ether_address(void); -void ioasic_lance_dma_setup(void *); +#endif /* _DEV_TC_IOASICVAR_ */ diff --git a/sys/dev/tc/tc.c b/sys/dev/tc/tc.c index 63a132da7a3..d11a1375ba9 100644 --- a/sys/dev/tc/tc.c +++ b/sys/dev/tc/tc.c @@ -1,5 +1,5 @@ -/* $OpenBSD: tc.c,v 1.11 2002/03/14 03:16:08 millert Exp $ */ -/* $NetBSD: tc.c,v 1.20 1996/10/22 21:37:29 cgd Exp $ */ +/* $OpenBSD: tc.c,v 1.12 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: tc.c,v 1.29 2001/11/13 06:26:10 lukem Exp $ */ /* * Copyright (c) 1994, 1995 Carnegie-Mellon University. @@ -36,19 +36,6 @@ #include <dev/tc/tcvar.h> #include <dev/tc/tcdevs.h> -#include <machine/autoconf.h> /* for the proto of badaddr() */ - -struct tc_softc { - struct device sc_dv; - - int sc_speed; - int sc_nslots; - struct tc_slotdesc *sc_slots; - - void (*sc_intr_establish)(struct device *, void *, - tc_intrlevel_t, int (*)(void *), void *); - void (*sc_intr_disestablish)(struct device *, void *); -}; /* Definition of the driver for autoconfig. */ int tcmatch(struct device *, void *, void *); @@ -68,13 +55,12 @@ int tc_checkslot(tc_addr_t, char *); void tc_devinfo(const char *, char *); int -tcmatch(parent, cfdata, aux) +tcmatch(parent, vcf, aux) struct device *parent; - void *cfdata; - void *aux; + void *vcf, *aux; { - struct cfdata *cf = cfdata; struct tcbus_attach_args *tba = aux; + struct cfdata *cf = vcf; if (strcmp(tba->tba_busname, cf->cf_driver->cd_name)) return (0); @@ -105,8 +91,10 @@ tcattach(parent, self, aux) sc->sc_speed = tba->tba_speed; sc->sc_nslots = tba->tba_nslots; sc->sc_slots = tba->tba_slots; + sc->sc_intr_evcnt = tba->tba_intr_evcnt; sc->sc_intr_establish = tba->tba_intr_establish; sc->sc_intr_disestablish = tba->tba_intr_disestablish; + sc->sc_get_dma_tag = tba->tba_get_dma_tag; /* * Try to configure each built-in device @@ -131,9 +119,8 @@ tcattach(parent, self, aux) * Set up the device attachment information. */ strncpy(ta.ta_modname, builtin->tcb_modname, TC_ROM_LLEN); -#ifdef __alpha__ /* XXX */ ta.ta_memt = tba->tba_memt; -#endif + ta.ta_dmat = (*sc->sc_get_dma_tag)(builtin->tcb_slot); ta.ta_modname[TC_ROM_LLEN] = '\0'; ta.ta_slot = builtin->tcb_slot; ta.ta_offset = builtin->tcb_offset; @@ -174,6 +161,8 @@ tcattach(parent, self, aux) /* * Set up the rest of the attachment information. */ + ta.ta_memt = tba->tba_memt; + ta.ta_dmat = (*sc->sc_get_dma_tag)(i); ta.ta_slot = i; ta.ta_offset = 0; ta.ta_addr = tcaddr; @@ -209,12 +198,12 @@ tcprint(aux, pnp) } int -tcsubmatch(parent, match, aux) +tcsubmatch(parent, vcf, aux) struct device *parent; - void *match, *aux; + void *vcf, *aux; { - struct cfdata *cf = match; struct tc_attach_args *d = aux; + struct cfdata *cf = vcf; if ((cf->tccf_slot != TCCF_SLOT_UNKNOWN) && (cf->tccf_slot != d->ta_slot)) @@ -223,7 +212,7 @@ tcsubmatch(parent, match, aux) (cf->tccf_offset != d->ta_offset)) return 0; - return ((*cf->cf_attach->ca_match)(parent, match, aux)); + return ((*cf->cf_attach->ca_match)(parent, cf, aux)); } @@ -273,17 +262,24 @@ tc_checkslot(slotbase, namep) return (0); } +const struct evcnt * +tc_intr_evcnt(struct device *dev, void *cookie) +{ + struct tc_softc *sc = tc_cd.cd_devs[0]; + + return ((*sc->sc_intr_evcnt)(dev, cookie)); +} + void tc_intr_establish(dev, cookie, level, handler, arg) struct device *dev; void *cookie, *arg; - tc_intrlevel_t level; + int level; int (*handler)(void *); { - struct tc_softc *sc = (struct tc_softc *)dev; + struct tc_softc *sc = tc_cd.cd_devs[0]; - (*sc->sc_intr_establish)(sc->sc_dv.dv_parent, cookie, level, - handler, arg); + (*sc->sc_intr_establish)(dev, cookie, level, handler, arg); } void @@ -291,9 +287,9 @@ tc_intr_disestablish(dev, cookie) struct device *dev; void *cookie; { - struct tc_softc *sc = (struct tc_softc *)dev; + struct tc_softc *sc = tc_cd.cd_devs[0]; - (*sc->sc_intr_disestablish)(sc->sc_dv.dv_parent, cookie); + (*sc->sc_intr_disestablish)(dev, cookie); } #ifdef TCVERBOSE diff --git a/sys/dev/tc/tcdevs b/sys/dev/tc/tcdevs index cdf9662c160..0f6558ee15a 100644 --- a/sys/dev/tc/tcdevs +++ b/sys/dev/tc/tcdevs @@ -1,5 +1,5 @@ -$OpenBSD: tcdevs,v 1.5 1998/06/23 23:26:18 deraadt Exp $ -/* $NetBSD: tcdevs,v 1.6 1996/08/26 23:39:34 cgd Exp $ */ +$OpenBSD: tcdevs,v 1.6 2002/05/02 22:56:06 miod Exp $ +/* $NetBSD: tcdevs,v 1.17 2000/12/17 13:56:05 ad Exp $ */ /* * Copyright (c) 1996 Christopher G. Demetriou @@ -32,21 +32,26 @@ $OpenBSD: tcdevs,v 1.5 1998/06/23 23:26:18 deraadt Exp $ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -+device AV01B-AA lofi DecAudio LoFi audio/isdn +device AV01B-AA lofi DecAudio \"LoFi\" audio/isdn +device AV300-AA ??? Video capture option card device DGLTA-FA otto DGLTA ATM device FORE_ATM fa Fore TCA-100 ATM device KZTSA-AA tza TZA FWD SCSI -device OTTO otto DEC SRC OTTO ATM +device OTTO otto DEC SRC \"OTTO\" ATM device PMAD-AA le LANCE Ethernet -device PMAF-AA fza DEFZA FDDI -device PMAF-F fta DEFTA FDDI +device PMAF-AA fza DEC FDDIcontroller 700 (DEFZA; fiber optic) +device PMAF-FA fta DEFTA FDDI device PMAG-AA mfb Monochrome Frame Buffer device PMAG-BA cfb Color Frame Buffer -device PMAG-CA ga 2D Graphics -device PMAG-DA gq 3D Graphics (LM) +device PMAG-CA px 2D Graphics (PX 2DA) +device PMAG-DA pxg 3D Graphics (PXG LM-3DA) +device PMAG-FA pxg 3D Graphics (PXG HE-3DA) +device PMAG-FB pxg 3D Graphics (PXG HE+3DA) +device PMAGB-FA pxg 3D Graphics (PXG HE+3DA) +device PMAGB-FB pxg 3D Graphics (PXG HE+3DA) # the following entry may be incorrect device PMAG-DV xcfb Maxine Color Frame Buffer -device PMAG-FA gq 3D Graphics (HE) +device PMAG-JA ??? 24-plane True Color Frame Buffer (TX) device PMAGB-BA sfb Smart Frame Buffer device PMAGD sfbp Smart Frame Buffer Plus, unknown bpp device PMAGD-AA sfbp Smart Frame Buffer Plus, 8bpp @@ -55,6 +60,25 @@ device PMAZ-AA asc 53c94 SCSI device PMAZ-DS tcds 53c94 TCDS SCSI (baseboard) device PMAZ-FS tcds 53c94 TCDS Fast SCSI (baseboard) device PMAZB-AA tcds 53c94 TCDS SCSI option card +device PMAZB-AB tcds 53c94 TCDS SCSI option card device PMAZC-AA tcds 53c94 TCDS Fast SCSI option card +device PMTNV-AA ??? Non-volatile RAM option card device T1D4PKT ds DECWRL Turbochannel T1 device T3PKT tt DECWRL Turbochannel T3 +device PMAT-AA tra DEC TurboChannel Token Ring Controller +device PMABV-AA vba VME Adapter +device PMAP-AA ??? Prestoserve +device KWS_TD ??? Kubota Denali + +# the following entries are unconfirmed +#device PMAD-AB le LANCE Ethernet +#device PMAF-CA fza DEC FDDIcontroller 700C (DEFZA; copper) +#device PMAG-DB ??? 8-plane 3D Grahpics (PXG) +#device PMAG-AB ??? Monochrome Graphics Adapter (MX) +#device PMAG-JB ??? 24-plane True Color Frame Buffer (TX) +#device PMAGB-BB ??? 8-plane Color/Grayscale 2D SFB (HX) +#device PMAGB-BC ??? 8-plane Color/Grayscale 2D SFB (HX) +#define PMAGB-BD ??? 8-plane Color/Grayscale 2D SFB (HX) +#define PMAGB-BE ??? 8-plane Color/Grayscale 2D SFB (HX) +#device PMAGB-JB ??? 24-plane True Color Frame Buffer (TX) +#device PMAZ-AB asc 53c94 SCSI diff --git a/sys/dev/tc/tcdevs.h b/sys/dev/tc/tcdevs.h index eaa29b985ea..9d4329fcb56 100644 --- a/sys/dev/tc/tcdevs.h +++ b/sys/dev/tc/tcdevs.h @@ -1,10 +1,12 @@ +/* $OpenBSD: tcdevs.h,v 1.6 2002/05/02 22:56:06 miod Exp $ */ + /* * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: tcdevs,v 1.5 1998/06/23 23:26:18 deraadt Exp + * OpenBSD */ -/* $NetBSD: tcdevs,v 1.6 1996/08/26 23:39:34 cgd Exp $ */ +/* $NetBSD: tcdevs,v 1.17 2000/12/17 13:56:05 ad Exp $ */ /* * Copyright (c) 1996 Christopher G. Demetriou @@ -37,6 +39,12 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#define TC_DEVICE_AV01B_AA "lofi" +#define TC_DESCRIPTION_AV01B_AA "DecAudio \"LoFi\" audio/isdn" + +#define TC_DEVICE_AV300_AA "???" +#define TC_DESCRIPTION_AV300_AA "Video capture option card" + #define TC_DEVICE_DGLTA_FA "otto" #define TC_DESCRIPTION_DGLTA_FA "DGLTA ATM" @@ -47,16 +55,16 @@ #define TC_DESCRIPTION_KZTSA_AA "TZA FWD SCSI" #define TC_DEVICE_OTTO "otto" -#define TC_DESCRIPTION_OTTO "DEC SRC OTTO ATM" +#define TC_DESCRIPTION_OTTO "DEC SRC \"OTTO\" ATM" #define TC_DEVICE_PMAD_AA "le" #define TC_DESCRIPTION_PMAD_AA "LANCE Ethernet" #define TC_DEVICE_PMAF_AA "fza" -#define TC_DESCRIPTION_PMAF_AA "DEFZA FDDI" +#define TC_DESCRIPTION_PMAF_AA "DEC FDDIcontroller 700 (DEFZA; fiber optic)" -#define TC_DEVICE_PMAF_F "fta" -#define TC_DESCRIPTION_PMAF_F "DEFTA FDDI" +#define TC_DEVICE_PMAF_FA "fta" +#define TC_DESCRIPTION_PMAF_FA "DEFTA FDDI" #define TC_DEVICE_PMAG_AA "mfb" #define TC_DESCRIPTION_PMAG_AA "Monochrome Frame Buffer" @@ -64,17 +72,29 @@ #define TC_DEVICE_PMAG_BA "cfb" #define TC_DESCRIPTION_PMAG_BA "Color Frame Buffer" -#define TC_DEVICE_PMAG_CA "ga" -#define TC_DESCRIPTION_PMAG_CA "2D Graphics" +#define TC_DEVICE_PMAG_CA "px" +#define TC_DESCRIPTION_PMAG_CA "2D Graphics (PX 2DA)" + +#define TC_DEVICE_PMAG_DA "pxg" +#define TC_DESCRIPTION_PMAG_DA "3D Graphics (PXG LM-3DA)" + +#define TC_DEVICE_PMAG_FA "pxg" +#define TC_DESCRIPTION_PMAG_FA "3D Graphics (PXG HE-3DA)" + +#define TC_DEVICE_PMAG_FB "pxg" +#define TC_DESCRIPTION_PMAG_FB "3D Graphics (PXG HE+3DA)" + +#define TC_DEVICE_PMAGB_FA "pxg" +#define TC_DESCRIPTION_PMAGB_FA "3D Graphics (PXG HE+3DA)" -#define TC_DEVICE_PMAG_DA "gq" -#define TC_DESCRIPTION_PMAG_DA "3D Graphics (LM)" +#define TC_DEVICE_PMAGB_FB "pxg" +#define TC_DESCRIPTION_PMAGB_FB "3D Graphics (PXG HE+3DA)" #define TC_DEVICE_PMAG_DV "xcfb" #define TC_DESCRIPTION_PMAG_DV "Maxine Color Frame Buffer" -#define TC_DEVICE_PMAG_FA "gq" -#define TC_DESCRIPTION_PMAG_FA "3D Graphics (HE)" +#define TC_DEVICE_PMAG_JA "???" +#define TC_DESCRIPTION_PMAG_JA "24-plane True Color Frame Buffer (TX)" #define TC_DEVICE_PMAGB_BA "sfb" #define TC_DESCRIPTION_PMAGB_BA "Smart Frame Buffer" @@ -100,11 +120,29 @@ #define TC_DEVICE_PMAZB_AA "tcds" #define TC_DESCRIPTION_PMAZB_AA "53c94 TCDS SCSI option card" +#define TC_DEVICE_PMAZB_AB "tcds" +#define TC_DESCRIPTION_PMAZB_AB "53c94 TCDS SCSI option card" + #define TC_DEVICE_PMAZC_AA "tcds" #define TC_DESCRIPTION_PMAZC_AA "53c94 TCDS Fast SCSI option card" +#define TC_DEVICE_PMTNV_AA "???" +#define TC_DESCRIPTION_PMTNV_AA "Non-volatile RAM option card" + #define TC_DEVICE_T1D4PKT "ds" #define TC_DESCRIPTION_T1D4PKT "DECWRL Turbochannel T1" #define TC_DEVICE_T3PKT "tt" #define TC_DESCRIPTION_T3PKT "DECWRL Turbochannel T3" + +#define TC_DEVICE_PMAT_AA "tra" +#define TC_DESCRIPTION_PMAT_AA "DEC TurboChannel Token Ring Controller" + +#define TC_DEVICE_PMABV_AA "vba" +#define TC_DESCRIPTION_PMABV_AA "VME Adapter" + +#define TC_DEVICE_PMAP_AA "???" +#define TC_DESCRIPTION_PMAP_AA "Prestoserve" + +#define TC_DEVICE_KWS_TD "???" +#define TC_DESCRIPTION_KWS_TD "Kubota Denali" diff --git a/sys/dev/tc/tcdevs_data.h b/sys/dev/tc/tcdevs_data.h index 26bd3621093..c16f2ea9a9f 100644 --- a/sys/dev/tc/tcdevs_data.h +++ b/sys/dev/tc/tcdevs_data.h @@ -1,10 +1,12 @@ +/* $OpenBSD: tcdevs_data.h,v 1.6 2002/05/02 22:56:06 miod Exp $ */ + /* * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT. * * generated from: - * OpenBSD: tcdevs,v 1.5 1998/06/23 23:26:18 deraadt Exp + * OpenBSD */ -/* $NetBSD: tcdevs,v 1.6 1996/08/26 23:39:34 cgd Exp $ */ +/* $NetBSD: tcdevs,v 1.17 2000/12/17 13:56:05 ad Exp $ */ /* * Copyright (c) 1996 Christopher G. Demetriou @@ -39,6 +41,16 @@ struct tc_knowndev tc_knowndevs[] = { { + "AV01B-AA", + TC_DEVICE_AV01B_AA, + TC_DESCRIPTION_AV01B_AA, + }, + { + "AV300-AA", + TC_DEVICE_AV300_AA, + TC_DESCRIPTION_AV300_AA, + }, + { "DGLTA-FA", TC_DEVICE_DGLTA_FA, TC_DESCRIPTION_DGLTA_FA, @@ -69,9 +81,9 @@ struct tc_knowndev tc_knowndevs[] = { TC_DESCRIPTION_PMAF_AA, }, { - "PMAF-F ", - TC_DEVICE_PMAF_F, - TC_DESCRIPTION_PMAF_F, + "PMAF-FA ", + TC_DEVICE_PMAF_FA, + TC_DESCRIPTION_PMAF_FA, }, { "PMAG-AA ", @@ -94,14 +106,34 @@ struct tc_knowndev tc_knowndevs[] = { TC_DESCRIPTION_PMAG_DA, }, { + "PMAG-FA ", + TC_DEVICE_PMAG_FA, + TC_DESCRIPTION_PMAG_FA, + }, + { + "PMAG-FB ", + TC_DEVICE_PMAG_FB, + TC_DESCRIPTION_PMAG_FB, + }, + { + "PMAGB-FA", + TC_DEVICE_PMAGB_FA, + TC_DESCRIPTION_PMAGB_FA, + }, + { + "PMAGB-FB", + TC_DEVICE_PMAGB_FB, + TC_DESCRIPTION_PMAGB_FB, + }, + { "PMAG-DV ", TC_DEVICE_PMAG_DV, TC_DESCRIPTION_PMAG_DV, }, { - "PMAG-FA ", - TC_DEVICE_PMAG_FA, - TC_DESCRIPTION_PMAG_FA, + "PMAG-JA ", + TC_DEVICE_PMAG_JA, + TC_DESCRIPTION_PMAG_JA, }, { "PMAGB-BA", @@ -144,11 +176,21 @@ struct tc_knowndev tc_knowndevs[] = { TC_DESCRIPTION_PMAZB_AA, }, { + "PMAZB-AB", + TC_DEVICE_PMAZB_AB, + TC_DESCRIPTION_PMAZB_AB, + }, + { "PMAZC-AA", TC_DEVICE_PMAZC_AA, TC_DESCRIPTION_PMAZC_AA, }, { + "PMTNV-AA", + TC_DEVICE_PMTNV_AA, + TC_DESCRIPTION_PMTNV_AA, + }, + { "T1D4PKT ", TC_DEVICE_T1D4PKT, TC_DESCRIPTION_T1D4PKT, @@ -158,5 +200,25 @@ struct tc_knowndev tc_knowndevs[] = { TC_DEVICE_T3PKT, TC_DESCRIPTION_T3PKT, }, + { + "PMAT-AA ", + TC_DEVICE_PMAT_AA, + TC_DESCRIPTION_PMAT_AA, + }, + { + "PMABV-AA", + TC_DEVICE_PMABV_AA, + TC_DESCRIPTION_PMABV_AA, + }, + { + "PMAP-AA ", + TC_DEVICE_PMAP_AA, + TC_DESCRIPTION_PMAP_AA, + }, + { + "KWS_TD ", + TC_DEVICE_KWS_TD, + TC_DESCRIPTION_KWS_TD, + }, { NULL, NULL, NULL, } }; diff --git a/sys/dev/tc/tcds.c b/sys/dev/tc/tcds.c new file mode 100644 index 00000000000..a69e5c7805f --- /dev/null +++ b/sys/dev/tc/tcds.c @@ -0,0 +1,602 @@ +/* $OpenBSD: tcds.c,v 1.1 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: tcds.c,v 1.3 2001/11/13 06:26:10 lukem Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Keith Bostic, Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +#include <sys/param.h> +#include <sys/kernel.h> +#include <sys/systm.h> +#include <sys/device.h> +#include <sys/malloc.h> + +#ifdef __alpha__ +#include <machine/rpb.h> +#endif /* __alpha__ */ + +#include <scsi/scsi_all.h> +#include <scsi/scsiconf.h> + +#include <dev/ic/ncr53c9xvar.h> + +#include <machine/bus.h> + +#ifndef EVCNT_COUNTERS +#include <machine/intrcnt.h> +#endif + +#include <dev/tc/tcvar.h> +#include <dev/tc/tcdsreg.h> +#include <dev/tc/tcdsvar.h> + +struct tcds_softc { + struct device sc_dv; + bus_space_tag_t sc_bst; + bus_space_handle_t sc_bsh; + bus_dma_tag_t sc_dmat; + void *sc_cookie; + int sc_flags; + struct tcds_slotconfig sc_slots[2]; +}; + +/* sc_flags */ +#define TCDSF_BASEBOARD 0x01 /* baseboard on DEC 3000 */ +#define TCDSF_FASTSCSI 0x02 /* supports Fast SCSI */ + +/* Definition of the driver for autoconfig. */ +int tcdsmatch(struct device *, void *, void *); +void tcdsattach(struct device *, struct device *, void *); +int tcdsprint(void *, const char *); +int tcdssubmatch(struct device *, void *, void *); + +struct cfattach tcds_ca = { + sizeof(struct tcds_softc), tcdsmatch, tcdsattach, +}; + +struct cfdriver tcds_cd = { + NULL, "tcds", DV_DULL, +}; + +/*static*/ int tcds_intr(void *); +/*static*/ int tcds_intrnull(void *); + +struct tcds_device { + const char *td_name; + int td_flags; +} tcds_devices[] = { +#ifdef __alpha__ + { "PMAZ-DS ", TCDSF_BASEBOARD }, + { "PMAZ-FS ", TCDSF_BASEBOARD|TCDSF_FASTSCSI }, +#endif /* __alpha__ */ + { "PMAZB-AA", 0 }, + { "PMAZC-AA", TCDSF_FASTSCSI }, + { NULL, 0 }, +}; + +struct tcds_device *tcds_lookup(const char *); +void tcds_params(struct tcds_softc *, int, int *, int *); + +struct tcds_device * +tcds_lookup(modname) + const char *modname; +{ + struct tcds_device *td; + + for (td = tcds_devices; td->td_name != NULL; td++) + if (strncmp(td->td_name, modname, TC_ROM_LLEN) == 0) + return (td); + + return (NULL); +} + +int +tcdsmatch(parent, cfdata, aux) + struct device *parent; + void *cfdata, *aux; +{ + struct tc_attach_args *ta = aux; + + return (tcds_lookup(ta->ta_modname) != NULL); +} + +void +tcdsattach(parent, self, aux) + struct device *parent, *self; + void *aux; +{ + struct tcds_softc *sc = (struct tcds_softc *)self; + struct tc_attach_args *ta = aux; + struct tcdsdev_attach_args tcdsdev; + struct tcds_slotconfig *slotc; + struct tcds_device *td; + bus_space_handle_t sbsh[2]; + int i, gpi2; + const struct evcnt *pevcnt; + + td = tcds_lookup(ta->ta_modname); + if (td == NULL) + panic("\ntcdsattach: impossible"); + + printf(": TurboChannel Dual SCSI"); + if (td->td_flags & TCDSF_BASEBOARD) + printf(" (baseboard)"); + printf("\n"); + + sc->sc_flags = td->td_flags; + + sc->sc_bst = ta->ta_memt; + sc->sc_dmat = ta->ta_dmat; + + /* + * Map the device. + */ + if (bus_space_map(sc->sc_bst, ta->ta_addr, + (TCDS_SCSI1_OFFSET + 0x100), 0, &sc->sc_bsh)) { + printf("%s: unable to map device\n", sc->sc_dv.dv_xname); + return; + } + + /* + * Now, slice off two subregions for the individual NCR SCSI chips. + */ + if (bus_space_subregion(sc->sc_bst, sc->sc_bsh, TCDS_SCSI0_OFFSET, + 0x100, &sbsh[0]) || + bus_space_subregion(sc->sc_bst, sc->sc_bsh, TCDS_SCSI1_OFFSET, + 0x100, &sbsh[1])) { + printf("%s: unable to subregion SCSI chip space\n", + sc->sc_dv.dv_xname); + return; + } + + sc->sc_cookie = ta->ta_cookie; + + pevcnt = tc_intr_evcnt(parent, sc->sc_cookie); + tc_intr_establish(parent, sc->sc_cookie, TC_IPL_BIO, tcds_intr, sc); + + /* + * XXX + * IMER apparently has some random (or, not so random, but still + * not useful) bits set in it when the system boots. Clear it. + */ + bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER, 0); + + /* XXX Initial contents of CIR? */ + + /* + * Remember if GPI2 is set in the CIR; we'll need it later. + */ + gpi2 = (bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR) & + TCDS_CIR_GPI_2) != 0; + + /* + * Set up the per-slot defintions for later use. + */ + + /* fill in common information first */ + for (i = 0; i < 2; i++) { + char *cp; + + slotc = &sc->sc_slots[i]; + bzero(slotc, sizeof *slotc); /* clear everything */ + + cp = slotc->sc_name; + snprintf(cp, sizeof(slotc->sc_name), "chip %d", i); +#ifdef EVCNT_COUNTERS + evcnt_attach_dynamic(&slotc->sc_evcnt, EVCNT_TYPE_INTR, + pevcnt, sc->sc_dv.dv_xname, cp); +#endif + + slotc->sc_slot = i; + slotc->sc_bst = sc->sc_bst; + slotc->sc_bsh = sc->sc_bsh; + slotc->sc_intrhand = tcds_intrnull; + slotc->sc_intrarg = (void *)(long)i; + } + + /* information for slot 0 */ + slotc = &sc->sc_slots[0]; + slotc->sc_resetbits = TCDS_CIR_SCSI0_RESET; + slotc->sc_intrmaskbits = + TCDS_IMER_SCSI0_MASK | TCDS_IMER_SCSI0_ENB; + slotc->sc_intrbits = TCDS_CIR_SCSI0_INT; + slotc->sc_dmabits = TCDS_CIR_SCSI0_DMAENA; + slotc->sc_errorbits = 0; /* XXX */ + slotc->sc_sda = TCDS_SCSI0_DMA_ADDR; + slotc->sc_dic = TCDS_SCSI0_DMA_INTR; + slotc->sc_dud0 = TCDS_SCSI0_DMA_DUD0; + slotc->sc_dud1 = TCDS_SCSI0_DMA_DUD1; + + /* information for slot 1 */ + slotc = &sc->sc_slots[1]; + slotc->sc_resetbits = TCDS_CIR_SCSI1_RESET; + slotc->sc_intrmaskbits = + TCDS_IMER_SCSI1_MASK | TCDS_IMER_SCSI1_ENB; + slotc->sc_intrbits = TCDS_CIR_SCSI1_INT; + slotc->sc_dmabits = TCDS_CIR_SCSI1_DMAENA; + slotc->sc_errorbits = 0; /* XXX */ + slotc->sc_sda = TCDS_SCSI1_DMA_ADDR; + slotc->sc_dic = TCDS_SCSI1_DMA_INTR; + slotc->sc_dud0 = TCDS_SCSI1_DMA_DUD0; + slotc->sc_dud1 = TCDS_SCSI1_DMA_DUD1; + + /* find the hardware attached to the TCDS ASIC */ + for (i = 0; i < 2; i++) { + tcds_params(sc, i, &tcdsdev.tcdsda_id, + &tcdsdev.tcdsda_fast); + + tcdsdev.tcdsda_bst = sc->sc_bst; + tcdsdev.tcdsda_bsh = sbsh[i]; + tcdsdev.tcdsda_dmat = sc->sc_dmat; + tcdsdev.tcdsda_chip = i; + tcdsdev.tcdsda_sc = &sc->sc_slots[i]; + /* + * Determine the chip frequency. TCDSF_FASTSCSI will be set + * for TC option cards. For baseboard chips, GPI2 is set, for a + * 25MHz clock, else a 40MHz clock. + */ + if ((sc->sc_flags & TCDSF_BASEBOARD && gpi2 == 0) || + sc->sc_flags & TCDSF_FASTSCSI) { + tcdsdev.tcdsda_freq = 40000000; + tcdsdev.tcdsda_period = tcdsdev.tcdsda_fast ? 4 : 8; + } else { + tcdsdev.tcdsda_freq = 25000000; + tcdsdev.tcdsda_period = 5; + } + if (sc->sc_flags & TCDSF_BASEBOARD) + tcdsdev.tcdsda_variant = NCR_VARIANT_NCR53C94; + else + tcdsdev.tcdsda_variant = NCR_VARIANT_NCR53C96; + + tcds_scsi_reset(tcdsdev.tcdsda_sc); + + config_found_sm(self, &tcdsdev, tcdsprint, tcdssubmatch); +#ifdef __alpha__ + /* + * The second SCSI chip isn't present on the baseboard TCDS + * on the DEC Alpha 3000/300 series. + */ + if (sc->sc_flags & TCDSF_BASEBOARD && + cputype == ST_DEC_3000_300) + break; +#endif /* __alpha__ */ + } +} + +int +tcdssubmatch(parent, vcf, aux) + struct device *parent; + void *vcf, *aux; +{ + struct tcdsdev_attach_args *tcdsdev = aux; + struct cfdata *cf = vcf; + + if (cf->cf_loc[0] != -1 && + cf->cf_loc[0] != tcdsdev->tcdsda_chip) + return (0); + + return ((*cf->cf_attach->ca_match)(parent, vcf, aux)); +} + +int +tcdsprint(aux, pnp) + void *aux; + const char *pnp; +{ + struct tcdsdev_attach_args *tcdsdev = aux; + + /* Only ASCs can attach to TCDSs; easy. */ + if (pnp) + printf("asc at %s", pnp); + + printf(" chip %d", tcdsdev->tcdsda_chip); + + return (UNCONF); +} + +void +tcds_intr_establish(tcds, slot, func, arg) + struct device *tcds; + int slot; + int (*func)(void *); + void *arg; +{ + struct tcds_softc *sc = (struct tcds_softc *)tcds; + + if (sc->sc_slots[slot].sc_intrhand != tcds_intrnull) + panic("tcds_intr_establish: chip %d twice", slot); + + sc->sc_slots[slot].sc_intrhand = func; + sc->sc_slots[slot].sc_intrarg = arg; + tcds_scsi_reset(&sc->sc_slots[slot]); +} + +void +tcds_intr_disestablish(tcds, slot) + struct device *tcds; + int slot; +{ + struct tcds_softc *sc = (struct tcds_softc *)tcds; + + if (sc->sc_slots[slot].sc_intrhand == tcds_intrnull) + panic("tcds_intr_disestablish: chip %d missing intr", + slot); + + sc->sc_slots[slot].sc_intrhand = tcds_intrnull; + sc->sc_slots[slot].sc_intrarg = (void *)(u_long)slot; + + tcds_dma_enable(&sc->sc_slots[slot], 0); + tcds_scsi_enable(&sc->sc_slots[slot], 0); +} + +int +tcds_intrnull(val) + void *val; +{ + + panic("tcds_intrnull: uncaught TCDS intr for chip %lu\n", + (u_long)val); +} + +void +tcds_scsi_reset(sc) + struct tcds_slotconfig *sc; +{ + u_int32_t cir; + + tcds_dma_enable(sc, 0); + tcds_scsi_enable(sc, 0); + + cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); + TCDS_CIR_CLR(cir, sc->sc_resetbits); + bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); + + DELAY(1); + + cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); + TCDS_CIR_SET(cir, sc->sc_resetbits); + bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); + + tcds_scsi_enable(sc, 1); + tcds_dma_enable(sc, 1); +} + +void +tcds_scsi_enable(sc, on) + struct tcds_slotconfig *sc; + int on; +{ + u_int32_t imer; + + imer = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER); + + if (on) + imer |= sc->sc_intrmaskbits; + else + imer &= ~sc->sc_intrmaskbits; + + bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_IMER, imer); +} + +void +tcds_dma_enable(sc, on) + struct tcds_slotconfig *sc; + int on; +{ + u_int32_t cir; + + cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); + + /* XXX Clear/set IOSLOT/PBS bits. */ + if (on) + TCDS_CIR_SET(cir, sc->sc_dmabits); + else + TCDS_CIR_CLR(cir, sc->sc_dmabits); + + bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, cir); +} + +int +tcds_scsi_isintr(sc, clear) + struct tcds_slotconfig *sc; + int clear; +{ + u_int32_t cir; + + cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); + + if ((cir & sc->sc_intrbits) != 0) { + if (clear) { + TCDS_CIR_CLR(cir, sc->sc_intrbits); + bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, + cir); + } + return (1); + } else + return (0); +} + +int +tcds_scsi_iserr(sc) + struct tcds_slotconfig *sc; +{ + u_int32_t cir; + + cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); + return ((cir & sc->sc_errorbits) != 0); +} + +int +tcds_intr(arg) + void *arg; +{ + struct tcds_softc *sc = arg; + u_int32_t ir, ir0; + + /* + * XXX + * Copy and clear (gag!) the interrupts. + */ + ir = ir0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); + TCDS_CIR_CLR(ir0, TCDS_CIR_ALLINTR); + bus_space_write_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR, ir0); + tc_syncbus(); + +#ifdef EVCNT_COUNTERS +#define INCRINTRCNT(slot) sc->sc_slots[slot].sc_evcnt.ev_count++ +#else +#define INCRINTRCNT(slot) intrcnt[INTRCNT_TCDS + slot]++ +#endif + +#define CHECKINTR(slot) \ + if (ir & sc->sc_slots[slot].sc_intrbits) { \ + INCRINTRCNT(slot); \ + (void)(*sc->sc_slots[slot].sc_intrhand) \ + (sc->sc_slots[slot].sc_intrarg); \ + } + CHECKINTR(0); + CHECKINTR(1); +#undef CHECKINTR + +#ifdef DIAGNOSTIC + /* + * Interrupts not currently handled, but would like to know if they + * occur. + * + * XXX + * Don't know if we have to set the interrupt mask and enable bits + * in the IMER to allow some of them to happen? + */ +#define PRINTINTR(msg, bits) \ + if (ir & bits) \ + printf("%s: %s", sc->sc_dv.dv_xname, msg); + PRINTINTR("SCSI0 DREQ interrupt.\n", TCDS_CIR_SCSI0_DREQ); + PRINTINTR("SCSI1 DREQ interrupt.\n", TCDS_CIR_SCSI1_DREQ); + PRINTINTR("SCSI0 prefetch interrupt.\n", TCDS_CIR_SCSI0_PREFETCH); + PRINTINTR("SCSI1 prefetch interrupt.\n", TCDS_CIR_SCSI1_PREFETCH); + PRINTINTR("SCSI0 DMA error.\n", TCDS_CIR_SCSI0_DMA); + PRINTINTR("SCSI1 DMA error.\n", TCDS_CIR_SCSI1_DMA); + PRINTINTR("SCSI0 DB parity error.\n", TCDS_CIR_SCSI0_DB); + PRINTINTR("SCSI1 DB parity error.\n", TCDS_CIR_SCSI1_DB); + PRINTINTR("SCSI0 DMA buffer parity error.\n", TCDS_CIR_SCSI0_DMAB_PAR); + PRINTINTR("SCSI1 DMA buffer parity error.\n", TCDS_CIR_SCSI1_DMAB_PAR); + PRINTINTR("SCSI0 DMA read parity error.\n", TCDS_CIR_SCSI0_DMAR_PAR); + PRINTINTR("SCSI1 DMA read parity error.\n", TCDS_CIR_SCSI1_DMAR_PAR); + PRINTINTR("TC write parity error.\n", TCDS_CIR_TCIOW_PAR); + PRINTINTR("TC I/O address parity error.\n", TCDS_CIR_TCIOA_PAR); +#undef PRINTINTR +#endif + + /* + * XXX + * The MACH source had this, with the comment: + * This is wrong, but machine keeps dying. + */ + DELAY(1); + + return (1); +} + +void +tcds_params(sc, chip, idp, fastp) + struct tcds_softc *sc; + int chip, *idp, *fastp; +{ + int id, fast; + u_int32_t ids; + +#ifdef __alpha__ + if (sc->sc_flags & TCDSF_BASEBOARD) { + extern u_int8_t dec_3000_scsiid[], dec_3000_scsifast[]; + + id = dec_3000_scsiid[chip]; + fast = dec_3000_scsifast[chip]; + } else +#endif /* __alpha__ */ + { + /* + * SCSI IDs are stored in the EEPROM, along with whether or + * not the device is "fast". Chip 0 is the high nibble, + * chip 1 the low nibble. + */ + ids = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_EEPROM_IDS); + if (chip == 0) + ids >>= 4; + + id = ids & 0x7; + fast = ids & 0x8; + } + + if (id < 0 || id > 7) { + printf("%s: WARNING: bad SCSI ID %d for chip %d, using 7\n", + sc->sc_dv.dv_xname, id, chip); + id = 7; + } + + if (fast) + printf("%s: fast mode set for chip %d\n", + sc->sc_dv.dv_xname, chip); + + *idp = id; + *fastp = fast; +} diff --git a/sys/dev/tc/tcdsreg.h b/sys/dev/tc/tcdsreg.h new file mode 100644 index 00000000000..974f913a7d1 --- /dev/null +++ b/sys/dev/tc/tcdsreg.h @@ -0,0 +1,218 @@ +/* $OpenBSD: tcdsreg.h,v 1.1 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: tcdsreg.h,v 1.1 2000/07/04 02:22:20 nisimura Exp $ */ + +/* + * Copyright (c) 1994, 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Authors: Keith Bostic, Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * Offsets to the SCSI chips + */ +#define TCDS_SCSI0_OFFSET 0x080000 +#define TCDS_SCSI1_OFFSET 0x080100 + +/* + * TCDS register offsets, bit masks. + */ +#define TCDS_EEPROM 0x000000 /* EEPROM offset */ +#define TCDS_EEPROM_IDS 0x000008 /* SCSI IDs offset in EEPROM */ + +#define TCDS_CIR 0x040000 /* CIR offset */ + +/* + * TCDS CIR control bits. + */ +#define TCDS_CIR_GPO_0 0x00000001 /* Not used */ +#define TCDS_CIR_GPO_1 0x00000002 /* Not used */ +#define TCDS_CIR_GPO_2 0x00000004 /* Not used */ +#define TCDS_CIR_STD 0x00000008 /* Serial transmit disable */ +#define TCDS_CIR_GPI_0 0x00000010 /* Not used */ +#define TCDS_CIR_GPI_1 0x00000020 /* Not used */ +#define TCDS_CIR_GPI_2 0x00000040 /* 1 = 25MHz, 0 = 40MHz */ +#define TCDS_CIR_GPI_3 0x00000080 /* Not used */ +#define TCDS_CIR_SCSI0_DMAENA 0x00000100 /* SCSI 0 DMA enable */ +#define TCDS_CIR_SCSI1_DMAENA 0x00000200 /* SCSI 1 DMA enable */ +#define TCDS_CIR_SCSI0_RESET 0x00000400 /* SCSI 0 reset */ +#define TCDS_CIR_SCSI1_RESET 0x00000800 /* SCSI 1 reset */ +#define TCDS_CIR_SCSI0_DMA_TEST 0x00001000 /* SCSI 0 DMA buf parity test */ +#define TCDS_CIR_SCSI1_DMA_TEST 0x00002000 /* SCSI 1 DMA buf parity test */ +#define TCDS_CIR_DB_PAR 0x00004000 /* DB parity test mode */ +#define TCDS_CIR_TC_PAR 0x00008000 /* TC parity test mode */ +#define TCDS_CIR_ALLCONTROL 0x0000ffff /* all control bits */ + +/* TCDS CIR interrupt bits. */ +#define TCDS_CIR_SCSI0_DREQ 0x00010000 /* SCSI 0 DREQ */ +#define TCDS_CIR_SCSI1_DREQ 0x00020000 /* SCSI 1 DREQ */ +#define TCDS_CIR_SCSI0_INT 0x00040000 /* SCSI 0 interrupt */ +#define TCDS_CIR_SCSI1_INT 0x00080000 /* SCSI 1 interrupt */ +#define TCDS_CIR_SCSI0_PREFETCH 0x00100000 /* SCSI 0 prefetch */ +#define TCDS_CIR_SCSI1_PREFETCH 0x00200000 /* SCSI 1 prefetch */ +#define TCDS_CIR_SCSI0_DMA 0x00400000 /* SCSI 0 DMA error */ +#define TCDS_CIR_SCSI1_DMA 0x00800000 /* SCSI 1 DMA error */ +#define TCDS_CIR_SCSI0_DB 0x01000000 /* SCSI 0 DB parity */ +#define TCDS_CIR_SCSI1_DB 0x02000000 /* SCSI 1 DB parity */ +#define TCDS_CIR_SCSI0_DMAB_PAR 0x04000000 /* SCSI 0 DMA buffer parity */ +#define TCDS_CIR_SCSI1_DMAB_PAR 0x08000000 /* SCSI 1 DMA buffer parity */ +#define TCDS_CIR_SCSI0_DMAR_PAR 0x10000000 /* SCSI 0 DMA read parity */ +#define TCDS_CIR_SCSI1_DMAR_PAR 0x20000000 /* SCSI 1 DMA read parity */ +#define TCDS_CIR_TCIOW_PAR 0x40000000 /* TC I/O write parity */ +#define TCDS_CIR_TCIOA_PAR 0x80000000 /* TC I/O address parity */ +#define TCDS_CIR_ALLINTR 0xffff0000 /* all interrupt bits */ + +#define TCDS_CIR_CLR(c, b) c = ((c | TCDS_CIR_ALLINTR) & ~b) +#define TCDS_CIR_SET(c, b) c = ((c | TCDS_CIR_ALLINTR) | b) + +/* TCDS IMER masks and enables, for interrupts in the CIR. */ +#define TCDS_IMER_SCSI0_MASK 0x04 /* SCSI 0 intr/enable mask */ +#define TCDS_IMER_SCSI1_MASK 0x08 /* SCSI 1 intr/enable mask */ +#define TCDS_IMER_SCSI0_ENB (TCDS_IMER_SCSI0_MASK << 16) +#define TCDS_IMER_SCSI1_ENB (TCDS_IMER_SCSI1_MASK << 16) +#define TCDS_IMER 0x040004 /* IMER offset */ + +#define TCDS_SCSI0_DMA_ADDR 0x041000 /* DMA address */ +#define TCDS_SCSI0_DMA_INTR 0x041004 /* DMA interrupt control */ +#define TCDS_SCSI0_DMA_DUD0 0x041008 /* DMA unaligned data[0] */ +#define TCDS_SCSI0_DMA_DUD1 0x04100c /* DMA unaligned data[1] */ + +#define TCDS_SCSI1_DMA_ADDR 0x041100 /* DMA address */ +#define TCDS_SCSI1_DMA_INTR 0x041104 /* DMA interrupt control */ +#define TCDS_SCSI1_DMA_DUD0 0x041108 /* DMA unaligned data[0] */ +#define TCDS_SCSI1_DMA_DUD1 0x04110c /* DMA unaligned data[1] */ + +#define TCDS_DIC_ADDRMASK 0x03 /* DMA address bits <1:0> */ +#define TCDS_DIC_READ_PREFETCH 0x40 /* DMA read prefetch enable */ +#define TCDS_DIC_WRITE 0x80 /* DMA write */ + +#define TCDS_DUD0_VALID00 0x00000001 /* byte 00 valid mask (zero) */ +#define TCDS_DUD0_VALID01 0x00000002 /* byte 01 valid mask */ +#define TCDS_DUD0_VALID10 0x00000004 /* byte 10 valid mask */ +#define TCDS_DUD0_VALID11 0x00000008 /* byte 11 valid mask */ +#define TCDS_DUD0_VALIDBITS 0x0000000f /* bits that show valid bytes */ + +#define TCDS_DUD1_VALID00 0x01000000 /* byte 00 valid mask */ +#define TCDS_DUD1_VALID01 0x02000000 /* byte 01 valid mask */ +#define TCDS_DUD1_VALID10 0x04000000 /* byte 10 valid mask */ +#define TCDS_DUD1_VALID11 0x08000000 /* byte 11 valid mask (zero) */ +#define TCDS_DUD1_VALIDBITS 0x0f000000 /* bits that show valid bytes */ + +#define TCDS_DUD_BYTE00 0x000000ff /* byte 00 mask */ +#define TCDS_DUD_BYTE01 0x0000ff00 /* byte 01 mask */ +#define TCDS_DUD_BYTE10 0x00ff0000 /* byte 10 mask */ +#define TCDS_DUD_BYTE11 0xff000000 /* byte 11 mask */ + +#if 0 +int tcds_scsi_iserr(struct dma_softc *); +int tcds_scsi_isintr(int, int); +void tcds_dma_disable(int); +void tcds_dma_enable(int); +void tcds_dma_init(struct dma_softc *, int); +void tcds_scsi_disable(int); +void tcds_scsi_enable(int); +void tcds_scsi_reset(int); + +/* + * XXX + * Start of MACH #defines, minimal changes to port to NetBSD. + * + * The following register is the SCSI control interrupt register. It + * starts, stops and resets scsi DMA. It takes over the SCSI funtions + * that were handled by the ASIC on the 3min. + */ +#define KN15AA_SYS_SCSI 0x1d0000000 +#define KN15AA_REG_SCSI_CIR (KN15AA_SYS_SCSI + 0x80000) +#define SCSI_CIR_AIOPAR 0x80000000 /* TC IO Address parity error */ +#define SCSI_CIR_WDIOPAR 0x40000000 /* TC IO write data parity error */ +#define SCSI_CIR_DMARPAR1 0x20000000 /* SCSI[1] TC DMA read data parity */ +#define SCSI_CIR_DMARPAR0 0x10000000 /* SCSI[0] TC DMA read data parity */ +#define SCSI_CIR_DMABUFPAR1 0x08000000 /* SCSI[1] DMA buffer parity error */ +#define SCSI_CIR_DMABUFPAR0 0x04000000 /* SCSI[0] DMA buffer parity error */ +#define SCSI_CIR_DBPAR1 0x02000000 /* SCSI[1] DB parity error */ +#define SCSI_CIR_DBPAR0 0x01000000 /* SCSI[0] DB parity error */ +#define SCSI_CIR_DMAERR1 0x00800000 /* SCSI[1] DMA error */ +#define SCSI_CIR_DMAERR0 0x00400000 /* SCSI[0] DMA error */ +#if fmm50 +#define SCSI_CIR_xxx0 0x00200000 /* RESERVED */ +#define SCSI_CIR_xxx1 0x00100000 /* RESERVED */ +#else +#define SCSI_CIR_PREF1 0x00200000 /* 53C94 prefetch interupt */ +#define SCSI_CIR_PREF0 0x00100000 /* 53C94 prefetch interupt */ +#endif +#define SCSI_CIR_53C94_INT1 0x00080000 /* SCSI[1] 53C94 Interupt */ +#define SCSI_CIR_53C94_INT0 0x00040000 /* SCSI[0] 53C94 Interupt */ +#define SCSI_CIR_53C94_DREQ1 0x00020000 /* SCSI[1] 53C94 DREQ */ +#define SCSI_CIR_53C94_DREQ0 0x00010000 /* SCSI[0] 53C94 DREQ */ +#define SCSI_CIR_TC_PAR_TEST 0x00008000 /* TC parity test mode */ +#define SCSI_CIR_DB_PAR_TEST 0x00004000 /* DB parity test mode */ +#define SCSI_CIR_DBUF_PAR_TEST1 0x00002000 /* SCSI[1] DMA buffer parity test */ +#define SCSI_CIR_DBUF_PAR_TEST0 0x00001000 /* SCSI[0] DMA buffer parity test */ +#define SCSI_CIR_RESET1 0x00000800 /* SCSI[1] ~Reset,enable(0)/disable(1) */ +#define SCSI_CIR_RESET0 0x00000400 /* SCSI[0] ~Reset,enable(0)/disable(1) */ +#define SCSI_CIR_DMAENA1 0x00000200 /* SCSI[1] DMA enable */ +#define SCSI_CIR_DMAENA0 0x00000100 /* SCSI[1] DMA enable */ +#define SCSI_CIR_GPI3 0x00000080 /* General purpose input <3> */ +#define SCSI_CIR_GPI2 0x00000040 /* General purpose input <2> */ +#define SCSI_CIR_GPI1 0x00000020 /* General purpose input <1> */ +#define SCSI_CIR_GPI0 0x00000010 /* General purpose input <0> */ +#define SCSI_CIR_TXDIS 0x00000008 /* TXDIS- serial transmit disable */ +#define SCSI_CIR_GPO2 0x00000004 /* General purpose output <2> */ +#define SCSI_CIR_GPO1 0x00000002 /* General purpose output <1> */ +#define SCSI_CIR_GPO0 0x00000001 /* General purpose output <0> */ +#define SCSI_CIR_ERROR (SCSI_CIR_AIOPAR | SCSI_CIR_WDIOPAR | SCSI_CIR_DMARPAR1 | SCSI_CIR_DMARPAR0 | SCSI_CIR_DMABUFPAR1 | SCSI_CIR_DMABUFPAR0 | SCSI_CIR_DBPAR1 |SCSI_CIR_DBPAR0 | SCSI_CIR_DMAERR1 | SCSI_CIR_DMAERR0 ) + +#define KN15AA_REG_SCSI_DMAPTR0 (KN15AA_SYS_SCSI + 0x82000) +#define KN15AA_REG_SCSI_DMAPTR1 (KN15AA_SYS_SCSI + 0x82200) + +#define KN15AA_REG_SCSI_DIC0 (KN15AA_SYS_SCSI + 0x82008) +#define KN15AA_REG_SCSI_DIC1 (KN15AA_SYS_SCSI + 0x82208) +#define SCSI_DIC_DMADIR 0x00000080 /* DMA direction read(0)/write(1) */ +#define SCSI_DIC_PREFENA 0x00000040 /* DMA read prefetch dis(0)/ena(1) */ +#define SCSI_DIC_DMAADDR1 0x00000002 /* DMA address <1> */ +#define SCSI_DIC_DMAADDR0 0x00000001 /* DMA address <0> */ +#define SCSI_DIC_ADDR_MASK (SCSI_DIC_DMAADDR0 |SCSI_DIC_DMAADDR1) + +#define KN15AA_REG_SCSI_94REG0 (KN15AA_SYS_SCSI + 0x100000) +#define KN15AA_REG_SCSI_94REG1 (KN15AA_SYS_SCSI + 0x100200) + +#define KN15AA_REG_SCSI_IMER (KN15AA_SYS_SCSI + 0x80008) + +/* these are the bits that were unalligned at the beginning of the dma */ +#define KN15AA_REG_SCSI_DUDB0 (KN15AA_SYS_SCSI + 0x82010) +#define KN15AA_REG_SCSI_DUDB1 (KN15AA_SYS_SCSI + 0x82210) +# define SCSI_DUDB_MASK01 0x00000001 /* Mask bit for byte[01] */ +# define SCSI_DUDB_MASK10 0x00000002 /* Mask bit for byte[10] */ +# define SCSI_DUDB_MASK11 0x00000004 /* Mask bit for byte[11] */ + +/* these are the bits that were unalligned at the end of the dma */ +#define KN15AA_REG_SCSI_DUDE0 (KN15AA_SYS_SCSI + 0x82018) +#define KN15AA_REG_SCSI_DUDE1 (KN15AA_SYS_SCSI + 0x82218) +# define SCSI_DUDE_MASK00 0x1000000 /* Mask bit for byte[00] */ +# define SCSI_DUDE_MASK01 0x2000000 /* Mask bit for byte[01] */ +# define SCSI_DUDE_MASK10 0x4000000 /* Mask bit for byte[10] */ + +#define SCSI_CIR ALPHA_PHYS_TO_K0SEG(KN15AA_REG_SCSI_CIR) +#define SCSI_IMER ALPHA_PHYS_TO_K0SEG(KN15AA_REG_SCSI_IMER) + +#endif diff --git a/sys/dev/tc/tcdsvar.h b/sys/dev/tc/tcdsvar.h new file mode 100644 index 00000000000..e1470188d10 --- /dev/null +++ b/sys/dev/tc/tcdsvar.h @@ -0,0 +1,87 @@ +/* $OpenBSD: tcdsvar.h,v 1.1 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: tcdsvar.h,v 1.2 2001/08/22 05:00:27 nisimura Exp $ */ + +/* + * Copyright (c) 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +struct tcds_slotconfig { + /* + * Bookkeeping information + */ + int sc_slot; + + bus_space_tag_t sc_bst; /* to frob TCDS regs */ + bus_space_handle_t sc_bsh; + + int (*sc_intrhand)(void *); /* intr. handler */ + void *sc_intrarg; /* intr. handler arg. */ + struct evcnt sc_evcnt; /* intr. count */ + char sc_name[8]; /* ev_name */ + + /* + * Sets of bits in TCDS CIR and IMER that enable/check + * various things. + */ + u_int32_t sc_resetbits; + u_int32_t sc_intrmaskbits; + u_int32_t sc_intrbits; + u_int32_t sc_dmabits; + u_int32_t sc_errorbits; + + /* + * Offsets to slot-specific DMA resources. + */ + bus_size_t sc_sda; + bus_size_t sc_dic; + bus_size_t sc_dud0; + bus_size_t sc_dud1; +}; + +struct tcdsdev_attach_args { + bus_space_tag_t tcdsda_bst; /* bus space tag */ + bus_space_handle_t tcdsda_bsh; /* bus space handle */ + bus_dma_tag_t tcdsda_dmat; /* bus dma tag */ + struct tcds_slotconfig *tcdsda_sc; /* slot configuration */ + int tcdsda_chip; /* chip number */ + int tcdsda_id; /* SCSI ID */ + u_int tcdsda_freq; /* chip frequency */ + int tcdsda_period; /* min. sync period */ + int tcdsda_variant; /* NCR chip variant */ + int tcdsda_fast; /* chip does Fast mode */ +}; + +/* + * TCDS functions. + */ +void tcds_intr_establish(struct device *, int, + int (*)(void *), void *); +void tcds_intr_disestablish(struct device *, int); +void tcds_dma_enable(struct tcds_slotconfig *, int); +void tcds_scsi_enable(struct tcds_slotconfig *, int); +int tcds_scsi_iserr(struct tcds_slotconfig *); +int tcds_scsi_isintr(struct tcds_slotconfig *, int); +void tcds_scsi_reset(struct tcds_slotconfig *); diff --git a/sys/dev/tc/tcreg.h b/sys/dev/tc/tcreg.h index 7cfe4de700f..115c749953d 100644 --- a/sys/dev/tc/tcreg.h +++ b/sys/dev/tc/tcreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: tcreg.h,v 1.2 1997/11/07 08:07:52 niklas Exp $ */ +/* $OpenBSD: tcreg.h,v 1.3 2002/05/02 22:56:06 miod Exp $ */ /* $NetBSD: tcreg.h,v 1.1 1995/12/20 00:48:36 cgd Exp $ */ /* diff --git a/sys/dev/tc/tcvar.h b/sys/dev/tc/tcvar.h index 9725a823a6d..4c563692a76 100644 --- a/sys/dev/tc/tcvar.h +++ b/sys/dev/tc/tcvar.h @@ -1,5 +1,5 @@ -/* $OpenBSD: tcvar.h,v 1.9 2002/03/14 03:16:08 millert Exp $ */ -/* $NetBSD: tcvar.h,v 1.7 1996/10/22 21:37:31 cgd Exp $ */ +/* $OpenBSD: tcvar.h,v 1.10 2002/05/02 22:56:06 miod Exp $ */ +/* $NetBSD: tcvar.h,v 1.17 2000/06/04 19:15:15 cgd Exp $ */ /* * Copyright (c) 1995 Carnegie-Mellon University. @@ -32,7 +32,7 @@ #define __DEV_TC_TCVAR_H__ /* - * Definitions for TurboChannel autoconfiguration. + * Definitions for TURBOchannel autoconfiguration. */ #include <machine/bus.h> @@ -41,23 +41,16 @@ /* * Machine-dependent definitions. */ -#if !defined(__alpha__) -ERROR: COMPILING FOR UNSUPPORTED MACHINE, OR MORE THAN ONE. -#endif -#ifdef __alpha__ -#include <alpha/tc/tc_machdep.h> -#endif +#include <machine/tc_machdep.h> /* - * In the long run, the following block will go completely away - * (i.e. both parts of the #if, including the #include, etc.). - * For now, the MI TC code still uses the old definitions provided - * by the pmax port, and not the new definitions provided by the - * alpha port. + * In the long run, the following block will go completely away. + * For now, the MI TC code still uses the old TC_IPL_ names + * and not the new IPL_ names. */ -#ifdef __alpha__ +#if 1 /* - * On the alpha, map the new definitions to the old. + * Map the new definitions to the old. */ #include <machine/intr.h> @@ -68,17 +61,28 @@ ERROR: COMPILING FOR UNSUPPORTED MACHINE, OR MORE THAN ONE. #define TC_IPL_NET IPL_NET #define TC_IPL_TTY IPL_TTY #define TC_IPL_CLOCK IPL_CLOCK +#endif /* 1 */ -#endif +struct tc_softc { + struct device sc_dv; + + int sc_speed; + int sc_nslots; + struct tc_slotdesc *sc_slots; + + const struct evcnt *(*sc_intr_evcnt)(struct device *, void *); + void (*sc_intr_establish)(struct device *, void *, + int, int (*)(void *), void *); + void (*sc_intr_disestablish)(struct device *, void *); + bus_dma_tag_t (*sc_get_dma_tag)(int); +}; /* - * Arguments used to attach TurboChannel busses. + * Arguments used to attach TURBOchannel busses. */ struct tcbus_attach_args { char *tba_busname; /* XXX should be common */ -#ifdef __alpha__ /* XXX */ bus_space_tag_t tba_memt; -#endif /* Bus information */ u_int tba_speed; /* see TC_SPEED_* below */ @@ -89,18 +93,19 @@ struct tcbus_attach_args { /* TC bus resource management; XXX will move elsewhere eventually. */ + const struct evcnt *(*tba_intr_evcnt)(struct device *, void *); void (*tba_intr_establish)(struct device *, void *, - tc_intrlevel_t, int (*)(void *), void *); + int, int (*)(void *), void *); void (*tba_intr_disestablish)(struct device *, void *); + bus_dma_tag_t (*tba_get_dma_tag)(int); }; /* - * Arguments used to attach TurboChannel devices. + * Arguments used to attach TURBOchannel devices. */ struct tc_attach_args { -#ifdef __alpha__ /* XXX */ bus_space_tag_t ta_memt; -#endif + bus_dma_tag_t ta_dmat; char ta_modname[TC_ROM_LLEN+1]; u_int ta_slot; @@ -111,8 +116,8 @@ struct tc_attach_args { }; /* - * Description of TurboChannel slots, provided by machine-dependent - * code to the TurboChannel bus driver. + * Description of TURBOchannel slots, provided by machine-dependent + * code to the TURBOchannel bus driver. */ struct tc_slotdesc { tc_addr_t tcs_addr; @@ -121,8 +126,8 @@ struct tc_slotdesc { }; /* - * Description of built-in TurboChannel devices, provided by - * machine-dependent code to the TurboChannel bus driver. + * Description of built-in TURBOchannel devices, provided by + * machine-dependent code to the TURBOchannel bus driver. */ struct tc_builtin { char *tcb_modname; @@ -134,12 +139,16 @@ struct tc_builtin { /* * Interrupt establishment functions. */ -void tc_intr_establish(struct device *, void *, tc_intrlevel_t, - int (*)(void *), void *); +int tc_checkslot(tc_addr_t, char *); +void tc_devinfo(const char *, char *); +void tcattach(struct device *, struct device *, void *); +const struct evcnt *tc_intr_evcnt(struct device *, void *); +void tc_intr_establish(struct device *, void *, int, int (*)(void *), + void *); void tc_intr_disestablish(struct device *, void *); /* - * Easy to remember names for TurboChannel device locators. + * Easy to remember names for TURBOchannel device locators. */ #define tccf_slot cf_loc[0] /* slot */ #define tccf_offset cf_loc[1] /* offset */ @@ -153,10 +162,4 @@ void tc_intr_disestablish(struct device *, void *); #define TC_SPEED_12_5_MHZ 0 /* 12.5MHz TC bus */ #define TC_SPEED_25_MHZ 1 /* 25MHz TC bus */ -/* - * The TurboChannel bus cfdriver, so that subdevices can more - * easily tell what bus they're on. - */ -extern struct cfdriver tc_cd; - #endif /* __DEV_TC_TCVAR_H__ */ |