| Age | Commit message (Expand) | Author |
|---|
| 2018-10-07 | In vmm, handle xsetbv like xrstor: instead of trying to prevalidate | Philip Guenther |
| 2018-10-04 | Use PCIDs where they and the INVPCID instruction are available. | Philip Guenther |
| 2018-10-02 | Unify the MD byteswapping code as much as possible across architectures. | Christian Weisgerber |
| 2018-09-30 | Delete the reserve_dumppages() declaration, missed in its 2010 removal | Philip Guenther |
| 2018-09-22 | Remap the UEFI buffer early such that we can use a write combining mapping | Mark Kettenis |
| 2018-09-20 | vmm(4): Clear the guest MWAITX/MONITORX extended CPUID feature bit, | Bryan Steele |
| 2018-09-12 | Whitespace fixes | Philip Guenther |
| 2018-09-11 | Add defines for amd microcode msrs which appear to be present since k8 | Jonathan Gray |
| 2018-09-05 | Add defines for dealing with PCID support in cr3 | Philip Guenther |
| 2018-08-25 | Define __HAVE_ACPI. | Mark Kettenis |
| 2018-08-21 | Perform mitigations for Intel L1TF screwup. There are three options: | Theo de Raadt |
| 2018-08-20 | Remove unused spllock(). | Visa Hankala |
| 2018-08-19 | Add support for multiple PCI segments. Only really implemented for arm64 | Mark Kettenis |
| 2018-08-15 | add cpuid and msr bits from | Jonathan Gray |
| 2018-08-08 | Recognise 'Speculative Store Bypass Disable' support cpuid bit. | Jonathan Gray |
| 2018-07-27 | Use the MI interrupt enable/distable API instead of the MD one on amd64 and | Mark Kettenis |
| 2018-07-24 | Fix previous commit: the RSB refill bits change %rcx so it needed to be | Philip Guenther |
| 2018-07-24 | Also do RSB refilling when context switching, after vmexits, and | Philip Guenther |
| 2018-07-23 | Add "Mitigation G-2" per AMD's Whitepaper "Software Techniques for | Bryan Steele |
| 2018-07-23 | Do "Return stack refilling", based on the "Return stack underflow" discussion | Philip Guenther |
| 2018-07-21 | Remove the "got meltdown?" conditional from INTRENTRY by doing it | Philip Guenther |
| 2018-07-13 | Disable codepatching infrastructure after boot | Stefan Fritsch |
| 2018-07-12 | zap an extra newline | Mike Larkin |
| 2018-07-12 | Reorganize the Meltdown entry and exit trampolines for syscall and | Philip Guenther |
| 2018-07-12 | vmm(8)/vmm(4): send a copy of the guest register state to vmd on exit, | Mike Larkin |
| 2018-07-11 | Declare cpu_meltdown in <machine/cpu.h> | Philip Guenther |
| 2018-07-11 | vmm(4): return proper cache topology for cpuid(0x4) | Mike Larkin |
| 2018-07-10 | In asm.h ensure NENTRY uses the old-school nop-sled align, but change standard | Theo de Raadt |
| 2018-07-10 | Drop the ignored selectors (tf_[defg]s) from the trap and interrupt frames. | Philip Guenther |
| 2018-07-09 | Delete the VM86 kernel option and i386_vm86(3) API: it's required | Philip Guenther |
| 2018-07-09 | Use a slightly more efficient zeroing idiom when clearing GPRs | Philip Guenther |
| 2018-07-06 | Split trap() into kerntrap() and usertrap(), with all the signal generation | Philip Guenther |
| 2018-07-05 | forgot to commit vmmvar.h needed by previous two commits, thanks ccardenas | Mike Larkin |
| 2018-07-04 | Properly pass around the PCI "chipset tag" in acpi(4) and refactor | Mark Kettenis |
| 2018-07-03 | Make intrframe the exact same size as trapframe: instead of pushing | Philip Guenther |
| 2018-07-03 | add amd speculation control cpuid bits | Jonathan Gray |
| 2018-07-01 | Update IDTVEC, KIDTVEC, and KUENTRY to align with _ALIGN_TRAPS instead of | Philip Guenther |
| 2018-07-01 | Add retguard asm macros. | mortimer |
| 2018-07-01 | Provide _ALIGN_TRAPS macro for text alignment with a trap-sled, then | Philip Guenther |
| 2018-06-30 | Add intr_enable() function, intended for MI use to amd64 and i386 and use | Mark Kettenis |
| 2018-06-24 | Move signal generation from fputrap() to where it's called in trap() | Philip Guenther |
| 2018-06-21 | Save and restore retguard area during hibernate unpack. This copies the | Mike Larkin |
| 2018-06-19 | SMT (Simultanious Multi Threading) implementations typically share | Mark Kettenis |
| 2018-06-14 | Clear the GPRs when entering the kernel from userspace so that | Philip Guenther |
| 2018-06-10 | Put the register-saving parts of INTRENTRY() into their own macros for | Philip Guenther |
| 2018-06-09 | Move all the DDBPROF logic into the trap03 (#BP) handler to keep alltraps | Philip Guenther |
| 2018-06-07 | Apply the retpoline transformation to indirect jumps in the raw ASM | Philip Guenther |
| 2018-06-07 | Treat XSAVEOPT and other XSAVE extensions like other cpu flags | Philip Guenther |
| 2018-06-05 | Switch from lazy FPU switching to semi-eager FPU switching: track whether | Philip Guenther |
| 2018-05-26 | Initialize ci_idle_pcb->pcb_cr0 just once, in cpu_attach(). | Philip Guenther |
