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path: root/sys/arch/arm/include
AgeCommit message (Expand)Author
2017-01-06there is no longer a need to ifdef __armv7__ armv6 rev instructionsJonathan Gray
2017-01-06unifdef CPU_ARMv7 and ARM_ARCH_7Jonathan Gray
2017-01-05Complete idle PCB allocation for secondary processors so that it makesPatrick Wildt
2017-01-04unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)Jonathan Gray
2017-01-01recognise Cortex A32Jonathan Gray
2016-12-30Remove unused headers.Jeremie Courreges-Anglas
2016-10-22If an Access Flag fault happens while we were running the kernel andPatrick Wildt
2016-10-05Some device trees use 64-bit intermediate virtual addresses. ThisPatrick Wildt
2016-10-02The userspace TCB_GET() shouldn't take an argumentPhilip Guenther
2016-09-24Stick the thread control block pointer into a CPU register on ARMv7.Patrick Wildt
2016-09-24If the value of r0 upon entering the kernel is zero, interpret this as theMark Kettenis
2016-09-21Modernize arm assembly in the kernel for clang.Mark Kettenis
2016-09-16Define PT_ARM_EXIDX.Mark Kettenis
2016-09-03Increase the number of mbufs on most architectures. This is basedAlexander Bluhm
2016-08-27Add support for the PXN bit in level 1 translation table descriptors andMark Kettenis
2016-08-26Implement bus dma support for loading raw mappings so that we can usePatrick Wildt
2016-08-26Remove the code that switches around MMU domains on armv7. MMU domains areMark Kettenis
2016-08-25Enable the UWXN bit in the SCTRL register when available. This shouldMark Kettenis
2016-08-24Replace pmap_fault_fixup() with an access flag fault handler on armv7.Mark Kettenis
2016-08-22Before pmap7.c rev 1.35 and pmap.h rev 1.44 DMA'able memory with theJonathan Gray
2016-08-20Don't set MSGBUFSIZE here such that the setting in <machine/param.h> takesMark Kettenis
2016-08-19Start using to XN flag to enforce that mappings without PROT_EXEC areMark Kettenis
2016-08-19Adjust the definitions of L1_S_COHERENT_v7, L2_L_COHERENT_v7 andMark Kettenis
2016-08-19Use Access Flag to do page reference emulation.Mark Kettenis
2016-08-18Separate out the Access Flag bit from the Access Permission bits in theMark Kettenis
2016-08-14Remove code for Intel 80219/80321 xscale processors used by armish.Jonathan Gray
2016-08-14Fix setting the SMP bit in the Auxiliary Control Register. The old code wasMark Kettenis
2016-08-10Add defines for the Access Flag as found on armv7. Fix definition of theMark Kettenis
2016-08-10Shuffle armv7 access permission bits around to something that is compatibleMark Kettenis
2016-08-08Mapping non-cachable memory as cachable and subsequently changing the mappingMark Kettenis
2016-08-07Add XOR cookies for lr and sp. Stop saving/restoring r12 to/from the jmpbuf.Philip Guenther
2016-08-06Put page tables in normal cachable memory on armv7. Check if the MMU walksMark Kettenis
2016-07-31Recognise Cortex A35 and Cortex A73.Jonathan Gray
2016-07-31Instead of testing MIDR values for every model of Cortex processor checkJonathan Gray
2016-07-27Instead of passing the raw reg property to simplebus nodes,Patrick Wildt
2016-07-13The "#address-cells" and "#size-cells" properties define the sizePatrick Wildt
2016-06-09Fetch "reg" and "interrupts" properties and pass them down as attach args toMark Kettenis
2016-05-27Remove the non ELF macrosTheo de Raadt
2016-05-21Implement openprom(4) for armv7.Mark Kettenis
2016-05-16Implement membar(9) for armv5. As there are no barrier instructions inJonathan Gray
2016-05-10SROP mitigation. sendsig() stores a (per-process ^ &sigcontext) cookieTheo de Raadt
2016-05-04Initial support for MSI-X. Only supported on amd64 for now. I have diffs toMark Kettenis
2016-05-02Rework mainbus and implement simplebus to be able to span a tree-likePatrick Wildt
2016-04-27G/C DDB_REGS.Martin Pieuchot
2016-04-25Implement atomic operations using the atomic instructions availablePatrick Wildt
2016-04-25Add macros to access cp14/cp15 registers by name instead of sixJonathan Gray
2016-04-24whitespace cleanupPatrick Wildt
2016-04-24EABI's Procedure Call Standard (AAPCS) requires the stack pointerPatrick Wildt
2016-04-04Store curcpu pointer in TPIDRPRW.Patrick Wildt
2016-04-04Read cache line sizes from CP15 Cache Type Register.Patrick Wildt
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