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path: root/sys/arch/arm64/arm64
AgeCommit message (Expand)Author
2021-06-29whitespaceMark Kettenis
2021-06-28delete .align inside sigtramp stubs, as the stack alignment requirementTheo de Raadt
2021-06-10recognise Cortex-A510, Cortex-A710 and Cortex-X2Jonathan Gray
2021-05-30Include <sys/mutex.h> to avoid a hidden header dependency.Visa Hankala
2021-05-21Fix some comments and use pmap_pte_insert() to update PTEs instead ofMark Kettenis
2021-05-17Rename some MD structs by giving them an architecture-neutral name inMark Kettenis
2021-05-16Drop PTE check in pmap_fault_fixup(). Since pmap_enter() doesn'tMark Kettenis
2021-05-16panic does not require a \n at the end. When one is provided, it looks wrong.Theo de Raadt
2021-05-16remove unneeded includesJonathan Gray
2021-05-16b_saveaddr has a type of void * use NULL not 0Jonathan Gray
2021-05-16ansiJonathan Gray
2021-05-15Use intr_enable()/int_disable()/intr_restore() instead ofMark Kettenis
2021-05-13Make memreg_add() a bit smarter and have it merge adjacent regions.Mark Kettenis
2021-05-12Build a list of memory regions and call yvm_physload(9) on those likeMark Kettenis
2021-05-05Unlock top part of the fault handler.Martin Pieuchot
2021-05-02Initialize per-CPU pointer register earlier.Mark Kettenis
2021-04-26remove unused cdev definesJonathan Gray
2021-04-02Fix Dale's email addressTheo Buehler
2021-03-27Make sure that all CPUs end up with the same bits set in SCTLR_EL1.Mark Kettenis
2021-03-27Add ARMv8.5 instruction set related CPU features.Mark Kettenis
2021-03-17Add missing memory clobbers to "data" barriers.Mark Kettenis
2021-03-16acpi_intr_disestablish() should free its own cookie.Patrick Wildt
2021-03-16Fix some correctness issues in the lowelevel kernel bringup code.Mark Kettenis
2021-03-15Add code to acpiiort(4) to look up named components in the IORT andPatrick Wildt
2021-03-15Add acpi_iommu_device_map(), which replaces the DMA tag with one thatPatrick Wildt
2021-03-13We can use memory marked as EfiBootServicesCode or EfiBootServicesDataMark Kettenis
2021-03-11spellingJonathan Gray
2021-03-10Let MAIR comment catch up with reality.Mark Kettenis
2021-03-09Recognize Apple Firestorm cores.Mark Kettenis
2021-03-08Revise the ASID allocation sheme to avoid a hang when running out of freeMark Kettenis
2021-03-04Turns out the cores on Apple's M1 SoC only support 8-bit ASIDs.Mark Kettenis
2021-03-04Print feature that indicates a CPU core supports 16-bit ASIDs.Mark Kettenis
2021-03-03Remove bogus (and pointless) pmap_activate(9) call.Mark Kettenis
2021-02-21Add cryptox(4), a driver for armv8 cryptographic extensions.tobhe
2021-02-21One CPUs that implement the VHE extension and have the E2H bit set, keepMark Kettenis
2021-02-17Add support for FIQs. We need these to support agtimer(4) on Apple M1 SoCsMark Kettenis
2021-02-16Introduce BUS_SPACE_MAP_POSTED such that we can distinguish betweenMark Kettenis
2021-02-11Call exuart(4) early attach on arm64.Patrick Wildt
2021-02-10Add a instruction barrier between writing CCSELR_EL1 and reading CCSIDR_EL1Mark Kettenis
2021-01-29recognise Cortex-A78CJonathan Gray
2021-01-26Recognize Apple Icestorm cores.Mark Kettenis
2021-01-25Give machdep.c a thorough cleanup that is long overdue.Mark Kettenis
2021-01-23introduce ujoy(4), a restricted subset of uhid(4) for gamecontrollers.thfr
2020-12-19Apply r1.86 of amd64 acpi_machdep.c to arm64 and i386, converting a fewJonathan Matthew
2020-12-09Remove redundant TLB flush. All callers of pmap_pte_remove() were alreadyMark Kettenis
2020-12-06Implement acpi_intr_disestablish() for arm64.Mark Kettenis
2020-12-04Recognize Neoverse-N2.Mark Kettenis
2020-11-22ARM64's bus dma coalesces segments when they are physically contiguous,Patrick Wildt
2020-11-20Restructure cache flush operations to avoid repeated barriers. SpecificallyPatrick Wildt
2020-11-15Add support for edge-triggered interrupts in acpi_intr_establish(). SoPatrick Wildt
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