| Age | Commit message (Expand) | Author |
|---|
| 2016-12-17 | Make Octeon model strings a bit more specific. While there, | Visa Hankala |
| 2016-12-16 | Provide the "machdep.lidsuspend" sysctl on Loongson. | Frederic Cambus |
| 2016-08-14 | Utilize the TLB Execute-Inhibit bit with non-executable mappings on CPUs | Visa Hankala |
| 2016-03-06 | Rename mips64's trap_frame into trapframe. | Martin Pieuchot |
| 2016-03-01 | guard macro args with parens | mmcc |
| 2016-01-05 | Some implementations of HitSyncDCache() call pmap_extract() for va->pa | Visa Hankala |
| 2015-12-25 | Make interrupt masking MP-aware. Linux IP27 and IP35 ports served as a | Visa Hankala |
| 2015-09-23 | That PICA reference ought to have been removed 20 years ago! | Miod Vallat |
| 2015-07-02 | introduce srp, which according to the manpage i wrote is short for | David Gwynne |
| 2015-02-11 | no md code wants lockmgr locks, so no md code needs to include sys/lock.h | David Gwynne |
| 2014-08-14 | fixed overrid(d)en typo | Tobias Stoeckmann |
| 2014-07-11 | CPU_BUSY_CYCLE(): A new MI statement for busy loop power reduction | Masao Uebayashi |
| 2014-04-04 | Second step of the R4000 EOP errata WAR: when pmap invalidates a page which | Miod Vallat |
| 2014-03-31 | Due the virtually indexed nature of the L1 instruction cache on most mips | Miod Vallat |
| 2014-03-29 | It's been a quarter century: we can assume volatile is present with that name. | Philip Guenther |
| 2014-03-22 | Second draft of my attempt to workaround the infamous R4000 end-of-page errata, | Miod Vallat |
| 2014-03-21 | Rename db_inst_type() into classify_insn() and make that function available | Miod Vallat |
| 2014-03-09 | Rework the per-cpu cache information. Use a common struct to store the line | Miod Vallat |
| 2013-12-19 | recognize octeon 2 cpus; as found in the lanner mr326 | Jasper Lievisse Adriaanse |
| 2013-03-12 | Fix kernel profiling on MP systems by using per-CPU buffers and teach | Martin Pieuchot |
| 2013-02-12 | Back out per-CPU kernel profiling, it shouldn't modify a public header | Martin Pieuchot |
| 2013-02-11 | Fix kernel profiling on MP systems by using per-CPU buffer. Previously | Martin Pieuchot |
| 2012-12-02 | Determine whether we're currently on the alternative signal stack | Philip Guenthe |
| 2012-10-03 | Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs, | Miod Vallat |
| 2012-09-29 | Basic R8000 processor support. R8000 processors require MMU-specific code, | Miod Vallat |
| 2012-09-29 | Forgot this in previous commit | Miod Vallat |
| 2012-09-29 | Handle the coprocessor 0 cause and status registers as a 64 bit value now, | Miod Vallat |
| 2012-09-29 | Add a few more coprocessor 0 cause and config registers defines. | Miod Vallat |
| 2012-09-29 | Kill the mostly unused VMTLB_xxx and VMNUM_xxx defines. Move all tlb | Miod Vallat |
| 2012-09-29 | Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions of | Miod Vallat |
| 2012-07-14 | Split the existing mips64 clock code into time-of-day and generic duties in | Miod Vallat |
| 2012-06-24 | Add cache operation functions pointers to struct cpu_info; the various | Miod Vallat |
| 2012-05-27 | Add a `L2 cache line size' member to struct cpu_info. This allows R4k code to | Miod Vallat |
| 2012-04-19 | Print the currently active ASID in `machine tlb' ddb command. | Miod Vallat |
| 2012-04-06 | Make the logic for PMAP_PREFER() and the logic, inside pmap, to do the | Miod Vallat |
| 2012-03-28 | Work in progress support for the SGI Indigo, Indigo 2 and Indy systems | Miod Vallat |
| 2012-03-25 | Move cache handling routines related definitions to a dedicated header file, | Miod Vallat |
| 2012-03-24 | The various ConfigCache() functions actually return void, not int. | Miod Vallat |
| 2012-03-24 | Add a few trivial routines to get mips64r2 specific config registers. Not used | Miod Vallat |
| 2012-03-19 | Use uncached addresses for all exception vectors, when copying our code (or | Miod Vallat |
| 2012-03-15 | uncached_base was introduced early in IP27 support, since these designs use | Miod Vallat |
| 2011-06-24 | machdep.kbdreset enables a shutdown by Ctrl-Alt-Del on amd64 and | Christian Weisgerber |
| 2011-03-31 | Recognize Loongson 3A processors, but don't accept to run on them yet, the | Miod Vallat |
| 2011-03-23 | Normalize sentinel. Use _MACHINE_*_H_ and _<ARCH>_*_H_ properly and consitently. | Paul Irofti |
| 2010-11-24 | Floating-point emulation code for systems lacking proper FPU (i.e. Octeon), | Miod Vallat |
| 2010-10-24 | Move build_trampoline() and setregs() to a common location for all mips ports. | Miod Vallat |
| 2010-10-02 | Added octeon specific cop0 registers. ok miod@ | Takuya ASADA |
| 2010-09-28 | Implement a per-cpu held mutex counter if DIAGNOSTIC on all non-x86 platforms, | Miod Vallat |
| 2010-09-21 | Replace the old floating point completion code with a C interface to the | Miod Vallat |
| 2010-09-20 | cache operations for octeon. ok miod@ | Takuya ASADA |
