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path: root/sys/arch/riscv64
AgeCommit message (Expand)Author
2022-02-18Add mpfgpio(4), a driver for the PolarFire SoC MSS GPIO controller.Visa Hankala
2022-02-16Add mpfiic(4), a driver for the PolarFire SoC MSS I2C controller.Visa Hankala
2022-01-18Add cdsdhc(4), a driver for the Cadence SD/SDIO/eMMC host controller.Visa Hankala
2022-01-18plic: Fix cpuid handlingVisa Hankala
2022-01-17sfcc: Fix accidental spinningVisa Hankala
2022-01-16remove "for all AArch64 platforms" from commentJonathan Gray
2022-01-12Remove -target riscv64-unknown-openbsd from CMACHFLAGS.Kevin Lo
2022-01-07.glue_7 is used for arm code calling thumb code, and .glue_7t is used forKevin Lo
2022-01-05Add mpfclock(4), a driver for the PolarFire SoC MSS clock controller.Visa Hankala
2022-01-03SOCs -> SoCsVisa Hankala
2022-01-03Don't use != 0 to check whether a pointer is non-NULL.Jonathan Gray
2022-01-02addres -> addressJonathan Gray
2022-01-02establush -> establishJonathan Gray
2022-01-01Remove unused function prototype.Mark Kettenis
2022-01-01Add missing locking to pmap_extract(9) and pmap_unwire(9).Mark Kettenis
2021-12-17Disable a few warning flags that were introduced and enabled by defaultPatrick Wildt
2021-12-11remove unused variable to fix build with llvm 13; ok jca@Christian Weisgerber
2021-12-09We only have one syscall table: inline sysent/SYS_MAXSYSCALL andPhilip Guenther
2021-11-30enable uhid/fidoTheo de Raadt
2021-11-27stop building kernels with -Wno-uninitialized on clang archsJonathan Gray
2021-11-26avoid clang -Wsometimes-uninitialized warning when MULTIPROCESSOR is notJonathan Gray
2021-11-14Make sure efiboot is built with RELA/REL relocations and not RELR,Philip Guenther
2021-11-11Retire switch(4) it never really was production ready and the OpenFlowClaudio Jeker
2021-10-26Remove more occurences of O_RDONLY in our bootloaders.Patrick Wildt
2021-10-06Change sendsig() interface so that the MD code does not need to accessClaudio Jeker
2021-10-05cleanup conf.c, and bring in wd(4) supportTheo de Raadt
2021-09-14Cleanup some style issues and remove some unused code. In particular,Mark Kettenis
2021-09-14Provide instruction cache invalidation through sysarch(RISCV_ICACHE_SYNC)Jeremie Courreges-Anglas
2021-09-03Zap a chatty printfJeremie Courreges-Anglas
2021-09-03Don't pretend we support PT_STEP on this architecture.Jeremie Courreges-Anglas
2021-09-03Enable ptrace(2) support for PT_GETFPREGS/PT_SETFPREGSJeremie Courreges-Anglas
2021-09-02add aq(4) to amd64 RAMDISK_CD and riscv64 RAMDISKMike Larkin
2021-09-02aq(4) driver for Aquantia 1/2.5/5/10Gb/s PCIe ethernet adaptersMike Larkin
2021-08-31Using suser() instead of doing it manually.Jan Klemkow
2021-08-30Remove typedef of db_addr_t; mpi converted the users of it to vaddr_t alreadyJasper Lievisse Adriaanse
2021-08-02Add memory barrier (data FENCE) before making the SBI call to issue aMark Kettenis
2021-07-30Use inline function for SFENCE.VMA instruction. Fixes missing "memory"Mark Kettenis
2021-07-30Cleanup ptrace-related code; still untested.Mark Kettenis
2021-07-26Print a few more registers in dump_regs().Mark Kettenis
2021-07-25enable iwm(4)Jonathan Gray
2021-07-25enable ix(4)Jonathan Gray
2021-07-24riscv64 userland timecounter supportJeremie Courreges-Anglas
2021-07-24Implement a workaround for the SiFive FU740 CIP-1200 errata.Mark Kettenis
2021-07-23Use 8/4/1 bytes loads/stores for copyin/copyout/kcopyJeremie Courreges-Anglas
2021-07-12Add uaudio(4) and umidi(4). ok kettenis@, mlarkin@Matthieu Herrb
2021-07-11convert db_addr_t to vaddr_tJasper Lievisse Adriaanse
2021-07-10tweak indentation of conditional in db_validate_address().Jasper Lievisse Adriaanse
2021-07-09use vaddr_t as type for frames as is commonly used elsewhere tooJasper Lievisse Adriaanse
2021-07-06Shifts (<<) of more than 32 bits must be done on 64-bit values.Patrick Wildt
2021-07-02Remove bogus comments.Mark Kettenis
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