| Age | Commit message (Expand) | Author |
|---|
| 2024-08-06 | The devicetree spec says in section 2.4: | Mark Kettenis |
| 2024-07-14 | Add elf_aux_info(3) | Jeremie Courreges-Anglas |
| 2024-06-30 | we don't need the NOBYFOUR space-savings option anymore, that codepath | Theo de Raadt |
| 2024-06-26 | return type on a dedicated line when declaring functions | Jonathan Gray |
| 2024-06-23 | If an ioctl(2) request isn't implemented we should return ENOTTY. | Mark Kettenis |
| 2024-06-23 | Fix previous commit; add missing label | Mark Kettenis |
| 2024-06-20 | Instead of allocating an arbitrary amount of extra space, let the EFI | Mark Kettenis |
| 2024-06-17 | KNF | Mark Kettenis |
| 2024-06-17 | When loading a device tree using the "mach dtb" command, give firmware | Mark Kettenis |
| 2024-06-11 | Enable UVM percpu cache on riscv64 | Jeremie Courreges-Anglas |
| 2024-06-11 | Clamp CPU clock frequencies to [min, max] range when determining the | Mark Kettenis |
| 2024-06-11 | remove drm prototypes duplicating those in sys/conf.h | Jonathan Gray |
| 2024-05-22 | remove prototypes with no matching function and externs with no var | Jonathan Gray |
| 2024-05-13 | remove prototypes with no matching function | Jonathan Gray |
| 2024-04-30 | remove commented DEBUG_TIMER for timer driver removed in 2021 | Jonathan Gray |
| 2024-04-29 | remove prototypes for removed functions | Jonathan Gray |
| 2024-04-29 | remove unused pmap_vp_remove() | Jonathan Gray |
| 2024-04-19 | Fix typo in comment | Jeremie Courreges-Anglas |
| 2024-04-07 | The RISC-V architecture has cache-coherent DMA... until it doesn't. This | Mark Kettenis |
| 2024-04-06 | Now that we support RISC-V CPUs that have MMUs with memory cachability | Mark Kettenis |
| 2024-03-31 | Enable rge(4). | Mark Kettenis |
| 2024-03-29 | Use SBI calls to reboot or power down the machine when the firmware | Mark Kettenis |
| 2024-03-27 | The RISC-V architecture specification says that memory read/writes are | Mark Kettenis |
| 2024-03-26 | The devicetree standard allows for multiple /memory nodes, each with | Mark Kettenis |
| 2024-03-26 | Implement support for the RISC-V UEFI Boot Protocol. This provides us | Mark Kettenis |
| 2024-03-25 | Add missing SFENCE.VMA instructions after switching page tables during | Mark Kettenis |
| 2024-03-07 | Enable dwxe(4) | Kevin Lo |
| 2024-02-25 | clockintr: rename "struct clockintr_queue" to "struct clockqueue" | Scott Soule Cheloha |
| 2024-02-23 | ddb(4): db_read_bytes/db_write_bytes: change dst/src parameter to void* | Scott Soule Cheloha |
| 2024-02-21 | revert r1.35 | David Gwynne |
| 2024-02-21 | handle /reserved-memory nodes from device trees on arm64. | David Gwynne |
| 2024-02-17 | Add JH7100 I2C clocks. | Mark Kettenis |
| 2024-02-03 | Implement Multiple Message MSI support on arm64. As on amd64 this is | Mark Kettenis |
| 2024-02-02 | Enable sximmc(4) | Mark Kettenis |
| 2024-01-27 | Add a few drivers to support Allwinner D1. | Mark Kettenis |
| 2024-01-27 | On Allwinner D1, the SBI call to schedule timer interrupts doesn't work. | Mark Kettenis |
| 2024-01-26 | Recognize the T-Head PLIC implementation. | Mark Kettenis |
| 2024-01-26 | Implement T-Head cache management operations which are needed to handle | Mark Kettenis |
| 2024-01-24 | clockintr: switch from callee- to caller-allocated clockintr structs | Scott Soule Cheloha |
| 2024-01-24 | Remove atomic_store_64(), misleading and now unused | Jeremie Courreges-Anglas |
| 2024-01-23 | T-Head implemented a page attribute extension that violates the RISC-V | Mark Kettenis |
| 2024-01-11 | Since no system call takes more than 6 arguments, and no more than one | Miod Vallat |
| 2024-01-01 | Move fdt attachment into sys/conf/files.conf instead of duplicating it on | Mark Kettenis |
| 2023-12-14 | NKMEMPAGES_MAX_DEFAULT is no longer used. Remove it from param.h. | Claudio Jeker |
| 2023-12-13 | Implement per-CPU caching for the page table page (vp) pool and the PTE | Jeremie Courreges-Anglas |
| 2023-12-13 | Fix syscall number bounds check computations. | Miod Vallat |
| 2023-12-12 | remove support for syscall(2) -- the "indirection system call" because | Theo de Raadt |
| 2023-12-12 | The sigtramp was calling sigreturn(2), and upon failure exit(2), which | Theo de Raadt |
| 2023-12-11 | Implement per-CPU caching for the page table page (vp) pool and the PTE | Mark Kettenis |
| 2023-12-10 | Add a new label "sigcodecall" inside every sigtramp definition, directly | Theo de Raadt |
