| Age | Commit message (Expand) | Author |
|---|---|---|
| 2012-05-12 | It turns out that, when the IRIX header files mention CTR/DCD/DTR/RTS wiring | Miod Vallat |
| 2012-04-29 | Recognize 85230 chips, and take advantage of their FIFOs to reduce the | Miod Vallat |
| 2012-04-29 | I am not sure what the mess with the wiring of carrier lines on Indigo resolves | Miod Vallat |
| 2012-04-18 | One more routine needed to cope for CTS and DCD being inverted on IP20. | Miod Vallat |
| 2012-04-15 | Provide an hpc_intr_establish() function for hpc subdevices, so they don't | Miod Vallat |
| 2012-04-05 | Lower ZS_DELAY() back to what it was, but issue a bus_space_barrier() after | Miod Vallat |
| 2012-04-01 | Increase delay between chip register accesses. Fixes the console freeze during | Miod Vallat |
| 2012-03-31 | softintr_establish() takes IPL_xxx, not SI_xxx (harmless here since they turned | Miod Vallat |
| 2012-03-28 | Work in progress support for the SGI Indigo, Indigo 2 and Indy systems | Miod Vallat |
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index : src | |
| OpenBSD base system |
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