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2018-02-24Enable bcmtemp(4).Mark Kettenis
2018-02-24Make ncpusfound count the available processors even if they don't attach.Mark Kettenis
ok patrick@
2018-02-23Disable mailbox interrupts on all cores upon attach instead of enabling theMark Kettenis
mailbox 0 interrupt on all cores. Seems to make GENERIC.MP work on the rpi3.
2018-02-23Get rid of the cpu_on_fn hook and call the psci(4) functions directly insteadMark Kettenis
like we already do in the code that flushes the BTB. ok jsg@
2018-02-23Drop redundant bzero() calls. ses_ghash is allocated with M_ZERO, soVisa Hankala
it is unnecessary to zero the struct's fields right after allocation. OK mikeb@
2018-02-22Set the PG_G (global) bit on the special page table entries that are sharedPhilip Guenther
between the u-k and u+k tables, because they're actually in *all* tables. ok bluhm@ kettenis@ mlarkin@
2018-02-22The compile time assertion for cpu info did not work with gcc.Alexander Bluhm
Rephrase the condition in a way that both gcc and clang accept it. OK guenther@
2018-02-22The GNU assembler does not understand 1ULL, so replace the constantAlexander Bluhm
with 1. Then it compiles with gcc, sign and size do not matter here. OK mlarkin@
2018-02-21Mark VIA padlock as capable of dealing with ESNMike Belopuhov
There are no actual changes to the driver since the software crypto driver is called to handle authentication operations. This enabled padlock to be used when tunnels are setup with iked(8). Tested by and OK fcambus
2018-02-21Meltdown: implement user/kernel page table separation.Philip Guenther
On Intel CPUs which speculate past user/supervisor page permission checks, use a separate page table for userspace with only the minimum of kernel code and data required for the transitions to/from the kernel (still marked as supervisor-only, of course): - the IDT (RO) - three pages of kernel text in the .kutext section for interrupt, trap, and syscall trampoline code (RX) - one page of kernel data in the .kudata section for TLB flush IPIs (RW) - the lapic page (RW, uncachable) - per CPU: one page for the TSS+GDT (RO) and one page for trampoline stacks (RW) When a syscall, trap, or interrupt takes a CPU from userspace to kernel the trampoline code switches page tables, switches stacks to the thread's real kernel stack, then copies over the necessary bits from the trampoline stack. On return to userspace the opposite occurs: recreate the iretq frame on the trampoline stack, switch stack, switch page tables, and return to userspace. mlarkin@ implemented the pmap bits and did 90% of the debugging, diagnosing issues on MP in particular, and drove the final push to completion. Many rounds of testing by naddy@, sthen@, and others Thanks to Alex Wilson from Joyent for early discussions about trampolines and their data requirements. Per-CPU page layout mostly inspired by DragonFlyBSD. ok mlarkin@ deraadt@
2018-02-20Add GENERIC.MP directory.Mark Kettenis
2018-02-20Add GENERIC.MP.Mark Kettenis
2018-02-20Release the secondary CPUs.Mark Kettenis
2018-02-20Make arm64 pmap (somewhat) mpsafe.Mark Kettenis
2018-02-20Convert key length from bits to bytesMike Belopuhov
Reported by Renaud Allard, fix tested by Renaud (i386) and fcambus@ (amd64). OK visa, fcambus
2018-02-19Convert sparc64 to MI mutex.Martin Pieuchot
ok dlg@
2018-02-19Remove almost unused `flags' argument of suser().Martin Pieuchot
The account flag `ASU' will no longer be set but that makes suser() mpsafe since it no longer mess with a per-process field. No objection from millert@, ok tedu@, bluhm@
2018-02-18Inline hw_{get,set}curcpu() to streamline the machine code.Visa Hankala
2018-02-18Replace a full memory barrier with a write-write barrier. The fullVisa Hankala
barrier is overkill when forcing parameter visibility before IPIs.
2018-02-18document "machine video"; requested by tinkerJason McIntyre
while here, put "directory" in the right place
2018-02-17Rename memhook to vmmap to match other archs.Mark Kettenis
ok millert@
2018-02-16Add sizes for free() in the i386 version of the Enhanced SpeedStep driver.Frederic Cambus
It was already done on amd64, but not on i386. Tested on an Atom N270. OK mpi@
2018-02-16Support card interrupts in imxesdhc(4). The code that was writtenPatrick Wildt
initially was never tested with SDIO, as there had been no user. With bwfm(4) we now have the first SDIO card on that controller. Align the code with the standard sdhc(4), so that it doesn't hang after the first interrupt fires. ok kettenis@
2018-02-15use the arm64 openprom.c on arm64Jonathan Gray
ok patrick@
2018-02-14prune files.* entries that refer to files not in treeJonathan Gray
ok krw@ mpi@
2018-02-12Typo in a comment (CR$_VMXE instead of CR4_VMXE). No functional change.Mike Larkin
2018-02-11Move .openbsd.randomdata into .rodata. This makes things morePatrick Wildt
consistent across architectures. Requested by deraadt@ ok kettenis@
2018-02-11Rework the DDB trace handling for armv7. By switching to clang thePatrick Wildt
stack frame format has changed. Apparently AAPCS doesn't specify at all what a stack frame looks like. We end up with much simpler code, but also with a lot less information in the trace. ok kettenis@
2018-02-11Move landisk to MI mutex.Martin Pieuchot
ok dlg@
2018-02-10Enable axppmic(4).Mark Kettenis
2018-02-10Convert armv7 to MI mutex.Martin Pieuchot
Tested by jsg@, ok patrick@
2018-02-10Revert previous & incorrect NULL dereference fix.Martin Pieuchot
This unbreak backtrace across interrupt frames.
2018-02-10Replace two spaces indents with tabs. Makes it easier to read andPatrick Wildt
especially makes it easier to diff against our other linker scripts. ok jsg@
2018-02-10Additional AMD CPUID bits documented inJonathan Gray
"Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors" ok mlarkin@ deraadt@
2018-02-10Remove now unused assembly mutex code.Martin Pieuchot
ok mlarkin@, deraadt@
2018-02-10Supplying entropy from etext has created a regression on arm where wePatrick Wildt
get an alignment fault while copying the data. Turns out that since we have .rodata in the text segment, it's very easily possible that etext remains unaligned. Work around this by word-aligning etext. The next step is to split .rodata out of the text segment. ok deraadt@
2018-02-10Put the ldscript parts into a single file instead of storing it as headPatrick Wildt
and tail and cat(1) it together. It was maybe needed when ports needed different contents, but now it's just a headache. ok deraadt@
2018-02-10Add a mapping from grandparent driver name to hibernate io function to reduceJonathan Matthew
the number of ->dv_parent->dv_parent chains and make this more readable. ok deraadt@ phessler@
2018-02-09Check for the existence of /bsd before trying to back it up to /obsd.Theo Buehler
Fixes 'make install' when /bsd is not present for some reason. ok rob florian, "fine with me" deraadt
2018-02-07Reporting the PXE boot interface we identified is independent of settingChristian Weisgerber
the boot device. We do the latter only for NFSCLIENT, but always the former. While here, modernize the interface matching loop. ok deraadt@
2018-02-07Use M_WAITOK to show we don't need to check for NULL.Kenneth R Westerback
ok deraadt@
2018-02-06Allow the kernel to recognize that it has been netbooted and to add theChristian Weisgerber
boot interface to the "netboot" group. efiboot grabs the MAC address from the PXE environment, passes it to the kernel, where it is matched against the list of ethernet interfaces and the boot device is set. Concept and most of the code cribbed from amd64. ok kettenis@
2018-02-06Make sure sigfillsiz is word aligned.Patrick Wildt
ok kettenis@
2018-02-06Load the Intel microcode much earlier. So far we had loaded it afterPatrick Wildt
the CPUs identified and then we had to update the CPU flags afterwards. As microcode updates can add/remove instructions and features, we need to load it earlier. Thus, make the bootloader look for the microcode and supply it to the kernel as another bootarg. This way we can update the cores' microcode before we identify them. ok deraadt@
2018-02-02Enable interrupts in (synchronous) trap handlers.Mark Kettenis
ok patrick@
2018-02-02Enable interrupts while running interrupt handlers like we do on agintc(4).Mark Kettenis
Spotted by patrick@ ok patrick@
2018-02-02vmm: add support for send / receive for AMD SVM hostspd
ok mlarkin@
2018-02-01handle ramdisk not containing ddb, so that builds can proceedTheo de Raadt
2018-01-31Make sure each CPU uses its own set of VAs for pmap_zero_page() andMark Kettenis
pmap_copy_page(). ok patrick@
2018-01-31Add MULTIPROCESSOR support to the interrupt controller drivers. This makesMark Kettenis
the secondary CPUs receive clock interrupts. Based on diffs from drahn@. ok patrick@
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