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path: root/sys/dev/fdt
AgeCommit message (Expand)Author
2023-04-07print which gmac the dwqe driver is attaching to.David Gwynne
2023-04-07Determine PHY mode and pass the appropriate flags down to the PHY when weMark Kettenis
2023-04-07register a mapping of dwqe interfaces to ofw nodes/phandles.David Gwynne
2023-04-06Add two more RK3568 clocks.Mark Kettenis
2023-04-06The simplebus_attach() function already prints a newline, so drop it here.Mark Kettenis
2023-04-06better handle "phy-mode" properties, in particular around clk delays.David Gwynne
2023-04-05Call dwpcie_link_config() when initializing the RK3568 PCIe controllers.Mark Kettenis
2023-04-04Synopsis Designware -> Synopsys DesignWareJonathan Gray
2023-04-03try using a standard phy drivers registered with ofw/fdt first.David Gwynne
2023-04-03add support for enabling both the usb2 and usb3 phys.David Gwynne
2023-04-03register mvneta so the interface can be found by node/phandle later.David Gwynne
2023-04-03do actual init of the phy itself when needed.David Gwynne
2023-04-02add rkusbphy(4), a driver for the usb2phy on rockchip SoCs.David Gwynne
2023-04-01Add rkiovd(4), a driver for the IO voltage domains on Rockchip SoCs. ThisMark Kettenis
2023-03-31Flip label separators to fix previousKlemens Nanni
2023-03-30keep match strings sortedKlemens Nanni
2023-03-30Attach Baikal-M PCIeKlemens Nanni
2023-03-26Aparantly we must configure the RGMII interface (and possible the TX/RXMark Kettenis
2023-03-26Add support for the RK3568 32k RTC clock. This clock uses a fractionalMark Kettenis
2023-03-25The "snps,reset-*" properties are deprecatedand are being replaced withMark Kettenis
2023-03-23correct rk3308 clk_32k_sel maskJonathan Gray
2023-03-19Add rkpciephy(4), ad friver for the PCIe 3.0 PHY dound on the RK356x.Mark Kettenis
2023-03-19improve dmesg output to help with debugging.David Gwynne
2023-03-19Add a few more RK3568 clocks.Mark Kettenis
2023-03-19Use a task to switch clocks on RK3568 as the clock API needs process context.Mark Kettenis
2023-03-16Add code to bring up the PCIe controller on the RK356x.Mark Kettenis
2023-03-16Add missing dependecy for rkcomphy(4); pointed out by dlg@Mark Kettenis
2023-03-12Add rkcomphy(3), a driver for the "naneng" combo PHY found on the RK356xMark Kettenis
2023-03-12Match on the Armada 380 temperature sensor, which works the same as theJonathan Matthew
2023-03-10Implement setting the parent clock for RK356x. This includes code forMark Kettenis
2023-03-10Take controller out of reset; makes it work on rk356x.Mark Kettenis
2023-03-07Add some minimal initialization code for rk356x such that the kernelMark Kettenis
2023-03-05Mask off IPL flags before storing the IPL for an interrupt.Patrick Wildt
2023-03-05Add RK356x-specific initialization. Also initialize a few auto modeMark Kettenis
2023-03-04Turns out the RK3566 has a different value in the GPIO_VER_ID registerMark Kettenis
2023-03-04On RK356x many devices need to be explicitly routed to use alternative pinMark Kettenis
2023-02-27Pass MII flags depending on the phy mode specified in the device tree.Jonathan Matthew
2023-02-26Defragment mbufs in the tx path to work around a (not fully understood)Mark Kettenis
2023-02-26RK3588 support.Mark Kettenis
2023-02-26Modern Rockchip SoCs, such as the RK356x and RK3588, use a differentMark Kettenis
2023-02-19Add support for deep(er) idle states that can be entered using PSCI. ForMark Kettenis
2023-02-15Don't print the version twice, but do print a newline before attaching theMark Kettenis
2023-02-15Add GMAC-related RK356x clocks.Mark Kettenis
2023-02-14Fix scmi(4) entry.Mark Kettenis
2023-02-13Add a driver for the ARM System Control and Management Interface, which,Mark Kettenis
2023-02-13Add RK356x TSADC clocks.Mark Kettenis
2023-02-13Add dwqe(4), a driver for the Synopsis DesignWare Ethernet QoS controllerPatrick Wildt
2023-02-13Add support for the Shenzhen Tangcheng Technology TCS4525 voltageMark Kettenis
2023-02-04Set default volume to -30 dB instead of using the hardware default of 0 dBMark Kettenis
2023-02-04Set default volume to -30 dB instead of using the hardware default of 0 dBMark Kettenis