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AgeCommit message (Expand)Author
2020-12-29Handle pinctrl.Mark Kettenis
2020-12-29Add more PWM pin descriptions.Mark Kettenis
2020-12-28Analog to the the kern.audio.record sysctl parameter for audio(4)Marcus Glocker
2020-12-28Add support for the PCIe controller found on Amlogic G12A/G12B/SM1 SoCs.Mark Kettenis
2020-12-28regenMark Kettenis
2020-12-28Add Synopsys vendor and their DesignWare PCIe bridge.Mark Kettenis
2020-12-27acpi_map_address() cannot be wrapped by SMALL_KERNEL anymore, asTheo de Raadt
2020-12-27Remove debug printf.Mark Kettenis
2020-12-27Add PCIe support.Mark Kettenis
2020-12-27Add PCIe power domain.Mark Kettenis
2020-12-27have mcx_process_txeof return the number of slots it processed.David Gwynne
2020-12-27do a bus space barrier after arming the eq.David Gwynne
2020-12-27disable timestamping a little bit harder to avoid divide by 0.David Gwynne
2020-12-27shuffle filling the rx ring so the sw prod is updated before the hw.David Gwynne
2020-12-26reuse the calculated vector as the argument to pci_intr_map_msix.David Gwynne
2020-12-26add bus_dmamap_sync ops around the eq.David Gwynne
2020-12-26add some bus_dmamap_syncs around the rq.David Gwynne
2020-12-26sprinkle some bus_dmamap_syncs around the cq handling.David Gwynne
2020-12-26sprinkle some bus_dmamap_syncs around the sq.David Gwynne
2020-12-26better manage the lifetime of the dmamem used for various rings.David Gwynne
2020-12-26sdmmc(4): sdmmc_io_function_enable(): don't sleep on lboltcheloha
2020-12-25expose the mcx timer as a timecounter.David Gwynne
2020-12-25match on Gemini Lake I2CJonathan Gray
2020-12-25Refactor klist insertion and removalVisa Hankala
2020-12-24Do proper accounting of zero length TDs. Currently a specific numberMarcus Glocker
2020-12-24Extract clock frequency from _DSD properties.Patrick Wildt
2020-12-24Implement capability register overrides based on _DSD properties.Mark Kettenis
2020-12-24regenJonathan Gray
2020-12-24add some NVMe devices and Intel Comet Lake host bridgesJonathan Gray
2020-12-24ramdisks do not contain WOLTheo de Raadt
2020-12-24Add Wake on LAN support to rge(4).Kevin Lo
2020-12-23Fix regulators that use "active-low" polarity. Our implementation nowMark Kettenis
2020-12-22have the ifrxr info stuff report the buffer size the hw handles.David Gwynne
2020-12-22Add PCIe clocks.Mark Kettenis
2020-12-22Defer hardware initialization in order to give things like PCIe PHYsMark Kettenis
2020-12-22name the rx rings like ix does for systat mbDavid Gwynne
2020-12-21Only enable rasops1_putchar8() and rasops1_putchar16() optomizations onMark Kettenis
2020-12-20sync with i915_pciids.hJonathan Gray
2020-12-20drm/i915: Remove dubious Valleyview PCI IDsJonathan Gray
2020-12-20remove duplicate device id caused by subids in INTEL_IVB_Q_IDSJonathan Gray
2020-12-20test against [VM_MIN_ADDRESS, VM_MAXUSER_ADDRESS] in access_ok()Jonathan Gray
2020-12-19There's no need to include the OFW GPIO header.Patrick Wildt
2020-12-19Add support for the i.MX8MP PCIe clocks.Patrick Wildt
2020-12-18Add support for the i.MX8MP second ethernet. The Plus SoC not only has thePatrick Wildt
2020-12-18Emulate open drain GPIOs. This replaces the hack added in the last commit.Mark Kettenis
2020-12-18Add symbolic constants related to open source and open drain GPIOs.Mark Kettenis
2020-12-18Make large read and write transactions work.Mark Kettenis
2020-12-18Add glue for the USB3 controller on the i.MX8MP SoC. NXP had this glue forPatrick Wildt
2020-12-18Add code to initialize the USB 3 PHY on i.MX8MP.Patrick Wildt
2020-12-18Add support for the i.MX8MP USB clocks.Patrick Wildt